riscv: Add SW single-step support for KDB
In KGDB, the GDB in the host is responsible for the single-step operation of the software. In other words, KGDB does not need to derive the next pc address when performing a software single-step operation. KGDB just inserts the break instruction at the indicated address according to the GDB instructions. This approach does not work in KDB because the GDB does not involve the KDB process. Therefore, this patch provides KDB a software single-step mechanism to use. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Vincent Chen
Palmer Dabbelt
parent
d96575709c
commit
edde5584c7
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@ -0,0 +1,219 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2020 SiFive
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*/
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#include <linux/bits.h>
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/* The bit field of immediate value in I-type instruction */
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#define I_IMM_SIGN_OPOFF 31
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#define I_IMM_11_0_OPOFF 20
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#define I_IMM_SIGN_OFF 12
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#define I_IMM_11_0_OFF 0
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#define I_IMM_11_0_MASK GENMASK(11, 0)
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/* The bit field of immediate value in J-type instruction */
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#define J_IMM_SIGN_OPOFF 31
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#define J_IMM_10_1_OPOFF 21
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#define J_IMM_11_OPOFF 20
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#define J_IMM_19_12_OPOFF 12
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#define J_IMM_SIGN_OFF 20
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#define J_IMM_10_1_OFF 1
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#define J_IMM_11_OFF 11
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#define J_IMM_19_12_OFF 12
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#define J_IMM_10_1_MASK GENMASK(9, 0)
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#define J_IMM_11_MASK GENMASK(0, 0)
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#define J_IMM_19_12_MASK GENMASK(7, 0)
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/* The bit field of immediate value in B-type instruction */
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#define B_IMM_SIGN_OPOFF 31
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#define B_IMM_10_5_OPOFF 25
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#define B_IMM_4_1_OPOFF 8
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#define B_IMM_11_OPOFF 7
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#define B_IMM_SIGN_OFF 12
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#define B_IMM_10_5_OFF 5
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#define B_IMM_4_1_OFF 1
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#define B_IMM_11_OFF 11
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#define B_IMM_10_5_MASK GENMASK(5, 0)
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#define B_IMM_4_1_MASK GENMASK(3, 0)
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#define B_IMM_11_MASK GENMASK(0, 0)
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/* The register offset in RVG instruction */
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#define RVG_RS1_OPOFF 15
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#define RVG_RS2_OPOFF 20
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#define RVG_RD_OPOFF 7
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/* The bit field of immediate value in RVC J instruction */
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#define RVC_J_IMM_SIGN_OPOFF 12
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#define RVC_J_IMM_4_OPOFF 11
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#define RVC_J_IMM_9_8_OPOFF 9
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#define RVC_J_IMM_10_OPOFF 8
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#define RVC_J_IMM_6_OPOFF 7
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#define RVC_J_IMM_7_OPOFF 6
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#define RVC_J_IMM_3_1_OPOFF 3
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#define RVC_J_IMM_5_OPOFF 2
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#define RVC_J_IMM_SIGN_OFF 11
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#define RVC_J_IMM_4_OFF 4
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#define RVC_J_IMM_9_8_OFF 8
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#define RVC_J_IMM_10_OFF 10
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#define RVC_J_IMM_6_OFF 6
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#define RVC_J_IMM_7_OFF 7
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#define RVC_J_IMM_3_1_OFF 1
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#define RVC_J_IMM_5_OFF 5
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#define RVC_J_IMM_4_MASK GENMASK(0, 0)
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#define RVC_J_IMM_9_8_MASK GENMASK(1, 0)
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#define RVC_J_IMM_10_MASK GENMASK(0, 0)
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#define RVC_J_IMM_6_MASK GENMASK(0, 0)
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#define RVC_J_IMM_7_MASK GENMASK(0, 0)
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#define RVC_J_IMM_3_1_MASK GENMASK(2, 0)
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#define RVC_J_IMM_5_MASK GENMASK(0, 0)
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/* The bit field of immediate value in RVC B instruction */
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#define RVC_B_IMM_SIGN_OPOFF 12
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#define RVC_B_IMM_4_3_OPOFF 10
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#define RVC_B_IMM_7_6_OPOFF 5
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#define RVC_B_IMM_2_1_OPOFF 3
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#define RVC_B_IMM_5_OPOFF 2
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#define RVC_B_IMM_SIGN_OFF 8
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#define RVC_B_IMM_4_3_OFF 3
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#define RVC_B_IMM_7_6_OFF 6
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#define RVC_B_IMM_2_1_OFF 1
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#define RVC_B_IMM_5_OFF 5
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#define RVC_B_IMM_4_3_MASK GENMASK(1, 0)
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#define RVC_B_IMM_7_6_MASK GENMASK(1, 0)
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#define RVC_B_IMM_2_1_MASK GENMASK(1, 0)
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#define RVC_B_IMM_5_MASK GENMASK(0, 0)
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/* The register offset in RVC op=C0 instruction */
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#define RVC_C0_RS1_OPOFF 7
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#define RVC_C0_RS2_OPOFF 2
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#define RVC_C0_RD_OPOFF 2
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/* The register offset in RVC op=C1 instruction */
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#define RVC_C1_RS1_OPOFF 7
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#define RVC_C1_RS2_OPOFF 2
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#define RVC_C1_RD_OPOFF 7
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/* The register offset in RVC op=C2 instruction */
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#define RVC_C2_RS1_OPOFF 7
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#define RVC_C2_RS2_OPOFF 2
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#define RVC_C2_RD_OPOFF 7
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/* parts of opcode for RVG*/
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#define OPCODE_BRANCH 0x63
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#define OPCODE_JALR 0x67
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#define OPCODE_JAL 0x6f
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#define OPCODE_SYSTEM 0x73
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/* parts of opcode for RVC*/
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#define OPCODE_C_0 0x0
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#define OPCODE_C_1 0x1
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#define OPCODE_C_2 0x2
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/* parts of funct3 code for I, M, A extension*/
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#define FUNCT3_JALR 0x0
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#define FUNCT3_BEQ 0x0
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#define FUNCT3_BNE 0x1000
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#define FUNCT3_BLT 0x4000
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#define FUNCT3_BGE 0x5000
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#define FUNCT3_BLTU 0x6000
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#define FUNCT3_BGEU 0x7000
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/* parts of funct3 code for C extension*/
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#define FUNCT3_C_BEQZ 0xc000
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#define FUNCT3_C_BNEZ 0xe000
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#define FUNCT3_C_J 0xa000
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#define FUNCT3_C_JAL 0x2000
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#define FUNCT4_C_JR 0x8000
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#define FUNCT4_C_JALR 0xf000
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#define FUNCT12_SRET 0x10200000
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#define MATCH_JALR (FUNCT3_JALR | OPCODE_JALR)
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#define MATCH_JAL (OPCODE_JAL)
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#define MATCH_BEQ (FUNCT3_BEQ | OPCODE_BRANCH)
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#define MATCH_BNE (FUNCT3_BNE | OPCODE_BRANCH)
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#define MATCH_BLT (FUNCT3_BLT | OPCODE_BRANCH)
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#define MATCH_BGE (FUNCT3_BGE | OPCODE_BRANCH)
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#define MATCH_BLTU (FUNCT3_BLTU | OPCODE_BRANCH)
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#define MATCH_BGEU (FUNCT3_BGEU | OPCODE_BRANCH)
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#define MATCH_SRET (FUNCT12_SRET | OPCODE_SYSTEM)
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#define MATCH_C_BEQZ (FUNCT3_C_BEQZ | OPCODE_C_1)
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#define MATCH_C_BNEZ (FUNCT3_C_BNEZ | OPCODE_C_1)
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#define MATCH_C_J (FUNCT3_C_J | OPCODE_C_1)
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#define MATCH_C_JAL (FUNCT3_C_JAL | OPCODE_C_1)
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#define MATCH_C_JR (FUNCT4_C_JR | OPCODE_C_2)
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#define MATCH_C_JALR (FUNCT4_C_JALR | OPCODE_C_2)
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#define MASK_JALR 0x707f
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#define MASK_JAL 0x7f
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#define MASK_C_JALR 0xf07f
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#define MASK_C_JR 0xf07f
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#define MASK_C_JAL 0xe003
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#define MASK_C_J 0xe003
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#define MASK_BEQ 0x707f
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#define MASK_BNE 0x707f
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#define MASK_BLT 0x707f
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#define MASK_BGE 0x707f
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#define MASK_BLTU 0x707f
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#define MASK_BGEU 0x707f
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#define MASK_C_BEQZ 0xe003
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#define MASK_C_BNEZ 0xe003
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#define MASK_SRET 0xffffffff
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#define __INSN_LENGTH_MASK _UL(0x3)
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#define __INSN_LENGTH_GE_32 _UL(0x3)
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#define __INSN_OPCODE_MASK _UL(0x7F)
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#define __INSN_BRANCH_OPCODE _UL(OPCODE_BRANCH)
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/* Define a series of is_XXX_insn functions to check if the value INSN
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* is an instance of instruction XXX.
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*/
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#define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
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static inline bool is_ ## INSN_NAME ## _insn(long insn) \
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{ \
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return (insn & (INSN_MASK)) == (INSN_MATCH); \
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}
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#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
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#define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
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#define RV_X(X, s, mask) (((X) >> (s)) & (mask))
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#define RVC_X(X, s, mask) RV_X(X, s, mask)
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#define EXTRACT_JTYPE_IMM(x) \
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({typeof(x) x_ = (x); \
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(RV_X(x_, J_IMM_10_1_OPOFF, J_IMM_10_1_MASK) << J_IMM_10_1_OFF) | \
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(RV_X(x_, J_IMM_11_OPOFF, J_IMM_11_MASK) << J_IMM_11_OFF) | \
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(RV_X(x_, J_IMM_19_12_OPOFF, J_IMM_19_12_MASK) << J_IMM_19_12_OFF) | \
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(RV_IMM_SIGN(x_) << J_IMM_SIGN_OFF); })
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#define EXTRACT_ITYPE_IMM(x) \
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({typeof(x) x_ = (x); \
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(RV_X(x_, I_IMM_11_0_OPOFF, I_IMM_11_0_MASK)) | \
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(RV_IMM_SIGN(x_) << I_IMM_SIGN_OFF); })
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#define EXTRACT_BTYPE_IMM(x) \
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({typeof(x) x_ = (x); \
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(RV_X(x_, B_IMM_4_1_OPOFF, B_IMM_4_1_MASK) << B_IMM_4_1_OFF) | \
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(RV_X(x_, B_IMM_10_5_OPOFF, B_IMM_10_5_MASK) << B_IMM_10_5_OFF) | \
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(RV_X(x_, B_IMM_11_OPOFF, B_IMM_11_MASK) << B_IMM_11_OFF) | \
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(RV_IMM_SIGN(x_) << B_IMM_SIGN_OFF); })
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#define EXTRACT_RVC_J_IMM(x) \
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({typeof(x) x_ = (x); \
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(RVC_X(x_, RVC_J_IMM_3_1_OPOFF, RVC_J_IMM_3_1_MASK) << RVC_J_IMM_3_1_OFF) | \
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(RVC_X(x_, RVC_J_IMM_4_OPOFF, RVC_J_IMM_4_MASK) << RVC_J_IMM_4_OFF) | \
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(RVC_X(x_, RVC_J_IMM_5_OPOFF, RVC_J_IMM_5_MASK) << RVC_J_IMM_5_OFF) | \
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(RVC_X(x_, RVC_J_IMM_6_OPOFF, RVC_J_IMM_6_MASK) << RVC_J_IMM_6_OFF) | \
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(RVC_X(x_, RVC_J_IMM_7_OPOFF, RVC_J_IMM_7_MASK) << RVC_J_IMM_7_OFF) | \
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(RVC_X(x_, RVC_J_IMM_9_8_OPOFF, RVC_J_IMM_9_8_MASK) << RVC_J_IMM_9_8_OFF) | \
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(RVC_X(x_, RVC_J_IMM_10_OPOFF, RVC_J_IMM_10_MASK) << RVC_J_IMM_10_OFF) | \
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(RVC_IMM_SIGN(x_) << RVC_J_IMM_SIGN_OFF); })
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#define EXTRACT_RVC_B_IMM(x) \
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({typeof(x) x_ = (x); \
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(RVC_X(x_, RVC_B_IMM_2_1_OPOFF, RVC_B_IMM_2_1_MASK) << RVC_B_IMM_2_1_OFF) | \
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(RVC_X(x_, RVC_B_IMM_4_3_OPOFF, RVC_B_IMM_4_3_MASK) << RVC_B_IMM_4_3_OFF) | \
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(RVC_X(x_, RVC_B_IMM_5_OPOFF, RVC_B_IMM_5_MASK) << RVC_B_IMM_5_OFF) | \
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(RVC_X(x_, RVC_B_IMM_7_6_OPOFF, RVC_B_IMM_7_6_MASK) << RVC_B_IMM_7_6_OFF) | \
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(RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); })
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@ -11,13 +11,179 @@
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#include <linux/string.h>
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#include <asm/cacheflush.h>
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#include <asm/gdb_xml.h>
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#include <asm/parse_asm.h>
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enum {
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NOT_KGDB_BREAK = 0,
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KGDB_SW_BREAK,
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KGDB_COMPILED_BREAK,
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KGDB_SW_SINGLE_STEP
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};
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static unsigned long stepped_address;
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static unsigned int stepped_opcode;
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#if __riscv_xlen == 32
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/* C.JAL is an RV32C-only instruction */
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DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
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#else
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#define is_c_jal_insn(opcode) 0
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#endif
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DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
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DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
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DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
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DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
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DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
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DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
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DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
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DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
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DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
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DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
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DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
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DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
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DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
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DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
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int decode_register_index(unsigned long opcode, int offset)
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{
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return (opcode >> offset) & 0x1F;
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}
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int decode_register_index_short(unsigned long opcode, int offset)
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{
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return ((opcode >> offset) & 0x7) + 8;
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}
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/* Calculate the new address for after a step */
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int get_step_address(struct pt_regs *regs, unsigned long *next_addr)
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{
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unsigned long pc = regs->epc;
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unsigned long *regs_ptr = (unsigned long *)regs;
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unsigned int rs1_num, rs2_num;
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int op_code;
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if (probe_kernel_address((void *)pc, op_code))
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return -EINVAL;
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if ((op_code & __INSN_LENGTH_MASK) != __INSN_LENGTH_GE_32) {
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if (is_c_jalr_insn(op_code) || is_c_jr_insn(op_code)) {
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rs1_num = decode_register_index(op_code, RVC_C2_RS1_OPOFF);
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*next_addr = regs_ptr[rs1_num];
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} else if (is_c_j_insn(op_code) || is_c_jal_insn(op_code)) {
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*next_addr = EXTRACT_RVC_J_IMM(op_code) + pc;
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} else if (is_c_beqz_insn(op_code)) {
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rs1_num = decode_register_index_short(op_code,
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RVC_C1_RS1_OPOFF);
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if (!rs1_num || regs_ptr[rs1_num] == 0)
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*next_addr = EXTRACT_RVC_B_IMM(op_code) + pc;
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else
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*next_addr = pc + 2;
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} else if (is_c_bnez_insn(op_code)) {
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rs1_num =
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decode_register_index_short(op_code, RVC_C1_RS1_OPOFF);
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if (rs1_num && regs_ptr[rs1_num] != 0)
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*next_addr = EXTRACT_RVC_B_IMM(op_code) + pc;
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else
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*next_addr = pc + 2;
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} else {
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*next_addr = pc + 2;
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}
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} else {
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if ((op_code & __INSN_OPCODE_MASK) == __INSN_BRANCH_OPCODE) {
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bool result = false;
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long imm = EXTRACT_BTYPE_IMM(op_code);
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unsigned long rs1_val = 0, rs2_val = 0;
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rs1_num = decode_register_index(op_code, RVG_RS1_OPOFF);
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rs2_num = decode_register_index(op_code, RVG_RS2_OPOFF);
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if (rs1_num)
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rs1_val = regs_ptr[rs1_num];
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if (rs2_num)
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rs2_val = regs_ptr[rs2_num];
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if (is_beq_insn(op_code))
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result = (rs1_val == rs2_val) ? true : false;
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else if (is_bne_insn(op_code))
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result = (rs1_val != rs2_val) ? true : false;
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else if (is_blt_insn(op_code))
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result =
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((long)rs1_val <
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(long)rs2_val) ? true : false;
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else if (is_bge_insn(op_code))
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result =
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((long)rs1_val >=
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(long)rs2_val) ? true : false;
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else if (is_bltu_insn(op_code))
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result = (rs1_val < rs2_val) ? true : false;
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else if (is_bgeu_insn(op_code))
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result = (rs1_val >= rs2_val) ? true : false;
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if (result)
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*next_addr = imm + pc;
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else
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*next_addr = pc + 4;
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} else if (is_jal_insn(op_code)) {
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*next_addr = EXTRACT_JTYPE_IMM(op_code) + pc;
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} else if (is_jalr_insn(op_code)) {
|
||||
rs1_num = decode_register_index(op_code, RVG_RS1_OPOFF);
|
||||
if (rs1_num)
|
||||
*next_addr = ((unsigned long *)regs)[rs1_num];
|
||||
*next_addr += EXTRACT_ITYPE_IMM(op_code);
|
||||
} else if (is_sret_insn(op_code)) {
|
||||
*next_addr = pc;
|
||||
} else {
|
||||
*next_addr = pc + 4;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int do_single_step(struct pt_regs *regs)
|
||||
{
|
||||
/* Determine where the target instruction will send us to */
|
||||
unsigned long addr = 0;
|
||||
int error = get_step_address(regs, &addr);
|
||||
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
/* Store the op code in the stepped address */
|
||||
error = probe_kernel_address((void *)addr, stepped_opcode);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
stepped_address = addr;
|
||||
|
||||
/* Replace the op code with the break instruction */
|
||||
error = probe_kernel_write((void *)stepped_address,
|
||||
arch_kgdb_ops.gdb_bpt_instr,
|
||||
BREAK_INSTR_SIZE);
|
||||
/* Flush and return */
|
||||
if (!error) {
|
||||
flush_icache_range(addr, addr + BREAK_INSTR_SIZE);
|
||||
kgdb_single_step = 1;
|
||||
atomic_set(&kgdb_cpu_doing_single_step,
|
||||
raw_smp_processor_id());
|
||||
} else {
|
||||
stepped_address = 0;
|
||||
stepped_opcode = 0;
|
||||
}
|
||||
return error;
|
||||
}
|
||||
|
||||
/* Undo a single step */
|
||||
static void undo_single_step(struct pt_regs *regs)
|
||||
{
|
||||
if (stepped_opcode != 0) {
|
||||
probe_kernel_write((void *)stepped_address,
|
||||
(void *)&stepped_opcode, BREAK_INSTR_SIZE);
|
||||
flush_icache_range(stepped_address,
|
||||
stepped_address + BREAK_INSTR_SIZE);
|
||||
}
|
||||
stepped_address = 0;
|
||||
stepped_opcode = 0;
|
||||
kgdb_single_step = 0;
|
||||
atomic_set(&kgdb_cpu_doing_single_step, -1);
|
||||
}
|
||||
|
||||
struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = {
|
||||
{DBG_REG_ZERO, GDB_SIZEOF_REG, -1},
|
||||
{DBG_REG_RA, GDB_SIZEOF_REG, offsetof(struct pt_regs, ra)},
|
||||
|
|
@ -135,6 +301,8 @@ int kgdb_arch_handle_exception(int vector, int signo, int err_code,
|
|||
{
|
||||
int err = 0;
|
||||
|
||||
undo_single_step(regs);
|
||||
|
||||
switch (remcom_in_buffer[0]) {
|
||||
case 'c':
|
||||
case 'D':
|
||||
|
|
@ -142,15 +310,20 @@ int kgdb_arch_handle_exception(int vector, int signo, int err_code,
|
|||
if (remcom_in_buffer[0] == 'c')
|
||||
kgdb_arch_update_addr(regs, remcom_in_buffer);
|
||||
break;
|
||||
case 's':
|
||||
kgdb_arch_update_addr(regs, remcom_in_buffer);
|
||||
err = do_single_step(regs);
|
||||
break;
|
||||
default:
|
||||
err = -1;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
int kgdb_riscv_kgdbbreak(unsigned long addr)
|
||||
{
|
||||
if (stepped_address == addr)
|
||||
return KGDB_SW_SINGLE_STEP;
|
||||
if (atomic_read(&kgdb_setting_breakpoint))
|
||||
if (addr == (unsigned long)&kgdb_compiled_break)
|
||||
return KGDB_COMPILED_BREAK;
|
||||
|
|
@ -174,7 +347,9 @@ static int kgdb_riscv_notify(struct notifier_block *self, unsigned long cmd,
|
|||
return NOTIFY_DONE;
|
||||
|
||||
local_irq_save(flags);
|
||||
if (kgdb_handle_exception(1, args->signr, cmd, regs))
|
||||
|
||||
if (kgdb_handle_exception(type == KGDB_SW_SINGLE_STEP ? 0 : 1,
|
||||
args->signr, cmd, regs))
|
||||
return NOTIFY_DONE;
|
||||
|
||||
if (type == KGDB_COMPILED_BREAK)
|
||||
|
|
|
|||
Loading…
Reference in New Issue