bnx2x: add additional regions for CRC memory test
a. Common tree of `dir` structures. b. Multi-port devices structures. CC: Francious Romieu <romieu@fz.zoreil.com> Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Dmitry Kravkov
David S. Miller
parent
f1691dc615
commit
edb944d27b
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@ -850,6 +850,9 @@ struct bnx2x_common {
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#define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF)
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#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
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CHIP_IS_57711E(bp))
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#define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \
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CHIP_IS_57811_MF(bp) || \
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CHIP_IS_57811_VF(bp))
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#define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
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CHIP_IS_57712_MF(bp) || \
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CHIP_IS_57712_VF(bp))
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@ -859,9 +862,7 @@ struct bnx2x_common {
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CHIP_IS_57810(bp) || \
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CHIP_IS_57810_MF(bp) || \
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CHIP_IS_57810_VF(bp) || \
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CHIP_IS_57811(bp) || \
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CHIP_IS_57811_MF(bp) || \
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CHIP_IS_57811_VF(bp) || \
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CHIP_IS_57811xx(bp) || \
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CHIP_IS_57840(bp) || \
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CHIP_IS_57840_MF(bp) || \
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CHIP_IS_57840_VF(bp))
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@ -2595,14 +2595,168 @@ static int bnx2x_test_ext_loopback(struct bnx2x *bp)
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return rc;
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}
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struct code_entry {
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u32 sram_start_addr;
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u32 code_attribute;
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#define CODE_IMAGE_TYPE_MASK 0xf0800003
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#define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003
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#define CODE_IMAGE_LENGTH_MASK 0x007ffffc
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#define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000
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u32 nvm_start_addr;
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};
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#define CODE_ENTRY_MAX 16
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#define CODE_ENTRY_EXTENDED_DIR_IDX 15
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#define MAX_IMAGES_IN_EXTENDED_DIR 64
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#define NVRAM_DIR_OFFSET 0x14
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#define EXTENDED_DIR_EXISTS(code) \
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((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
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(code & CODE_IMAGE_LENGTH_MASK) != 0)
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#define CRC32_RESIDUAL 0xdebb20e3
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#define CRC_BUFF_SIZE 256
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static int bnx2x_nvram_crc(struct bnx2x *bp,
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int offset,
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int size,
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u8 *buff)
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{
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u32 crc = ~0;
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int rc = 0, done = 0;
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DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
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"NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
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while (done < size) {
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int count = min_t(int, size - done, CRC_BUFF_SIZE);
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rc = bnx2x_nvram_read(bp, offset + done, buff, count);
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if (rc)
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return rc;
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crc = crc32_le(crc, buff, count);
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done += count;
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}
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if (crc != CRC32_RESIDUAL)
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rc = -EINVAL;
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return rc;
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}
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static int bnx2x_test_nvram_dir(struct bnx2x *bp,
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struct code_entry *entry,
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u8 *buff)
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{
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size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
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u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
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int rc;
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/* Zero-length images and AFEX profiles do not have CRC */
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if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
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return 0;
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rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
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if (rc)
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DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
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"image %x has failed crc test (rc %d)\n", type, rc);
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return rc;
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}
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static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
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{
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int rc;
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struct code_entry entry;
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rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
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if (rc)
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return rc;
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return bnx2x_test_nvram_dir(bp, &entry, buff);
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}
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static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
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{
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u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
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struct code_entry entry;
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int i;
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rc = bnx2x_nvram_read32(bp,
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dir_offset +
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sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
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(u32 *)&entry, sizeof(entry));
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if (rc)
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return rc;
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if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
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return 0;
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rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
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&cnt, sizeof(u32));
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if (rc)
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return rc;
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dir_offset = entry.nvm_start_addr + 8;
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for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
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rc = bnx2x_test_dir_entry(bp, dir_offset +
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sizeof(struct code_entry) * i,
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buff);
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if (rc)
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return rc;
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}
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return 0;
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}
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static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
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{
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u32 rc, dir_offset = NVRAM_DIR_OFFSET;
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int i;
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DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
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for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
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rc = bnx2x_test_dir_entry(bp, dir_offset +
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sizeof(struct code_entry) * i,
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buff);
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if (rc)
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return rc;
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}
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return bnx2x_test_nvram_ext_dirs(bp, buff);
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}
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struct crc_pair {
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int offset;
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int size;
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};
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static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
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const struct crc_pair *nvram_tbl, u8 *buf)
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{
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int i;
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for (i = 0; nvram_tbl[i].size; i++) {
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int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
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nvram_tbl[i].size, buf);
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if (rc) {
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DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
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"nvram_tbl[%d] has failed crc test (rc %d)\n",
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i, rc);
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return rc;
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}
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}
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return 0;
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}
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static int bnx2x_test_nvram(struct bnx2x *bp)
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{
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static const struct {
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int offset;
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int size;
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} nvram_tbl[] = {
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const struct crc_pair nvram_tbl[] = {
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{ 0, 0x14 }, /* bootstrap */
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{ 0x14, 0xec }, /* dir */
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{ 0x100, 0x350 }, /* manuf_info */
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@ -2611,14 +2765,20 @@ static int bnx2x_test_nvram(struct bnx2x *bp)
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{ 0x708, 0x70 }, /* manuf_key_info */
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{ 0, 0 }
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};
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const struct crc_pair nvram_tbl2[] = {
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{ 0x7e8, 0x350 }, /* manuf_info2 */
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{ 0xb38, 0xf0 }, /* feature_info */
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{ 0, 0 }
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};
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u8 *buf;
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int i, rc;
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u32 magic, crc;
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int rc;
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u32 magic;
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if (BP_NOMCP(bp))
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return 0;
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buf = kmalloc(0x350, GFP_KERNEL);
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buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
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if (!buf) {
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DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
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rc = -ENOMEM;
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@ -2639,25 +2799,26 @@ static int bnx2x_test_nvram(struct bnx2x *bp)
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goto test_nvram_exit;
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}
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for (i = 0; nvram_tbl[i].size; i++) {
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DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
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rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
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if (rc)
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goto test_nvram_exit;
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rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, buf,
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nvram_tbl[i].size);
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if (rc) {
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DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
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"nvram_tbl[%d] read data (rc %d)\n", i, rc);
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goto test_nvram_exit;
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}
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if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
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u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
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SHARED_HW_CFG_HIDE_PORT1;
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crc = ether_crc_le(nvram_tbl[i].size, buf);
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if (crc != CRC32_RESIDUAL) {
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if (!hide) {
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DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
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"nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc);
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rc = -ENODEV;
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goto test_nvram_exit;
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"Port 1 CRC test-set\n");
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rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
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if (rc)
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goto test_nvram_exit;
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}
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}
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rc = bnx2x_test_nvram_dirs(bp, buf);
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test_nvram_exit:
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kfree(buf);
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return rc;
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