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Merge branch 'mellanox/mlx5-next' into rdma.git for-next 

From git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux.git

This is required to resolve dependencies of the next series of RDMA
patches.

* branch 'mellanox/mlx5-next':
  net/mlx5: Add support for flow table destination number
  net/mlx5: Add forward compatible support for the FTE match data
  net/mlx5: Fix tristate and description for MLX5 module
  net/mlx5: Better return types for CQE API
  net/mlx5: Use ERR_CAST() instead of coding it
  net/mlx5: Add missing SET_DRIVER_VERSION command translation
  net/mlx5: Add XRQ commands definitions
  net/mlx5: Add core support for double vlan push/pop steering action
  net/mlx5: Expose MPEGC (Management PCIe General Configuration) structures
  net/mlx5: FW tracer, add hardware structures
  net/mlx5: fix uaccess beyond "count" in debugfs read/write handlers

Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
This commit is contained in:
Jason Gunthorpe 2018-07-24 13:10:23 -06:00
parent 4fca037783 664000b6bb
commit eda98779f7
14 changed files with 166 additions and 149 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/infiniband/hw/mlx5/Kconfig
View File

@ -1,5 +1,5 @@
config MLX5_INFINIBAND
tristate "Mellanox Connect-IB HCA support"
tristate "Mellanox 5th generation network adapters (ConnectX series) support"
depends on NETDEVICES && ETHERNET && PCI && MLX5_CORE
depends on INFINIBAND_USER_ACCESS || INFINIBAND_USER_ACCESS=n
---help---

6
drivers/net/ethernet/mellanox/mlx5/core/Kconfig
View File

@ -3,7 +3,7 @@
#
config MLX5_CORE
tristate "Mellanox Technologies ConnectX-4 and Connect-IB core driver"
tristate "Mellanox 5th generation network adapters (ConnectX series) core driver"
depends on MAY_USE_DEVLINK
depends on PCI
imply PTP_1588_CLOCK
@ -27,7 +27,7 @@ config MLX5_FPGA
sandbox-specific client drivers.
config MLX5_CORE_EN
bool "Mellanox Technologies ConnectX-4 Ethernet support"
bool "Mellanox 5th generation network adapters (ConnectX series) Ethernet support"
depends on NETDEVICES && ETHERNET && INET && PCI && MLX5_CORE
depends on IPV6=y || IPV6=n || MLX5_CORE=m
select PAGE_POOL
@ -69,7 +69,7 @@ config MLX5_CORE_EN_DCB
If unsure, set to Y
config MLX5_CORE_IPOIB
bool "Mellanox Technologies ConnectX-4 IPoIB offloads support"
bool "Mellanox 5th generation network adapters (connectX series) IPoIB offloads support"
depends on MLX5_CORE_EN
default n
---help---

37
drivers/net/ethernet/mellanox/mlx5/core/cmd.c
View File

@ -278,6 +278,7 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
case MLX5_CMD_OP_DESTROY_PSV:
case MLX5_CMD_OP_DESTROY_SRQ:
case MLX5_CMD_OP_DESTROY_XRC_SRQ:
case MLX5_CMD_OP_DESTROY_XRQ:
case MLX5_CMD_OP_DESTROY_DCT:
case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
@ -347,6 +348,9 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
case MLX5_CMD_OP_CREATE_XRC_SRQ:
case MLX5_CMD_OP_QUERY_XRC_SRQ:
case MLX5_CMD_OP_ARM_XRC_SRQ:
case MLX5_CMD_OP_CREATE_XRQ:
case MLX5_CMD_OP_QUERY_XRQ:
case MLX5_CMD_OP_ARM_XRQ:
case MLX5_CMD_OP_CREATE_DCT:
case MLX5_CMD_OP_DRAIN_DCT:
case MLX5_CMD_OP_QUERY_DCT:
@ -456,6 +460,7 @@ const char *mlx5_command_str(int command)
MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
MLX5_COMMAND_STR_CASE(QUERY_ISSI);
MLX5_COMMAND_STR_CASE(SET_ISSI);
MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
MLX5_COMMAND_STR_CASE(CREATE_MKEY);
MLX5_COMMAND_STR_CASE(QUERY_MKEY);
MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
@ -603,6 +608,10 @@ const char *mlx5_command_str(int command)
MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
MLX5_COMMAND_STR_CASE(CREATE_XRQ);
MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
MLX5_COMMAND_STR_CASE(QUERY_XRQ);
MLX5_COMMAND_STR_CASE(ARM_XRQ);
MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT);
@ -1037,7 +1046,10 @@ static ssize_t dbg_write(struct file *filp, const char __user *buf,
if (!dbg->in_msg || !dbg->out_msg)
return -ENOMEM;
if (copy_from_user(lbuf, buf, sizeof(lbuf)))
if (count < sizeof(lbuf) - 1)
return -EINVAL;
if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
return -EFAULT;
lbuf[sizeof(lbuf) - 1] = 0;
@ -1241,21 +1253,12 @@ static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
{
struct mlx5_core_dev *dev = filp->private_data;
struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
int copy;
if (*pos)
return 0;
if (!dbg->out_msg)
return -ENOMEM;
copy = min_t(int, count, dbg->outlen);
if (copy_to_user(buf, dbg->out_msg, copy))
return -EFAULT;
*pos += copy;
return copy;
return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
dbg->outlen);
}
static const struct file_operations dfops = {
@ -1273,19 +1276,11 @@ static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
char outlen[8];
int err;
if (*pos)
return 0;
err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
if (err < 0)
return err;
if (copy_to_user(buf, &outlen, err))
return -EFAULT;
*pos += err;
return err;
return simple_read_from_buffer(buf, count, pos, outlen, err);
}
static ssize_t outlen_write(struct file *filp, const char __user *buf,

22
drivers/net/ethernet/mellanox/mlx5/core/debugfs.c
View File

@ -150,22 +150,13 @@ static ssize_t average_read(struct file *filp, char __user *buf, size_t count,
int ret;
char tbuf[22];
if (*pos)
return 0;
stats = filp->private_data;
spin_lock_irq(&stats->lock);
if (stats->n)
field = div64_u64(stats->sum, stats->n);
spin_unlock_irq(&stats->lock);
ret = snprintf(tbuf, sizeof(tbuf), "%llu\n", field);
if (ret > 0) {
if (copy_to_user(buf, tbuf, ret))
return -EFAULT;
}
*pos += ret;
return ret;
return simple_read_from_buffer(buf, count, pos, tbuf, ret);
}
static ssize_t average_write(struct file *filp, const char __user *buf,
@ -442,9 +433,6 @@ static ssize_t dbg_read(struct file *filp, char __user *buf, size_t count,
u64 field;
int ret;
if (*pos)
return 0;
desc = filp->private_data;
d = (void *)(desc - desc->i) - sizeof(*d);
switch (d->type) {
@ -470,13 +458,7 @@ static ssize_t dbg_read(struct file *filp, char __user *buf, size_t count,
else
ret = snprintf(tbuf, sizeof(tbuf), "0x%llx\n", field);
if (ret > 0) {
if (copy_to_user(buf, tbuf, ret))
return -EFAULT;
}
*pos += ret;
return ret;
return simple_read_from_buffer(buf, count, pos, tbuf, ret);
}
static const struct file_operations fops = {

3
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
View File

@ -240,6 +240,9 @@ const char *parse_fs_dst(struct trace_seq *p,
case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE:
trace_seq_printf(p, "ft=%p\n", dst->ft);
break;
case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM:
trace_seq_printf(p, "ft_num=%u\n", dst->ft_num);
break;
case MLX5_FLOW_DESTINATION_TYPE_TIR:
trace_seq_printf(p, "tir=%u\n", dst->tir_num);
break;

2
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h
View File

@ -138,6 +138,8 @@ TRACE_EVENT(mlx5_fs_del_fg,
{MLX5_FLOW_CONTEXT_ACTION_MOD_HDR, "MOD_HDR"},\
{MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH, "VLAN_PUSH"},\
{MLX5_FLOW_CONTEXT_ACTION_VLAN_POP, "VLAN_POP"},\
{MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2, "VLAN_PUSH_2"},\
{MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2, "VLAN_POP_2"},\
{MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO, "NEXT_PRIO"}
TRACE_EVENT(mlx5_fs_set_fte,

6
drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c
View File

@ -70,9 +70,9 @@ mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
flow_act.vlan.ethtype = ntohs(attr->vlan_proto);
flow_act.vlan.vid = attr->vlan_vid;
flow_act.vlan.prio = attr->vlan_prio;
flow_act.vlan[0].ethtype = ntohs(attr->vlan_proto);
flow_act.vlan[0].vid = attr->vlan_vid;
flow_act.vlan[0].prio = attr->vlan_prio;
}
if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {

36
drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c
View File

@ -349,9 +349,15 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev,
vlan = MLX5_ADDR_OF(flow_context, in_flow_context, push_vlan);
MLX5_SET(vlan, vlan, ethtype, fte->action.vlan.ethtype);
MLX5_SET(vlan, vlan, vid, fte->action.vlan.vid);
MLX5_SET(vlan, vlan, prio, fte->action.vlan.prio);
MLX5_SET(vlan, vlan, ethtype, fte->action.vlan[0].ethtype);
MLX5_SET(vlan, vlan, vid, fte->action.vlan[0].vid);
MLX5_SET(vlan, vlan, prio, fte->action.vlan[0].prio);
vlan = MLX5_ADDR_OF(flow_context, in_flow_context, push_vlan_2);
MLX5_SET(vlan, vlan, ethtype, fte->action.vlan[1].ethtype);
MLX5_SET(vlan, vlan, vid, fte->action.vlan[1].vid);
MLX5_SET(vlan, vlan, prio, fte->action.vlan[1].prio);
in_match_value = MLX5_ADDR_OF(flow_context, in_flow_context,
match_value);
@ -362,18 +368,20 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev,
int list_size = 0;
list_for_each_entry(dst, &fte->node.children, node.list) {
unsigned int id;
unsigned int id, type = dst->dest_attr.type;
if (dst->dest_attr.type == MLX5_FLOW_DESTINATION_TYPE_COUNTER)
if (type == MLX5_FLOW_DESTINATION_TYPE_COUNTER)
continue;
MLX5_SET(dest_format_struct, in_dests, destination_type,
dst->dest_attr.type);
if (dst->dest_attr.type ==
MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
switch (type) {
case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM:
id = dst->dest_attr.ft_num;
type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
break;
case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE:
id = dst->dest_attr.ft->id;
} else if (dst->dest_attr.type ==
MLX5_FLOW_DESTINATION_TYPE_VPORT) {
break;
case MLX5_FLOW_DESTINATION_TYPE_VPORT:
id = dst->dest_attr.vport.num;
MLX5_SET(dest_format_struct, in_dests,
destination_eswitch_owner_vhca_id_valid,
@ -381,9 +389,13 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev,
MLX5_SET(dest_format_struct, in_dests,
destination_eswitch_owner_vhca_id,
dst->dest_attr.vport.vhca_id);
} else {
break;
default:
id = dst->dest_attr.tir_num;
}
MLX5_SET(dest_format_struct, in_dests, destination_type,
type);
MLX5_SET(dest_format_struct, in_dests, destination_id, id);
in_dests += MLX5_ST_SZ_BYTES(dest_format_struct);
list_size++;

87
drivers/net/ethernet/mellanox/mlx5/core/fs_core.c
View File

@ -309,89 +309,17 @@ static struct fs_prio *find_prio(struct mlx5_flow_namespace *ns,
return NULL;
}
static bool check_last_reserved(const u32 *match_criteria)
{
char *match_criteria_reserved =
MLX5_ADDR_OF(fte_match_param, match_criteria, MLX5_FTE_MATCH_PARAM_RESERVED);
return !match_criteria_reserved[0] &&
!memcmp(match_criteria_reserved, match_criteria_reserved + 1,
MLX5_FLD_SZ_BYTES(fte_match_param,
MLX5_FTE_MATCH_PARAM_RESERVED) - 1);
}
static bool check_valid_mask(u8 match_criteria_enable, const u32 *match_criteria)
{
if (match_criteria_enable & ~(
(1 << MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS) |
(1 << MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS) |
(1 << MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS) |
(1 << MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2)))
return false;
if (!(match_criteria_enable &
1 << MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS)) {
char *fg_type_mask = MLX5_ADDR_OF(fte_match_param,
match_criteria, outer_headers);
if (fg_type_mask[0] ||
memcmp(fg_type_mask, fg_type_mask + 1,
MLX5_ST_SZ_BYTES(fte_match_set_lyr_2_4) - 1))
return false;
}
if (!(match_criteria_enable &
1 << MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS)) {
char *fg_type_mask = MLX5_ADDR_OF(fte_match_param,
match_criteria, misc_parameters);
if (fg_type_mask[0] ||
memcmp(fg_type_mask, fg_type_mask + 1,
MLX5_ST_SZ_BYTES(fte_match_set_misc) - 1))
return false;
}
if (!(match_criteria_enable &
1 << MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS)) {
char *fg_type_mask = MLX5_ADDR_OF(fte_match_param,
match_criteria, inner_headers);
if (fg_type_mask[0] ||
memcmp(fg_type_mask, fg_type_mask + 1,
MLX5_ST_SZ_BYTES(fte_match_set_lyr_2_4) - 1))
return false;
}
if (!(match_criteria_enable &
1 << MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2)) {
char *fg_type_mask = MLX5_ADDR_OF(fte_match_param,
match_criteria, misc_parameters_2);
if (fg_type_mask[0] ||
memcmp(fg_type_mask, fg_type_mask + 1,
MLX5_ST_SZ_BYTES(fte_match_set_misc2) - 1))
return false;
}
return check_last_reserved(match_criteria);
}
static bool check_valid_spec(const struct mlx5_flow_spec *spec)
{
int i;
if (!check_valid_mask(spec->match_criteria_enable, spec->match_criteria)) {
pr_warn("mlx5_core: Match criteria given mismatches match_criteria_enable\n");
return false;
}
for (i = 0; i < MLX5_ST_SZ_DW_MATCH_PARAM; i++)
if (spec->match_value[i] & ~spec->match_criteria[i]) {
pr_warn("mlx5_core: match_value differs from match_criteria\n");
return false;
}
return check_last_reserved(spec->match_value);
return true;
}
static struct mlx5_flow_root_namespace *find_root(struct fs_node *node)
@ -1158,9 +1086,6 @@ struct mlx5_flow_group *mlx5_create_flow_group(struct mlx5_flow_table *ft,
struct mlx5_flow_group *fg;
int err;
if (!check_valid_mask(match_criteria_enable, match_criteria))
return ERR_PTR(-EINVAL);
if (ft->autogroup.active)
return ERR_PTR(-EPERM);
@ -1431,7 +1356,9 @@ static bool mlx5_flow_dests_cmp(struct mlx5_flow_destination *d1,
(d1->type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
d1->ft == d2->ft) ||
(d1->type == MLX5_FLOW_DESTINATION_TYPE_TIR &&
d1->tir_num == d2->tir_num))
d1->tir_num == d2->tir_num) ||
(d1->type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM &&
d1->ft_num == d2->ft_num))
return true;
}
@ -1464,7 +1391,9 @@ static bool check_conflicting_actions(u32 action1, u32 action2)
MLX5_FLOW_CONTEXT_ACTION_DECAP |
MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
MLX5_FLOW_CONTEXT_ACTION_VLAN_POP |
MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH))
MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 |
MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2))
return true;
return false;
@ -1823,7 +1752,7 @@ search_again_locked:
g = alloc_auto_flow_group(ft, spec);
if (IS_ERR(g)) {
rule = (void *)g;
rule = ERR_CAST(g);
up_write_ref_node(&ft->node);
return rule;
}

2
drivers/net/ethernet/mellanox/mlx5/core/main.c
View File

@ -64,7 +64,7 @@
#include "lib/clock.h"
MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_VERSION(DRIVER_VERSION);

8
include/linux/mlx5/device.h
View File

@ -750,7 +750,7 @@ enum {
#define MLX5_MINI_CQE_ARRAY_SIZE 8
static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
{
return (cqe->op_own >> 2) & 0x3;
}
@ -770,14 +770,14 @@ static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
return (cqe->l4_l3_hdr_type >> 2) & 0x3;
}
static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe)
static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
{
return cqe->outer_l3_tunneled & 0x1;
}
static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
{
return !!(cqe->l4_l3_hdr_type & 0x1);
return cqe->l4_l3_hdr_type & 0x1;
}
static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)

5
include/linux/mlx5/driver.h
View File

@ -138,9 +138,14 @@ enum {
MLX5_REG_HOST_ENDIANNESS = 0x7004,
MLX5_REG_MCIA = 0x9014,
MLX5_REG_MLCR = 0x902b,
MLX5_REG_MTRC_CAP = 0x9040,
MLX5_REG_MTRC_CONF = 0x9041,
MLX5_REG_MTRC_STDB = 0x9042,
MLX5_REG_MTRC_CTRL = 0x9043,
MLX5_REG_MPCNT = 0x9051,
MLX5_REG_MTPPS = 0x9053,
MLX5_REG_MTPPSE = 0x9054,
MLX5_REG_MPEGC = 0x9056,
MLX5_REG_MCQI = 0x9061,
MLX5_REG_MCC = 0x9062,
MLX5_REG_MCDA = 0x9063,

5
include/linux/mlx5/fs.h
View File

@ -89,6 +89,7 @@ struct mlx5_flow_destination {
enum mlx5_flow_destination_type type;
union {
u32 tir_num;
u32 ft_num;
struct mlx5_flow_table *ft;
struct mlx5_fc *counter;
struct {
@ -152,6 +153,8 @@ struct mlx5_fs_vlan {
u8 prio;
};
#define MLX5_FS_VLAN_DEPTH 2
struct mlx5_flow_act {
u32 action;
bool has_flow_tag;
@ -159,7 +162,7 @@ struct mlx5_flow_act {
u32 encap_id;
u32 modify_id;
uintptr_t esp_id;
struct mlx5_fs_vlan vlan;
struct mlx5_fs_vlan vlan[MLX5_FS_VLAN_DEPTH];
struct ib_counters *counters;
};

94
include/linux/mlx5/mlx5_ifc.h
View File

@ -341,7 +341,10 @@ struct mlx5_ifc_flow_table_prop_layout_bits {
u8 reserved_at_9[0x1];
u8 pop_vlan[0x1];
u8 push_vlan[0x1];
u8 reserved_at_c[0x14];
u8 reserved_at_c[0x1];
u8 pop_vlan_2[0x1];
u8 push_vlan_2[0x1];
u8 reserved_at_f[0x11];
u8 reserved_at_20[0x2];
u8 log_max_ft_size[0x6];
@ -1181,6 +1184,7 @@ enum mlx5_flow_destination_type {
MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
};
struct mlx5_ifc_dest_format_struct_bits {
@ -2390,6 +2394,8 @@ enum {
MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
};
struct mlx5_ifc_vlan_bits {
@ -2420,7 +2426,9 @@ struct mlx5_ifc_flow_context_bits {
u8 modify_header_id[0x20];
u8 reserved_at_100[0x100];
struct mlx5_ifc_vlan_bits push_vlan_2;
u8 reserved_at_120[0xe0];
struct mlx5_ifc_fte_match_param_bits match_value;
@ -8053,6 +8061,19 @@ struct mlx5_ifc_peir_reg_bits {
u8 error_type[0x8];
};
struct mlx5_ifc_mpegc_reg_bits {
u8 reserved_at_0[0x30];
u8 field_select[0x10];
u8 tx_overflow_sense[0x1];
u8 mark_cqe[0x1];
u8 mark_cnp[0x1];
u8 reserved_at_43[0x1b];
u8 tx_lossy_overflow_oper[0x2];
u8 reserved_at_60[0x100];
};
struct mlx5_ifc_pcam_enhanced_features_bits {
u8 reserved_at_0[0x6d];
u8 rx_icrc_encapsulated_counter[0x1];
@ -8101,7 +8122,11 @@ struct mlx5_ifc_pcam_reg_bits {
};
struct mlx5_ifc_mcam_enhanced_features_bits {
u8 reserved_at_0[0x7b];
u8 reserved_at_0[0x74];
u8 mark_tx_action_cnp[0x1];
u8 mark_tx_action_cqe[0x1];
u8 dynamic_tx_overflow[0x1];
u8 reserved_at_77[0x4];
u8 pcie_outbound_stalled[0x1];
u8 tx_overflow_buffer_pkt[0x1];
u8 mtpps_enh_out_per_adj[0x1];
@ -8116,7 +8141,11 @@ struct mlx5_ifc_mcam_access_reg_bits {
u8 mcqi[0x1];
u8 reserved_at_1f[0x1];
u8 regs_95_to_64[0x20];
u8 regs_95_to_87[0x9];
u8 mpegc[0x1];
u8 regs_85_to_68[0x12];
u8 tracer_registers[0x4];
u8 regs_63_to_32[0x20];
u8 regs_31_to_0[0x20];
};
@ -9191,4 +9220,61 @@ struct mlx5_ifc_create_uctx_in_bits {
struct mlx5_ifc_uctx_bits uctx;
};
struct mlx5_ifc_mtrc_string_db_param_bits {
u8 string_db_base_address[0x20];
u8 reserved_at_20[0x8];
u8 string_db_size[0x18];
};
struct mlx5_ifc_mtrc_cap_bits {
u8 trace_owner[0x1];
u8 trace_to_memory[0x1];
u8 reserved_at_2[0x4];
u8 trc_ver[0x2];
u8 reserved_at_8[0x14];
u8 num_string_db[0x4];
u8 first_string_trace[0x8];
u8 num_string_trace[0x8];
u8 reserved_at_30[0x28];
u8 log_max_trace_buffer_size[0x8];
u8 reserved_at_60[0x20];
struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
u8 reserved_at_280[0x180];
};
struct mlx5_ifc_mtrc_conf_bits {
u8 reserved_at_0[0x1c];
u8 trace_mode[0x4];
u8 reserved_at_20[0x18];
u8 log_trace_buffer_size[0x8];
u8 trace_mkey[0x20];
u8 reserved_at_60[0x3a0];
};
struct mlx5_ifc_mtrc_stdb_bits {
u8 string_db_index[0x4];
u8 reserved_at_4[0x4];
u8 read_size[0x18];
u8 start_offset[0x20];
u8 string_db_data[0];
};
struct mlx5_ifc_mtrc_ctrl_bits {
u8 trace_status[0x2];
u8 reserved_at_2[0x2];
u8 arm_event[0x1];
u8 reserved_at_5[0xb];
u8 modify_field_select[0x10];
u8 reserved_at_20[0x2b];
u8 current_timestamp52_32[0x15];
u8 current_timestamp31_0[0x20];
u8 reserved_at_80[0x180];
};
#endif /* MLX5_IFC_H */