dmaengine fixes for v5.7-rc4
Core: - Documentation typo fixes - fix the channel indexes - Dmatest: fixes for process hang and iterations Drivers: - hisilicon: build error fix without PCI_MSI - ti-k3: deadlock fix - uniphier-xdmac: fix for reg region - pch: fix data race - tegra: fix clock state -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+vs47OPLdNbVcHzyfBQHDyUjg0cFAl6tUikACgkQfBQHDyUj g0dGcw//ZIU2KARtc+IpMEPlId15gDuNXYfiC5c8yqGlGy7bfj853XecDjGWSWa3 9Ouj1mZL2szGudzSKvQwIWXQNlf0nYTH1QvKJVRoiO9uiwrY9tse5hKd247lJzVh EH4PvZpk0gTXZcV4eM3LrQZV+lxJLnrJIlnmk4m8/HGtAa0hLXZpFEDJnwsLaVVL CLeJoPZpbDWEfmITdB622yAgnHMqSlra0jwBwhfNXtf22MkLGliHLveB0/IxWOal QR0r9b/9SGSBtxAYBq5BakgP0HuArKuoNyYw6C9Ve8w3Gq+enEPKiY+OPNN59zTQ 86x9o3l0Zp6Bs0xoQEi1Ut8Iate5LEeJw47LfGvQZdDbg+h7CcbIoqEaLUfVmchz shwEoX1vPQehomJqmdolktxsBjYfYCpmPhp0c4vLNuNdVycAbS0x/sEAWc6HdP77 f3BU5yk1FahHc9y7z7RQfdukD3eAFcjpv6Lk4xbpJcy0/6TPpYEznk6XU82c4iJZ LjYAxwUIibMhvjgJ12Ik9kEHP2or1wUNRg0wWLRI83ko+r6gXlemZH2mLOE04xz+ kFxKnNWdCFKnTRMQtCa0+Y7TSuZEm7Gcep952hWgRu5+wAtEMWreub31QIRyuAj+ fqKrpUzQtAQly4ToOYj0Ns5w87berbkhJG+fmHX/kgukdYWh104= =py+J -----END PGP SIGNATURE----- Merge tag 'dmaengine-fix-5.7-rc4' of git://git.infradead.org/users/vkoul/slave-dma Pull dmaengine fixes from Vinod Koul: "Core: - Documentation typo fixes - fix the channel indexes - dmatest: fixes for process hang and iterations Drivers: - hisilicon: build error fix without PCI_MSI - ti-k3: deadlock fix - uniphier-xdmac: fix for reg region - pch: fix data race - tegra: fix clock state" * tag 'dmaengine-fix-5.7-rc4' of git://git.infradead.org/users/vkoul/slave-dma: dmaengine: dmatest: Fix process hang when reading 'wait' parameter dmaengine: dmatest: Fix iteration non-stop logic dmaengine: tegra-apb: Ensure that clock is enabled during of DMA synchronization dmaengine: fix channel index enumeration dmaengine: mmp_tdma: Reset channel error on release dmaengine: mmp_tdma: Do not ignore slave config validation errors dmaengine: pch_dma.c: Avoid data race between probe and irq handler dt-bindings: dma: uniphier-xdmac: switch to single reg region include/linux/dmaengine: Typos fixes in API documentation dmaengine: xilinx_dma: Add missing check for empty list dmaengine: ti: k3-psil: fix deadlock on error path dmaengine: hisilicon: Fix build error without PCI_MSI
This commit is contained in:
Linus Torvalds
commit
ed6889db63
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@ -22,9 +22,7 @@ properties:
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const: socionext,uniphier-xdmac
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reg:
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items:
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- description: XDMAC base register region (offset and length)
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- description: XDMAC extension register region (offset and length)
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maxItems: 1
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interrupts:
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maxItems: 1
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@ -49,12 +47,13 @@ required:
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- reg
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- interrupts
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- "#dma-cells"
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- dma-channels
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examples:
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- |
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xdmac: dma-controller@5fc10000 {
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compatible = "socionext,uniphier-xdmac";
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reg = <0x5fc10000 0x1000>, <0x5fc20000 0x800>;
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reg = <0x5fc10000 0x5300>;
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interrupts = <0 188 4>;
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#dma-cells = <2>;
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dma-channels = <16>;
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@ -241,7 +241,8 @@ config FSL_RAID
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config HISI_DMA
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tristate "HiSilicon DMA Engine support"
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depends on ARM64 || (COMPILE_TEST && PCI_MSI)
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depends on ARM64 || COMPILE_TEST
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depends on PCI_MSI
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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@ -232,10 +232,6 @@ static void chan_dev_release(struct device *dev)
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struct dma_chan_dev *chan_dev;
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chan_dev = container_of(dev, typeof(*chan_dev), device);
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if (atomic_dec_and_test(chan_dev->idr_ref)) {
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ida_free(&dma_ida, chan_dev->dev_id);
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kfree(chan_dev->idr_ref);
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}
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kfree(chan_dev);
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}
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@ -1043,27 +1039,9 @@ static int get_dma_id(struct dma_device *device)
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}
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static int __dma_async_device_channel_register(struct dma_device *device,
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struct dma_chan *chan,
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int chan_id)
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struct dma_chan *chan)
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{
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int rc = 0;
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int chancnt = device->chancnt;
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atomic_t *idr_ref;
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struct dma_chan *tchan;
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tchan = list_first_entry_or_null(&device->channels,
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struct dma_chan, device_node);
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if (!tchan)
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return -ENODEV;
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if (tchan->dev) {
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idr_ref = tchan->dev->idr_ref;
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} else {
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idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
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if (!idr_ref)
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return -ENOMEM;
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atomic_set(idr_ref, 0);
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}
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chan->local = alloc_percpu(typeof(*chan->local));
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if (!chan->local)
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@ -1079,29 +1057,36 @@ static int __dma_async_device_channel_register(struct dma_device *device,
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* When the chan_id is a negative value, we are dynamically adding
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* the channel. Otherwise we are static enumerating.
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*/
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chan->chan_id = chan_id < 0 ? chancnt : chan_id;
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mutex_lock(&device->chan_mutex);
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chan->chan_id = ida_alloc(&device->chan_ida, GFP_KERNEL);
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mutex_unlock(&device->chan_mutex);
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if (chan->chan_id < 0) {
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pr_err("%s: unable to alloc ida for chan: %d\n",
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__func__, chan->chan_id);
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goto err_out;
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}
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chan->dev->device.class = &dma_devclass;
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chan->dev->device.parent = device->dev;
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chan->dev->chan = chan;
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chan->dev->idr_ref = idr_ref;
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chan->dev->dev_id = device->dev_id;
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atomic_inc(idr_ref);
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dev_set_name(&chan->dev->device, "dma%dchan%d",
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device->dev_id, chan->chan_id);
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rc = device_register(&chan->dev->device);
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if (rc)
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goto err_out;
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goto err_out_ida;
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chan->client_count = 0;
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device->chancnt = chan->chan_id + 1;
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device->chancnt++;
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return 0;
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err_out_ida:
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mutex_lock(&device->chan_mutex);
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ida_free(&device->chan_ida, chan->chan_id);
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mutex_unlock(&device->chan_mutex);
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err_out:
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free_percpu(chan->local);
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kfree(chan->dev);
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if (atomic_dec_return(idr_ref) == 0)
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kfree(idr_ref);
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return rc;
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}
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@ -1110,7 +1095,7 @@ int dma_async_device_channel_register(struct dma_device *device,
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{
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int rc;
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rc = __dma_async_device_channel_register(device, chan, -1);
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rc = __dma_async_device_channel_register(device, chan);
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if (rc < 0)
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return rc;
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@ -1130,6 +1115,9 @@ static void __dma_async_device_channel_unregister(struct dma_device *device,
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device->chancnt--;
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chan->dev->chan = NULL;
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mutex_unlock(&dma_list_mutex);
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mutex_lock(&device->chan_mutex);
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ida_free(&device->chan_ida, chan->chan_id);
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mutex_unlock(&device->chan_mutex);
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device_unregister(&chan->dev->device);
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free_percpu(chan->local);
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}
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@ -1152,7 +1140,7 @@ EXPORT_SYMBOL_GPL(dma_async_device_channel_unregister);
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*/
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int dma_async_device_register(struct dma_device *device)
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{
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int rc, i = 0;
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int rc;
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struct dma_chan* chan;
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if (!device)
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@ -1257,9 +1245,12 @@ int dma_async_device_register(struct dma_device *device)
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if (rc != 0)
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return rc;
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mutex_init(&device->chan_mutex);
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ida_init(&device->chan_ida);
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/* represent channels in sysfs. Probably want devs too */
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list_for_each_entry(chan, &device->channels, device_node) {
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rc = __dma_async_device_channel_register(device, chan, i++);
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rc = __dma_async_device_channel_register(device, chan);
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if (rc < 0)
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goto err_out;
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}
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@ -1334,6 +1325,7 @@ void dma_async_device_unregister(struct dma_device *device)
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*/
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dma_cap_set(DMA_PRIVATE, device->cap_mask);
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dma_channel_rebalance();
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ida_free(&dma_ida, device->dev_id);
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dma_device_put(device);
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mutex_unlock(&dma_list_mutex);
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}
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@ -240,7 +240,7 @@ static bool is_threaded_test_run(struct dmatest_info *info)
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struct dmatest_thread *thread;
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list_for_each_entry(thread, &dtc->threads, node) {
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if (!thread->done)
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if (!thread->done && !thread->pending)
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return true;
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}
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}
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@ -662,8 +662,8 @@ static int dmatest_func(void *data)
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flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
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ktime = ktime_get();
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while (!kthread_should_stop()
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&& !(params->iterations && total_tests >= params->iterations)) {
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while (!(kthread_should_stop() ||
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(params->iterations && total_tests >= params->iterations))) {
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struct dma_async_tx_descriptor *tx = NULL;
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struct dmaengine_unmap_data *um;
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dma_addr_t *dsts;
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@ -363,6 +363,8 @@ static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac)
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gen_pool_free(gpool, (unsigned long)tdmac->desc_arr,
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size);
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tdmac->desc_arr = NULL;
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if (tdmac->status == DMA_ERROR)
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tdmac->status = DMA_COMPLETE;
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return;
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}
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@ -443,7 +445,8 @@ static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic(
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if (!desc)
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goto err_out;
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mmp_tdma_config_write(chan, direction, &tdmac->slave_config);
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if (mmp_tdma_config_write(chan, direction, &tdmac->slave_config))
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goto err_out;
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while (buf < buf_len) {
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desc = &tdmac->desc_arr[i];
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@ -865,6 +865,7 @@ static int pch_dma_probe(struct pci_dev *pdev,
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}
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pci_set_master(pdev);
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pd->dma.dev = &pdev->dev;
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err = request_irq(pdev->irq, pd_irq, IRQF_SHARED, DRV_NAME, pd);
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if (err) {
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@ -880,7 +881,6 @@ static int pch_dma_probe(struct pci_dev *pdev,
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goto err_free_irq;
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}
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pd->dma.dev = &pdev->dev;
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INIT_LIST_HEAD(&pd->dma.channels);
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@ -816,6 +816,13 @@ static bool tegra_dma_eoc_interrupt_deasserted(struct tegra_dma_channel *tdc)
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static void tegra_dma_synchronize(struct dma_chan *dc)
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{
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struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
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int err;
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err = pm_runtime_get_sync(tdc->tdma->dev);
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if (err < 0) {
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dev_err(tdc2dev(tdc), "Failed to synchronize DMA: %d\n", err);
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return;
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}
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/*
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* CPU, which handles interrupt, could be busy in
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@ -825,6 +832,8 @@ static void tegra_dma_synchronize(struct dma_chan *dc)
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wait_event(tdc->wq, tegra_dma_eoc_interrupt_deasserted(tdc));
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tasklet_kill(&tdc->tasklet);
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pm_runtime_put(tdc->tdma->dev);
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}
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static unsigned int tegra_dma_sg_bytes_xferred(struct tegra_dma_channel *tdc,
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@ -27,6 +27,7 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id)
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soc_ep_map = &j721e_ep_map;
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} else {
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pr_err("PSIL: No compatible machine found for map\n");
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mutex_unlock(&ep_map_mutex);
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return ERR_PTR(-ENOTSUPP);
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}
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pr_debug("%s: Using map for %s\n", __func__, soc_ep_map->name);
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@ -1230,16 +1230,16 @@ static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,
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return ret;
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spin_lock_irqsave(&chan->lock, flags);
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desc = list_last_entry(&chan->active_list,
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struct xilinx_dma_tx_descriptor, node);
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/*
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* VDMA and simple mode do not support residue reporting, so the
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* residue field will always be 0.
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*/
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if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA)
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residue = xilinx_dma_get_residue(chan, desc);
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if (!list_empty(&chan->active_list)) {
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desc = list_last_entry(&chan->active_list,
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struct xilinx_dma_tx_descriptor, node);
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/*
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* VDMA and simple mode do not support residue reporting, so the
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* residue field will always be 0.
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*/
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if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA)
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residue = xilinx_dma_get_residue(chan, desc);
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}
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spin_unlock_irqrestore(&chan->lock, flags);
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dma_set_residue(txstate, residue);
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@ -83,9 +83,9 @@ enum dma_transfer_direction {
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/**
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* Interleaved Transfer Request
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* ----------------------------
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* A chunk is collection of contiguous bytes to be transfered.
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* A chunk is collection of contiguous bytes to be transferred.
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* The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
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* ICGs may or maynot change between chunks.
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* ICGs may or may not change between chunks.
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* A FRAME is the smallest series of contiguous {chunk,icg} pairs,
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* that when repeated an integral number of times, specifies the transfer.
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* A transfer template is specification of a Frame, the number of times
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@ -341,13 +341,11 @@ struct dma_chan {
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* @chan: driver channel device
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* @device: sysfs device
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* @dev_id: parent dma_device dev_id
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* @idr_ref: reference count to gate release of dma_device dev_id
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*/
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struct dma_chan_dev {
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struct dma_chan *chan;
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struct device device;
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int dev_id;
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atomic_t *idr_ref;
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};
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/**
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@ -835,6 +833,8 @@ struct dma_device {
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int dev_id;
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struct device *dev;
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struct module *owner;
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struct ida chan_ida;
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struct mutex chan_mutex; /* to protect chan_ida */
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u32 src_addr_widths;
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u32 dst_addr_widths;
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@ -1069,7 +1069,7 @@ static inline int dmaengine_terminate_all(struct dma_chan *chan)
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* dmaengine_synchronize() needs to be called before it is safe to free
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* any memory that is accessed by previously submitted descriptors or before
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* freeing any resources accessed from within the completion callback of any
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* perviously submitted descriptors.
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* previously submitted descriptors.
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*
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* This function can be called from atomic context as well as from within a
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* complete callback of a descriptor submitted on the same channel.
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@ -1091,7 +1091,7 @@ static inline int dmaengine_terminate_async(struct dma_chan *chan)
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*
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* Synchronizes to the DMA channel termination to the current context. When this
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* function returns it is guaranteed that all transfers for previously issued
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* descriptors have stopped and and it is safe to free the memory assoicated
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* descriptors have stopped and it is safe to free the memory associated
|
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* with them. Furthermore it is guaranteed that all complete callback functions
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* for a previously submitted descriptor have finished running and it is safe to
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* free resources accessed from within the complete callbacks.
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|
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Loading…
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