UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

STM32 DT updates for v4.12, round 1 

Highlights:
 ----------
 
  - ADD RTC support on STM32F746 MCU
  - Enable RTC on STM32F746 Eval board
  - Enable clocks on STM32F746 MCU
  - Enable DMA, pwm1 and pwm3 on STM32F429I Eval
  - Add support of STM32H743 MCU and his Eval board
  - Enable USB HS and FS on STM32F469 Disco board
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJY4n6WAAoJEH+ayWryHnCFaXYQAKmOBcBrU2RiZt/tn02lhEJI
 /BKTjFUBg9CCSMqT8xJvDtCJ3YLUwxqo4HhkvKnTZh7AQ1mSTdVScKrB0Le83271
 IOoAFBmCZCn9ShSgclBPiold1q5i7g/hZRagQwNwXHdQXt8GZxhpVzaYgZj7EtQ4
 B5ikmQCT9KagPSiY4M6X1pzRPRmqcN6alAYsIO8SoHrFpBXm8/TWqspn5pPhojIM
 4oWbGEwAxLR4J86TA2Eu+Yp/8FvGX8+W59tFbarlBPloKueHADZ72MfrTZ72vXf6
 y4s4JGctDOiLqRFBR6Pp3i8/F4d2pxtd7GsWHR12Mw8lQGHHkKZWs20vri+s6HiT
 qkjKWXdV4mwYis4vUB997NOYClbqTbURcUt7uRvFrDXD2gg3TnRGkP5WynEX8njS
 cnRhJ+1rS3iC2rvNtRGE9aadRRtxXVqVQ1HA2EeBeNGpVgFFPbdhPpt2ZDhC2PLf
 FRYQnxxVAngionqxNGytwKTHXSsVYufMINPyUZWxqUXN083+HAWemJCUTd6cC1ia
 I781iAjQDWyQzrG8jQtsEXPT2rSdrouVzu0CG642EDuU81CkAWz8vBkrjPj9m+9g
 fcd8RhRQTvcz0rePNBq/OLRojA7bVsDBBikAJJh6tCnwil8oJlaJ5DSbORe8J8Ez
 DlOoNIKk1byGfN6LrxKz
 =l7eq
 -----END PGP SIGNATURE-----

Merge tag 'stm32-dt-for-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into next/dt

STM32 DT updates for v4.12, round 1

Highlights:
----------

 - ADD RTC support on STM32F746 MCU
 - Enable RTC on STM32F746 Eval board
 - Enable clocks on STM32F746 MCU
 - Enable DMA, pwm1 and pwm3 on STM32F429I Eval
 - Add support of STM32H743 MCU and his Eval board
 - Enable USB HS and FS on STM32F469 Disco board

* tag 'stm32-dt-for-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
  dt-bindings: Document the STM32 USB OTG DWC2 core binding
  ARM: dts: stm32: Enable USB HS in FS mode (embedded phy) on stm32f429-disco
  ARM: dts: stm32: Enable USB FS on stm32f469-disco
  ARM: dts: stm32: Add USB FS support for STM32F429 MCU
  ARM: dts: stm32: Add STM32H743 MCU and STM32H743i-EVAL board
  ARM: dts: stm32: Enable pwm1 and pwm3 on stm32f429i-eval
  ARM: dts: stm32: Enable dma by default on stm32f4 adc
  ARM: dts: stm32: enable RTC on stm32746g-eval
  ARM: dts: stm32: Add RTC support for STM32F746 MCU
  ARM: dts: stm32: set HSE_RTC clock frequency to 1 MHz on stm32f746
  dt-bindings: mfd: Add STM32F7 RCC numeric constants into DT include file
  ARM: dts: stm32: Enable clocks for STM32F746 MCU

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2017-04-19 05:22:29 -07:00
parent a47e346680 21b825e404
commit ed50c4855e
12 changed files with 601 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/usb/dwc2.txt
View File

@ -14,6 +14,10 @@ Required properties:
- "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs;
- "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs;
- snps,dwc2: A generic DWC2 USB controller with default parameters.
- "st,stm32f4x9-fsotg": The DWC2 USB FS/HS controller instance in STM32F4x9 SoCs
configured in FS mode;
- "st,stm32f4x9-hsotg": The DWC2 USB HS controller instance in STM32F4x9 SoCs
configured in HS mode;
- reg : Should contain 1 register range (address and length)
- interrupts : Should contain 1 interrupt
- clocks: clock provider specifier

3
arch/arm/boot/dts/Makefile
View File

@ -776,7 +776,8 @@ dtb-$(CONFIG_ARCH_STM32)+= \
stm32f429-disco.dtb \
stm32f469-disco.dtb \
stm32429i-eval.dtb \
stm32746g-eval.dtb
stm32746g-eval.dtb \
stm32h743i-eval.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \

28
arch/arm/boot/dts/stm32429i-eval.dts
View File

@ -167,6 +167,34 @@
status = "okay";
};
&timers1 {
status = "okay";
pwm {
pinctrl-0 = <&pwm1_pins>;
pinctrl-names = "default";
status = "okay";
};
timer@0 {
status = "okay";
};
};
&timers3 {
status = "okay";
pwm {
pinctrl-0 = <&pwm3_pins>;
pinctrl-names = "default";
status = "okay";
};
timer@2 {
status = "okay";
};
};
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";

4
arch/arm/boot/dts/stm32746g-eval.dts
View File

@ -89,6 +89,10 @@
clock-frequency = <25000000>;
};
&rtc {
status = "okay";
};
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";

16
arch/arm/boot/dts/stm32f429-disco.dts
View File

@ -88,6 +88,14 @@
gpios = <&gpioa 0 0>;
};
};
/* This turns on vbus for otg for host mode (dwc2) */
vcc5v_otg: vcc5v-otg-regulator {
compatible = "regulator-fixed";
gpio = <&gpioc 4 0>;
regulator-name = "vcc5_host1";
regulator-always-on;
};
};
&clk_hse {
@ -105,3 +113,11 @@
pinctrl-names = "default";
status = "okay";
};
&usbotg_hs {
compatible = "st,stm32f4x9-fsotg";
dr_mode = "host";
pinctrl-0 = <&usbotg_fs_pins_b>;
pinctrl-names = "default";
status = "okay";
};

37
arch/arm/boot/dts/stm32f429.dtsi
View File

@ -450,6 +450,8 @@
clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
interrupt-parent = <&adc>;
interrupts = <0>;
dmas = <&dma2 0 0 0x400 0x0>;
dma-names = "rx";
status = "disabled";
};
@ -460,6 +462,8 @@
clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
interrupt-parent = <&adc>;
interrupts = <1>;
dmas = <&dma2 3 1 0x400 0x0>;
dma-names = "rx";
status = "disabled";
};
@ -470,6 +474,8 @@
clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
interrupt-parent = <&adc>;
interrupts = <2>;
dmas = <&dma2 1 2 0x400 0x0>;
dma-names = "rx";
status = "disabled";
};
};
@ -666,6 +672,28 @@
};
};
usbotg_fs_pins_a: usbotg_fs@0 {
pins {
pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
<STM32F429_PA11_FUNC_OTG_FS_DM>,
<STM32F429_PA12_FUNC_OTG_FS_DP>;
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
usbotg_fs_pins_b: usbotg_fs@1 {
pins {
pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
<STM32F429_PB14_FUNC_OTG_HS_DM>,
<STM32F429_PB15_FUNC_OTG_HS_DP>;
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
usbotg_hs_pins_a: usbotg_hs@0 {
pins {
pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
@ -805,6 +833,15 @@
status = "disabled";
};
usbotg_fs: usb@50000000 {
compatible = "st,stm32f4x9-fsotg";
reg = <0x50000000 0x40000>;
interrupts = <67>;
clocks = <&rcc 0 39>;
clock-names = "otg";
status = "disabled";
};
rng: rng@50060800 {
compatible = "st,stm32-rng";
reg = <0x50060800 0x400>;

16
arch/arm/boot/dts/stm32f469-disco.dts
View File

@ -68,6 +68,15 @@
soc {
dma-ranges = <0xc0000000 0x0 0x10000000>;
};
/* This turns on vbus for otg for host mode (dwc2) */
vcc5v_otg: vcc5v-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpiob 2 0>;
regulator-name = "vcc5_host1";
regulator-always-on;
};
};
&rcc {
@ -115,3 +124,10 @@
pinctrl-names = "default";
status = "okay";
};
&usbotg_fs {
dr_mode = "host";
pinctrl-0 = <&usbotg_fs_pins_a>;
pinctrl-names = "default";
status = "okay";
};

96
arch/arm/boot/dts/stm32f746.dtsi
View File

@ -43,6 +43,8 @@
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
#include <dt-bindings/clock/stm32fx-clock.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>
/ {
clocks {
@ -51,6 +53,24 @@
compatible = "fixed-clock";
clock-frequency = <0>;
};
clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32000>;
};
clk_i2s_ckin: clk-i2s-ckin {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <48000000>;
};
};
soc {
@ -58,7 +78,7 @@
compatible = "st,stm32-timer";
reg = <0x40000000 0x400>;
interrupts = <28>;
clocks = <&rcc 0 128>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
status = "disabled";
};
@ -66,7 +86,7 @@
compatible = "st,stm32-timer";
reg = <0x40000400 0x400>;
interrupts = <29>;
clocks = <&rcc 0 129>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
status = "disabled";
};
@ -74,7 +94,7 @@
compatible = "st,stm32-timer";
reg = <0x40000800 0x400>;
interrupts = <30>;
clocks = <&rcc 0 130>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
status = "disabled";
};
@ -82,14 +102,14 @@
compatible = "st,stm32-timer";
reg = <0x40000c00 0x400>;
interrupts = <50>;
clocks = <&rcc 0 131>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
};
timer6: timer@40001000 {
compatible = "st,stm32-timer";
reg = <0x40001000 0x400>;
interrupts = <54>;
clocks = <&rcc 0 132>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
status = "disabled";
};
@ -97,7 +117,21 @@
compatible = "st,stm32-timer";
reg = <0x40001400 0x400>;
interrupts = <55>;
clocks = <&rcc 0 133>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
status = "disabled";
};
rtc: rtc@40002800 {
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
clocks = <&rcc 1 CLK_RTC>;
clock-names = "ck_rtc";
assigned-clocks = <&rcc 1 CLK_RTC>;
assigned-clock-parents = <&rcc 1 CLK_LSE>;
interrupt-parent = <&exti>;
interrupts = <17 1>;
interrupt-names = "alarm";
st,syscfg = <&pwrcfg>;
status = "disabled";
};
@ -105,7 +139,7 @@
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40004400 0x400>;
interrupts = <38>;
clocks = <&rcc 0 145>;
clocks = <&rcc 1 CLK_USART2>;
status = "disabled";
};
@ -113,7 +147,7 @@
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40004800 0x400>;
interrupts = <39>;
clocks = <&rcc 0 146>;
clocks = <&rcc 1 CLK_USART3>;
status = "disabled";
};
@ -121,7 +155,7 @@
compatible = "st,stm32f7-uart";
reg = <0x40004c00 0x400>;
interrupts = <52>;
clocks = <&rcc 0 147>;
clocks = <&rcc 1 CLK_UART4>;
status = "disabled";
};
@ -129,7 +163,7 @@
compatible = "st,stm32f7-uart";
reg = <0x40005000 0x400>;
interrupts = <53>;
clocks = <&rcc 0 148>;
clocks = <&rcc 1 CLK_UART5>;
status = "disabled";
};
@ -137,7 +171,7 @@
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40007800 0x400>;
interrupts = <82>;
clocks = <&rcc 0 158>;
clocks = <&rcc 1 CLK_UART7>;
status = "disabled";
};
@ -145,7 +179,7 @@
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40007c00 0x400>;
interrupts = <83>;
clocks = <&rcc 0 159>;
clocks = <&rcc 1 CLK_UART8>;
status = "disabled";
};
@ -153,7 +187,7 @@
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
clocks = <&rcc 0 164>;
clocks = <&rcc 1 CLK_USART1>;
status = "disabled";
};
@ -161,7 +195,7 @@
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40011400 0x400>;
interrupts = <71>;
clocks = <&rcc 0 165>;
clocks = <&rcc 1 CLK_USART6>;
status = "disabled";
};
@ -178,6 +212,11 @@
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
};
pwrcfg: power-config@40007000 {
compatible = "syscon";
reg = <0x40007000 0x400>;
};
pin-controller {
#address-cells = <1>;
#size-cells = <1>;
@ -191,7 +230,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x0 0x400>;
clocks = <&rcc 0 256>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
};
@ -199,7 +238,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x400 0x400>;
clocks = <&rcc 0 257>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
};
@ -207,7 +246,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x800 0x400>;
clocks = <&rcc 0 258>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
};
@ -215,7 +254,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0xc00 0x400>;
clocks = <&rcc 0 259>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
};
@ -223,7 +262,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x1000 0x400>;
clocks = <&rcc 0 260>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
};
@ -231,7 +270,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x1400 0x400>;
clocks = <&rcc 0 261>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
};
@ -239,7 +278,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x1800 0x400>;
clocks = <&rcc 0 262>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
};
@ -247,7 +286,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x1c00 0x400>;
clocks = <&rcc 0 263>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
};
@ -255,7 +294,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x2000 0x400>;
clocks = <&rcc 0 264>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
};
@ -263,7 +302,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x2400 0x400>;
clocks = <&rcc 0 265>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
st,bank-name = "GPIOJ";
};
@ -271,7 +310,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x2800 0x400>;
clocks = <&rcc 0 266>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
st,bank-name = "GPIOK";
};
@ -291,9 +330,12 @@
rcc: rcc@40023800 {
#clock-cells = <2>;
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
compatible = "st,stm32f746-rcc", "st,stm32-rcc";
reg = <0x40023800 0x400>;
clocks = <&clk_hse>;
clocks = <&clk_hse>, <&clk_i2s_ckin>;
st,syscfg = <&pwrcfg>;
assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
assigned-clock-rates = <1000000>;
};
};
};

156
arch/arm/boot/dts/stm32h743-pinctrl.dtsi Normal file
View File

@ -0,0 +1,156 @@
/*
* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/pinctrl/stm32h7-pinfunc.h>
/ {
soc {
pin-controller {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32h743-pinctrl";
ranges = <0 0x58020000 0x3000>;
pins-are-numbered;
gpioa: gpio@58020000 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x0 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOA";
};
gpiob: gpio@58020400 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x400 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOB";
};
gpioc: gpio@58020800 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x800 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOC";
};
gpiod: gpio@58020c00 {
gpio-controller;
#gpio-cells = <2>;
reg = <0xc00 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOD";
};
gpioe: gpio@58021000 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x1000 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOE";
};
gpiof: gpio@58021400 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x1400 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOF";
};
gpiog: gpio@58021800 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x1800 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOG";
};
gpioh: gpio@58021c00 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x1c00 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOH";
};
gpioi: gpio@58022000 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x2000 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOI";
};
gpioj: gpio@58022400 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x2400 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOJ";
};
gpiok: gpio@58022800 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x2800 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOK";
};
usart1_pins: usart1@0 {
pins1 {
pinmux = <STM32H7_PB14_FUNC_USART1_TX>;
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32H7_PB15_FUNC_USART1_RX>;
bias-disable;
};
};
};
};
};

83
arch/arm/boot/dts/stm32h743.dtsi Normal file
View File

@ -0,0 +1,83 @@
/*
* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
/ {
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
timer_clk: timer-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
};
};
soc {
usart1: serial@40011000 {
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
status = "disabled";
clocks = <&timer_clk>;
};
timer5: timer@40000c00 {
compatible = "st,stm32-timer";
reg = <0x40000c00 0x400>;
interrupts = <50>;
clocks = <&timer_clk>;
};
};
};
&systick {
clock-frequency = <250000000>;
status = "okay";
};

74
arch/arm/boot/dts/stm32h743i-eval.dts Normal file
View File

@ -0,0 +1,74 @@
/*
* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "stm32h743.dtsi"
#include "stm32h743-pinctrl.dtsi"
/ {
model = "STMicroelectronics STM32H743i-EVAL board";
compatible = "st,stm32h743i-eval", "st,stm32h743";
chosen {
bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
};
memory {
reg = <0xd0000000 0x2000000>;
};
aliases {
serial0 = &usart1;
};
};
&clk_hse {
clock-frequency = <125000000>;
};
&usart1 {
pinctrl-0 = <&usart1_pins>;
pinctrl-names = "default";
status = "okay";
};

112
include/dt-bindings/mfd/stm32f7-rcc.h Normal file
View File

@ -0,0 +1,112 @@
/*
* This header provides constants for the STM32F7 RCC IP
*/
#ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H
#define _DT_BINDINGS_MFD_STM32F7_RCC_H
/* AHB1 */
#define STM32F7_RCC_AHB1_GPIOA 0
#define STM32F7_RCC_AHB1_GPIOB 1
#define STM32F7_RCC_AHB1_GPIOC 2
#define STM32F7_RCC_AHB1_GPIOD 3
#define STM32F7_RCC_AHB1_GPIOE 4
#define STM32F7_RCC_AHB1_GPIOF 5
#define STM32F7_RCC_AHB1_GPIOG 6
#define STM32F7_RCC_AHB1_GPIOH 7
#define STM32F7_RCC_AHB1_GPIOI 8
#define STM32F7_RCC_AHB1_GPIOJ 9
#define STM32F7_RCC_AHB1_GPIOK 10
#define STM32F7_RCC_AHB1_CRC 12
#define STM32F7_RCC_AHB1_BKPSRAM 18
#define STM32F7_RCC_AHB1_DTCMRAM 20
#define STM32F7_RCC_AHB1_DMA1 21
#define STM32F7_RCC_AHB1_DMA2 22
#define STM32F7_RCC_AHB1_DMA2D 23
#define STM32F7_RCC_AHB1_ETHMAC 25
#define STM32F7_RCC_AHB1_ETHMACTX 26
#define STM32F7_RCC_AHB1_ETHMACRX 27
#define STM32FF_RCC_AHB1_ETHMACPTP 28
#define STM32F7_RCC_AHB1_OTGHS 29
#define STM32F7_RCC_AHB1_OTGHSULPI 30
#define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
#define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
/* AHB2 */
#define STM32F7_RCC_AHB2_DCMI 0
#define STM32F7_RCC_AHB2_CRYP 4
#define STM32F7_RCC_AHB2_HASH 5
#define STM32F7_RCC_AHB2_RNG 6
#define STM32F7_RCC_AHB2_OTGFS 7
#define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8))
#define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20)
/* AHB3 */
#define STM32F7_RCC_AHB3_FMC 0
#define STM32F7_RCC_AHB3_QSPI 1
#define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8))
#define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40)
/* APB1 */
#define STM32F7_RCC_APB1_TIM2 0
#define STM32F7_RCC_APB1_TIM3 1
#define STM32F7_RCC_APB1_TIM4 2
#define STM32F7_RCC_APB1_TIM5 3
#define STM32F7_RCC_APB1_TIM6 4
#define STM32F7_RCC_APB1_TIM7 5
#define STM32F7_RCC_APB1_TIM12 6
#define STM32F7_RCC_APB1_TIM13 7
#define STM32F7_RCC_APB1_TIM14 8
#define STM32F7_RCC_APB1_LPTIM1 9
#define STM32F7_RCC_APB1_WWDG 11
#define STM32F7_RCC_APB1_SPI2 14
#define STM32F7_RCC_APB1_SPI3 15
#define STM32F7_RCC_APB1_SPDIFRX 16
#define STM32F7_RCC_APB1_UART2 17
#define STM32F7_RCC_APB1_UART3 18
#define STM32F7_RCC_APB1_UART4 19
#define STM32F7_RCC_APB1_UART5 20
#define STM32F7_RCC_APB1_I2C1 21
#define STM32F7_RCC_APB1_I2C2 22
#define STM32F7_RCC_APB1_I2C3 23
#define STM32F7_RCC_APB1_I2C4 24
#define STM32F7_RCC_APB1_CAN1 25
#define STM32F7_RCC_APB1_CAN2 26
#define STM32F7_RCC_APB1_CEC 27
#define STM32F7_RCC_APB1_PWR 28
#define STM32F7_RCC_APB1_DAC 29
#define STM32F7_RCC_APB1_UART7 30
#define STM32F7_RCC_APB1_UART8 31
#define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8))
#define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80)
/* APB2 */
#define STM32F7_RCC_APB2_TIM1 0
#define STM32F7_RCC_APB2_TIM8 1
#define STM32F7_RCC_APB2_USART1 4
#define STM32F7_RCC_APB2_USART6 5
#define STM32F7_RCC_APB2_ADC1 8
#define STM32F7_RCC_APB2_ADC2 9
#define STM32F7_RCC_APB2_ADC3 10
#define STM32F7_RCC_APB2_SDMMC1 11
#define STM32F7_RCC_APB2_SPI1 12
#define STM32F7_RCC_APB2_SPI4 13
#define STM32F7_RCC_APB2_SYSCFG 14
#define STM32F7_RCC_APB2_TIM9 16
#define STM32F7_RCC_APB2_TIM10 17
#define STM32F7_RCC_APB2_TIM11 18
#define STM32F7_RCC_APB2_SPI5 20
#define STM32F7_RCC_APB2_SPI6 21
#define STM32F7_RCC_APB2_SAI1 22
#define STM32F7_RCC_APB2_SAI2 23
#define STM32F7_RCC_APB2_LTDC 26
#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8))
#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0)
#endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */