intel-gpio for v5.8-1
* MSI support for Intel Merrifield * Refactor gpio-pch to be up-to-date with recent kernel APIs * Miscellaneous cleanups here and there The following is an automated git shortlog grouped by driver: ich: - fix a typo merrifield: - Better show how GPIO and IRQ bases are derived from hardware - Switch over to MSI interrupts pch: - Use in pch_irq_type() macros provided by IRQ core - Refactor pch_irq_type() to avoid unnecessary locking - Get rid of unneeded variable in IRQ handler - Use BIT() and GENMASK() where it's appropriate -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAl65YWMACgkQb7wzTHR8 rCgOfRAApn+H8DzunFCHdskAwE8RZlPqwYA0McawGnnOExKEohkXO/8ckaQ1OA+e 7TeR5H2wJQzRChj4d9bAirmwOT0PGL8IrWsfZOPV4TUpF0LpRfmZr+Y0lzV83eB0 C/qfPRTjKLIcBSLpyayW9dEBKS0G6NlPgM9GSfR/Vkzw+Lv5LwHSHjGjgRM+vFk6 XMc+0dmxicOAhx9i1nVjoQVXJJ/zOMmZZ4/+7ShglXevkRHlZzBoxizLxM3swTka 9dQ4CoTWNvmNfTYAsBWFuXNrL5aiNKM/eynQio8rlDMOM/KoiP3KtKr7NZBcKnai RUUa19l96IxNaE/u1HY9FuaBP0VwQ3CuCWSI5aYjj4dfpUk0dMcNJNjoZ4u9F9xZ Rn7tFLvmyhXBvrFKcZglKfD7u/SE2YzPLR4IMBjbBdYBSrsktOpJBZbvRm2ZzxJv UE4CY2A2e6BC9YUD0IwokiP76h/YGMYbRf+3mYt0zJAaQFnWBBixRBDAQHqMjV99 jC6iIJJKHbL9Ai9QnlZ1P6edHJG0FsuvAN4D6ufZhjI9Df5n2ou7pfwTZrWOY/zh +RNEHrC3jCoux1FRtcYjL9N4ax9WiIVClc/wkp52pRauRtptNFg9sjuz9KM7dPNl jyyqA3FLDR3wG5wcpbSP1/xzhbHrSTDUbIN6Pr8R/QZnNIEZt2U= =P708 -----END PGP SIGNATURE----- Merge tag 'intel-gpio-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel into devel intel-gpio for v5.8-1 * MSI support for Intel Merrifield * Refactor gpio-pch to be up-to-date with recent kernel APIs * Miscellaneous cleanups here and there The following is an automated git shortlog grouped by driver: ich: - fix a typo merrifield: - Better show how GPIO and IRQ bases are derived from hardware - Switch over to MSI interrupts pch: - Use in pch_irq_type() macros provided by IRQ core - Refactor pch_irq_type() to avoid unnecessary locking - Get rid of unneeded variable in IRQ handler - Use BIT() and GENMASK() where it's appropriate
This commit is contained in:
Linus Walleij
commit
ed43f2b4e7
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@ -89,7 +89,7 @@ static struct {
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struct device *dev;
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struct gpio_chip chip;
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struct resource *gpio_base; /* GPIO IO base */
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struct resource *pm_base; /* Power Mangagment IO base */
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struct resource *pm_base; /* Power Management IO base */
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struct ichx_desc *desc; /* Pointer to chipset-specific description */
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u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */
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u8 use_gpio; /* Which GPIO groups are usable */
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@ -443,8 +443,8 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id
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base = pcim_iomap_table(pdev)[1];
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irq_base = readl(base);
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gpio_base = readl(sizeof(u32) + base);
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irq_base = readl(base + 0 * sizeof(u32));
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gpio_base = readl(base + 1 * sizeof(u32));
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/* Release the IO mapping, since we already get the info from BAR1 */
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pcim_iounmap_regions(pdev, BIT(1));
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@ -473,6 +473,10 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id
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raw_spin_lock_init(&priv->lock);
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retval = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
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if (retval < 0)
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return retval;
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girq = &priv->chip.irq;
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girq->chip = &mrfld_irqchip;
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girq->init_hw = mrfld_irq_init_hw;
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@ -482,7 +486,7 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id
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sizeof(*girq->parents), GFP_KERNEL);
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if (!girq->parents)
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return -ENOMEM;
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girq->parents[0] = pdev->irq;
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girq->parents[0] = pci_irq_vector(pdev, 0);
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girq->first = irq_base;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_bad_irq;
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@ -2,6 +2,7 @@
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/*
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* Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
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*/
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#include <linux/bits.h>
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#include <linux/gpio/driver.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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@ -11,11 +12,11 @@
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#include <linux/slab.h>
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#define PCH_EDGE_FALLING 0
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#define PCH_EDGE_RISING BIT(0)
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#define PCH_LEVEL_L BIT(1)
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#define PCH_LEVEL_H (BIT(0) | BIT(1))
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#define PCH_EDGE_BOTH BIT(2)
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#define PCH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
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#define PCH_EDGE_RISING 1
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#define PCH_LEVEL_L 2
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#define PCH_LEVEL_H 3
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#define PCH_EDGE_BOTH 4
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#define PCH_IM_MASK GENMASK(2, 0)
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#define PCH_IRQ_BASE 24
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@ -103,9 +104,9 @@ static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
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spin_lock_irqsave(&chip->spinlock, flags);
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reg_val = ioread32(&chip->reg->po);
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if (val)
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reg_val |= (1 << nr);
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reg_val |= BIT(nr);
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else
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reg_val &= ~(1 << nr);
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reg_val &= ~BIT(nr);
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iowrite32(reg_val, &chip->reg->po);
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spin_unlock_irqrestore(&chip->spinlock, flags);
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@ -115,7 +116,7 @@ static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
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{
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struct pch_gpio *chip = gpiochip_get_data(gpio);
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return (ioread32(&chip->reg->pi) >> nr) & 1;
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return !!(ioread32(&chip->reg->pi) & BIT(nr));
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}
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static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
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@ -130,13 +131,14 @@ static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
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reg_val = ioread32(&chip->reg->po);
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if (val)
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reg_val |= (1 << nr);
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reg_val |= BIT(nr);
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else
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reg_val &= ~(1 << nr);
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reg_val &= ~BIT(nr);
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iowrite32(reg_val, &chip->reg->po);
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pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
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pm |= (1 << nr);
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pm = ioread32(&chip->reg->pm);
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pm &= BIT(gpio_pins[chip->ioh]) - 1;
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pm |= BIT(nr);
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iowrite32(pm, &chip->reg->pm);
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spin_unlock_irqrestore(&chip->spinlock, flags);
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@ -151,8 +153,9 @@ static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
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unsigned long flags;
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spin_lock_irqsave(&chip->spinlock, flags);
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pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
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pm &= ~(1 << nr);
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pm = ioread32(&chip->reg->pm);
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pm &= BIT(gpio_pins[chip->ioh]) - 1;
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pm &= ~BIT(nr);
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iowrite32(pm, &chip->reg->pm);
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spin_unlock_irqrestore(&chip->spinlock, flags);
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@ -226,17 +229,15 @@ static int pch_irq_type(struct irq_data *d, unsigned int type)
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int ch, irq = d->irq;
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ch = irq - chip->irq_base;
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if (irq <= chip->irq_base + 7) {
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if (irq < chip->irq_base + 8) {
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im_reg = &chip->reg->im0;
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im_pos = ch;
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im_pos = ch - 0;
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} else {
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im_reg = &chip->reg->im1;
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im_pos = ch - 8;
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}
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dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos);
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spin_lock_irqsave(&chip->spinlock, flags);
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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val = PCH_EDGE_RISING;
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@ -254,20 +255,21 @@ static int pch_irq_type(struct irq_data *d, unsigned int type)
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val = PCH_LEVEL_L;
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break;
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default:
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goto unlock;
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return 0;
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}
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spin_lock_irqsave(&chip->spinlock, flags);
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/* Set interrupt mode */
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im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
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iowrite32(im | (val << (im_pos * 4)), im_reg);
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/* And the handler */
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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if (type & IRQ_TYPE_LEVEL_MASK)
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irq_set_handler_locked(d, handle_level_irq);
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else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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else if (type & IRQ_TYPE_EDGE_BOTH)
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irq_set_handler_locked(d, handle_edge_irq);
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unlock:
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spin_unlock_irqrestore(&chip->spinlock, flags);
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return 0;
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}
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@ -277,7 +279,7 @@ static void pch_irq_unmask(struct irq_data *d)
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct pch_gpio *chip = gc->private;
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iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
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iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imaskclr);
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}
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static void pch_irq_mask(struct irq_data *d)
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@ -285,7 +287,7 @@ static void pch_irq_mask(struct irq_data *d)
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct pch_gpio *chip = gc->private;
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iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
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iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imask);
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}
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static void pch_irq_ack(struct irq_data *d)
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@ -293,21 +295,22 @@ static void pch_irq_ack(struct irq_data *d)
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct pch_gpio *chip = gc->private;
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iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr);
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iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->iclr);
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}
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static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
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{
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struct pch_gpio *chip = dev_id;
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unsigned long reg_val = ioread32(&chip->reg->istatus);
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int i, ret = IRQ_NONE;
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int i;
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for_each_set_bit(i, ®_val, gpio_pins[chip->ioh]) {
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dev_dbg(chip->dev, "[%d]:irq=%d status=0x%lx\n", i, irq, reg_val);
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dev_dbg(chip->dev, "irq=%d status=0x%lx\n", irq, reg_val);
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reg_val &= BIT(gpio_pins[chip->ioh]) - 1;
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for_each_set_bit(i, ®_val, gpio_pins[chip->ioh])
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generic_handle_irq(chip->irq_base + i);
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ret = IRQ_HANDLED;
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}
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return ret;
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return IRQ_RETVAL(reg_val);
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}
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static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
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@ -344,7 +347,6 @@ static int pch_gpio_probe(struct pci_dev *pdev,
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s32 ret;
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struct pch_gpio *chip;
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int irq_base;
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u32 msk;
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chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
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if (chip == NULL)
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@ -357,7 +359,7 @@ static int pch_gpio_probe(struct pci_dev *pdev,
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return ret;
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}
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ret = pcim_iomap_regions(pdev, 1 << 1, KBUILD_MODNAME);
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ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
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if (ret) {
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dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
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return ret;
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@ -393,9 +395,8 @@ static int pch_gpio_probe(struct pci_dev *pdev,
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chip->irq_base = irq_base;
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/* Mask all interrupts, but enable them */
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msk = (1 << gpio_pins[chip->ioh]) - 1;
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iowrite32(msk, &chip->reg->imask);
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iowrite32(msk, &chip->reg->ien);
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iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask);
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iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien);
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ret = devm_request_irq(&pdev->dev, pdev->irq, pch_gpio_handler,
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IRQF_SHARED, KBUILD_MODNAME, chip);
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