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reset: starfive: Extract the common JH71X0 reset code 

Extract the common JH71X0 reset code for reusing them to
support JH7110 SoC.

Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Emil Renner Berthing 2023-04-01 19:19:22 +08:00 committed by Conor Dooley
parent 1ec3d20e4e
commit ed36fcd160
3 changed files with 77 additions and 55 deletions
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49
drivers/reset/starfive/reset-starfive-jh7100.c
View File

@ -10,6 +10,55 @@
#include "reset-starfive-jh71x0.h"
#include <dt-bindings/reset/starfive-jh7100.h>
/* register offsets */
#define JH7100_RESET_ASSERT0 0x00
#define JH7100_RESET_ASSERT1 0x04
#define JH7100_RESET_ASSERT2 0x08
#define JH7100_RESET_ASSERT3 0x0c
#define JH7100_RESET_STATUS0 0x10
#define JH7100_RESET_STATUS1 0x14
#define JH7100_RESET_STATUS2 0x18
#define JH7100_RESET_STATUS3 0x1c
/*
* Writing a 1 to the n'th bit of the m'th ASSERT register asserts
* line 32m + n, and writing a 0 deasserts the same line.
* Most reset lines have their status inverted so a 0 bit in the STATUS
* register means the line is asserted and a 1 means it's deasserted. A few
* lines don't though, so store the expected value of the status registers when
* all lines are asserted.
*/
static const u64 jh7100_reset_asserted[2] = {
/* STATUS0 */
BIT_ULL_MASK(JH7100_RST_U74) |
BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
/* STATUS1 */
BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
/* STATUS2 */
BIT_ULL_MASK(JH7100_RST_E24) |
/* STATUS3 */
0,
};
static int __init jh7100_reset_probe(struct platform_device *pdev)
{
void __iomem *base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
return reset_starfive_jh7100_register(&pdev->dev, pdev->dev.of_node,
base + JH7100_RESET_ASSERT0,
base + JH7100_RESET_STATUS0,
jh7100_reset_asserted,
JH7100_RSTN_END,
THIS_MODULE);
}
static const struct of_device_id jh7100_reset_dt_ids[] = {
{ .compatible = "starfive,jh7100-reset" },
{ /* sentinel */ }

78
drivers/reset/starfive/reset-starfive-jh71x0.c
View File

@ -10,51 +10,18 @@
#include <linux/io.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/iopoll.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/spinlock.h>
#include "reset-starfive-jh71x0.h"
#include <dt-bindings/reset/starfive-jh7100.h>
/* register offsets */
#define JH7100_RESET_ASSERT0 0x00
#define JH7100_RESET_ASSERT1 0x04
#define JH7100_RESET_ASSERT2 0x08
#define JH7100_RESET_ASSERT3 0x0c
#define JH7100_RESET_STATUS0 0x10
#define JH7100_RESET_STATUS1 0x14
#define JH7100_RESET_STATUS2 0x18
#define JH7100_RESET_STATUS3 0x1c
/*
* Writing a 1 to the n'th bit of the m'th ASSERT register asserts
* line 32m + n, and writing a 0 deasserts the same line.
* Most reset lines have their status inverted so a 0 bit in the STATUS
* register means the line is asserted and a 1 means it's deasserted. A few
* lines don't though, so store the expected value of the status registers when
* all lines are asserted.
*/
static const u64 jh7100_reset_asserted[2] = {
/* STATUS0 */
BIT_ULL_MASK(JH7100_RST_U74) |
BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
/* STATUS1 */
BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
/* STATUS2 */
BIT_ULL_MASK(JH7100_RST_E24) |
/* STATUS3 */
0,
};
struct jh7100_reset {
struct reset_controller_dev rcdev;
/* protect registers against concurrent read-modify-write */
spinlock_t lock;
void __iomem *base;
void __iomem *assert;
void __iomem *status;
const u64 *asserted;
};
static inline struct jh7100_reset *
@ -69,9 +36,9 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev,
struct jh7100_reset *data = jh7100_reset_from(rcdev);
unsigned long offset = BIT_ULL_WORD(id);
u64 mask = BIT_ULL_MASK(id);
void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64);
void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
u64 done = jh7100_reset_asserted[offset] & mask;
void __iomem *reg_assert = data->assert + offset * sizeof(u64);
void __iomem *reg_status = data->status + offset * sizeof(u64);
u64 done = data->asserted ? data->asserted[offset] & mask : 0;
u64 value;
unsigned long flags;
int ret;
@ -125,10 +92,10 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev,
struct jh7100_reset *data = jh7100_reset_from(rcdev);
unsigned long offset = BIT_ULL_WORD(id);
u64 mask = BIT_ULL_MASK(id);
void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
void __iomem *reg_status = data->status + offset * sizeof(u64);
u64 value = readq(reg_status);
return !((value ^ jh7100_reset_asserted[offset]) & mask);
return !((value ^ data->asserted[offset]) & mask);
}
static const struct reset_control_ops jh7100_reset_ops = {
@ -138,25 +105,28 @@ static const struct reset_control_ops jh7100_reset_ops = {
.status = jh7100_reset_status,
};
int jh7100_reset_probe(struct platform_device *pdev)
int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
void __iomem *assert, void __iomem *status,
const u64 *asserted, unsigned int nr_resets,
struct module *owner)
{
struct jh7100_reset *data;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(data->base))
return PTR_ERR(data->base);
data->rcdev.ops = &jh7100_reset_ops;
data->rcdev.owner = THIS_MODULE;
data->rcdev.nr_resets = JH7100_RSTN_END;
data->rcdev.dev = &pdev->dev;
data->rcdev.of_node = pdev->dev.of_node;
spin_lock_init(&data->lock);
data->rcdev.owner = owner;
data->rcdev.nr_resets = nr_resets;
data->rcdev.dev = dev;
data->rcdev.of_node = of_node;
return devm_reset_controller_register(&pdev->dev, &data->rcdev);
spin_lock_init(&data->lock);
data->assert = assert;
data->status = status;
data->asserted = asserted;
return devm_reset_controller_register(dev, &data->rcdev);
}
EXPORT_SYMBOL_GPL(jh7100_reset_probe);
EXPORT_SYMBOL_GPL(reset_starfive_jh7100_register);

5
drivers/reset/starfive/reset-starfive-jh71x0.h
View File

@ -6,6 +6,9 @@
#ifndef __RESET_STARFIVE_JH71X0_H
#define __RESET_STARFIVE_JH71X0_H
int jh7100_reset_probe(struct platform_device *pdev);
int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
void __iomem *assert, void __iomem *status,
const u64 *asserted, unsigned int nr_resets,
struct module *owner);
#endif /* __RESET_STARFIVE_JH71X0_H */