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PCI: designware: Fix configuration base address when using 'reg' 

The code has calculated cfg0_base and cfg1_base when parsing 'reg' or
'ranges' property of PCI DTS node, so remove duplicate calculation.  When
using 'reg', resource cfg is not used, so this code computed an incorrect
configuration base.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
This commit is contained in:
Minghuan Lian 2014-09-23 22:28:56 +08:00 committed by Bjorn Helgaas
parent 9f0dbe087b
commit ec98e9ab6f
1 changed files with 0 additions and 2 deletions
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2
drivers/pci/host/pcie-designware.c
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@ -510,7 +510,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
pp->mem_base = pp->mem.start;
if (!pp->va_cfg0_base) {
pp->cfg0_base = pp->cfg.start;
pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
pp->cfg0_size);
if (!pp->va_cfg0_base) {
@ -520,7 +519,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
}
if (!pp->va_cfg1_base) {
pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
pp->cfg1_size);
if (!pp->va_cfg1_base) {