Merge branches 'clk-ingenic', 'clk-init-leak', 'clk-ux500' and 'clk-bitmain' into clk-next
- Support CGU in Ingenix X1000 - Support Bitmain BM1880 clks * clk-ingenic: clk: ingenic: Allow drivers to be built with COMPILE_TEST clk: Ingenic: Add CGU driver for X1000. dt-bindings: clock: Add X1000 bindings. * clk-init-leak: clk: mark clk_disable_unused() as __init clk: Fix memory leak in clk_unregister() * clk-ux500: MAINTAINERS: Update section for Ux500 clock drivers * clk-bitmain: MAINTAINERS: Add entry for BM1880 SoC clock driver clk: Add common clock driver for BM1880 SoC dt-bindings: clock: Add devicetree binding for BM1880 SoC clk: Add clk_hw_unregister_composite helper function definition clk: Zero init clk_init_data in helpers
This commit is contained in:
Stephen Boyd
commit
ec16ffe36d
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@ -0,0 +1,76 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/clock/bitmain,bm1880-clk.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Bitmain BM1880 Clock Controller
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maintainers:
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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description: |
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The Bitmain BM1880 clock controller generates and supplies clock to
|
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various peripherals within the SoC.
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This binding uses common clock bindings
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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|
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properties:
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compatible:
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const: bitmain,bm1880-clk
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|
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reg:
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items:
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- description: pll registers
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- description: system registers
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|
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reg-names:
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items:
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- const: pll
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- const: sys
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|
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clocks:
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maxItems: 1
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clock-names:
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const: osc
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- '#clock-cells'
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additionalProperties: false
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examples:
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# Clock controller node:
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- |
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clk: clock-controller@e8 {
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compatible = "bitmain,bm1880-clk";
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reg = <0xe8 0x0c>, <0x800 0xb0>;
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reg-names = "pll", "sys";
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clocks = <&osc>;
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clock-names = "osc";
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#clock-cells = <1>;
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};
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# Example UART controller node that consumes clock generated by the clock controller:
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- |
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uart0: serial@58018000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x58018000 0x0 0x2000>;
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clocks = <&clk 45>, <&clk 46>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <0 9 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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...
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|
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@ -11,6 +11,7 @@ Required properties:
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* ingenic,jz4725b-cgu
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* ingenic,jz4770-cgu
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* ingenic,jz4780-cgu
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* ingenic,x1000-cgu
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- reg : The address & length of the CGU registers.
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- clocks : List of phandle & clock specifiers for clocks external to the CGU.
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Two such external clocks should be specified - first the external crystal
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|
|
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|
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@ -1529,8 +1529,10 @@ M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: arch/arm64/boot/dts/bitmain/
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F: drivers/clk/clk-bm1880.c
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F: drivers/pinctrl/pinctrl-bm1880.c
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F: Documentation/devicetree/bindings/arm/bitmain.yaml
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F: Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml
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F: Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt
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ARM/CALXEDA HIGHBANK ARCHITECTURE
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|
|
@ -2490,10 +2492,10 @@ F: drivers/reset/reset-uniphier.c
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F: drivers/tty/serial/8250/8250_uniphier.c
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N: uniphier
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ARM/Ux500 CLOCK FRAMEWORK SUPPORT
|
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Ux500 CLOCK DRIVERS
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M: Ulf Hansson <ulf.hansson@linaro.org>
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L: linux-clk@vger.kernel.org
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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T: git git://git.linaro.org/people/ulfh/clk.git
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S: Maintained
|
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F: drivers/clk/ux500/
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|
|
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|
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@ -136,6 +136,13 @@ config COMMON_CLK_SI570
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This driver supports Silicon Labs 570/571/598/599 programmable
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clock generators.
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config COMMON_CLK_BM1880
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bool "Clock driver for Bitmain BM1880 SoC"
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depends on ARCH_BITMAIN || COMPILE_TEST
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default ARCH_BITMAIN
|
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help
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This driver supports the clocks on Bitmain BM1880 SoC.
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|
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config COMMON_CLK_CDCE706
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tristate "Clock driver for TI CDCE706 clock synthesizer"
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depends on I2C
|
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|
|
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|
|
@ -22,6 +22,7 @@ obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o
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obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
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obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o
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obj-$(CONFIG_COMMON_CLK_BD718XX) += clk-bd718x7.o
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obj-$(CONFIG_COMMON_CLK_BM1880) += clk-bm1880.o
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obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o
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obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
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obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
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|
|
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|
|
@ -0,0 +1,969 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Bitmain BM1880 SoC clock driver
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*
|
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* Copyright (c) 2019 Linaro Ltd.
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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*/
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#include <linux/clk-provider.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
|
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#include <linux/of_device.h>
|
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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|
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#include <dt-bindings/clock/bm1880-clock.h>
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|
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#define BM1880_CLK_MPLL_CTL 0x00
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#define BM1880_CLK_SPLL_CTL 0x04
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#define BM1880_CLK_FPLL_CTL 0x08
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#define BM1880_CLK_DDRPLL_CTL 0x0c
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|
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#define BM1880_CLK_ENABLE0 0x00
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#define BM1880_CLK_ENABLE1 0x04
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#define BM1880_CLK_SELECT 0x20
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#define BM1880_CLK_DIV0 0x40
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#define BM1880_CLK_DIV1 0x44
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#define BM1880_CLK_DIV2 0x48
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#define BM1880_CLK_DIV3 0x4c
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#define BM1880_CLK_DIV4 0x50
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#define BM1880_CLK_DIV5 0x54
|
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#define BM1880_CLK_DIV6 0x58
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#define BM1880_CLK_DIV7 0x5c
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#define BM1880_CLK_DIV8 0x60
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#define BM1880_CLK_DIV9 0x64
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#define BM1880_CLK_DIV10 0x68
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#define BM1880_CLK_DIV11 0x6c
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||||
#define BM1880_CLK_DIV12 0x70
|
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#define BM1880_CLK_DIV13 0x74
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#define BM1880_CLK_DIV14 0x78
|
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#define BM1880_CLK_DIV15 0x7c
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#define BM1880_CLK_DIV16 0x80
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#define BM1880_CLK_DIV17 0x84
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#define BM1880_CLK_DIV18 0x88
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#define BM1880_CLK_DIV19 0x8c
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#define BM1880_CLK_DIV20 0x90
|
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#define BM1880_CLK_DIV21 0x94
|
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#define BM1880_CLK_DIV22 0x98
|
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#define BM1880_CLK_DIV23 0x9c
|
||||
#define BM1880_CLK_DIV24 0xa0
|
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#define BM1880_CLK_DIV25 0xa4
|
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#define BM1880_CLK_DIV26 0xa8
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#define BM1880_CLK_DIV27 0xac
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#define BM1880_CLK_DIV28 0xb0
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|
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#define to_bm1880_pll_clk(_hw) container_of(_hw, struct bm1880_pll_hw_clock, hw)
|
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#define to_bm1880_div_clk(_hw) container_of(_hw, struct bm1880_div_hw_clock, hw)
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|
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static DEFINE_SPINLOCK(bm1880_clk_lock);
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|
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struct bm1880_clock_data {
|
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void __iomem *pll_base;
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void __iomem *sys_base;
|
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struct clk_hw_onecell_data hw_data;
|
||||
};
|
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|
||||
struct bm1880_gate_clock {
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unsigned int id;
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const char *name;
|
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const char *parent;
|
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u32 gate_reg;
|
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s8 gate_shift;
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
struct bm1880_mux_clock {
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const char * const *parents;
|
||||
s8 num_parents;
|
||||
u32 reg;
|
||||
s8 shift;
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
struct bm1880_div_clock {
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unsigned int id;
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const char *name;
|
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u32 reg;
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u8 shift;
|
||||
u8 width;
|
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u32 initval;
|
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const struct clk_div_table *table;
|
||||
unsigned long flags;
|
||||
};
|
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|
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struct bm1880_div_hw_clock {
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struct bm1880_div_clock div;
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void __iomem *base;
|
||||
spinlock_t *lock;
|
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struct clk_hw hw;
|
||||
struct clk_init_data init;
|
||||
};
|
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|
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struct bm1880_composite_clock {
|
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unsigned int id;
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const char *name;
|
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const char *parent;
|
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const char * const *parents;
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unsigned int num_parents;
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unsigned long flags;
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|
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u32 gate_reg;
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u32 mux_reg;
|
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u32 div_reg;
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|
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s8 gate_shift;
|
||||
s8 mux_shift;
|
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s8 div_shift;
|
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s8 div_width;
|
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s16 div_initval;
|
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const struct clk_div_table *table;
|
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};
|
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|
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struct bm1880_pll_clock {
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unsigned int id;
|
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const char *name;
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u32 reg;
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unsigned long flags;
|
||||
};
|
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|
||||
struct bm1880_pll_hw_clock {
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struct bm1880_pll_clock pll;
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void __iomem *base;
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struct clk_hw hw;
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struct clk_init_data init;
|
||||
};
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|
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static const struct clk_ops bm1880_pll_ops;
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static const struct clk_ops bm1880_clk_div_ops;
|
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|
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#define GATE_DIV(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \
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_div_shift, _div_width, _div_initval, _table, \
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_flags) { \
|
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.id = _id, \
|
||||
.parent = _parent, \
|
||||
.name = _name, \
|
||||
.gate_reg = _gate_reg, \
|
||||
.gate_shift = _gate_shift, \
|
||||
.div_reg = _div_reg, \
|
||||
.div_shift = _div_shift, \
|
||||
.div_width = _div_width, \
|
||||
.div_initval = _div_initval, \
|
||||
.table = _table, \
|
||||
.mux_shift = -1, \
|
||||
.flags = _flags, \
|
||||
}
|
||||
|
||||
#define GATE_MUX(_id, _name, _parents, _gate_reg, _gate_shift, \
|
||||
_mux_reg, _mux_shift, _flags) { \
|
||||
.id = _id, \
|
||||
.parents = _parents, \
|
||||
.num_parents = ARRAY_SIZE(_parents), \
|
||||
.name = _name, \
|
||||
.gate_reg = _gate_reg, \
|
||||
.gate_shift = _gate_shift, \
|
||||
.div_shift = -1, \
|
||||
.mux_reg = _mux_reg, \
|
||||
.mux_shift = _mux_shift, \
|
||||
.flags = _flags, \
|
||||
}
|
||||
|
||||
#define CLK_PLL(_id, _name, _parent, _reg, _flags) { \
|
||||
.pll.id = _id, \
|
||||
.pll.name = _name, \
|
||||
.pll.reg = _reg, \
|
||||
.hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, \
|
||||
&bm1880_pll_ops, \
|
||||
_flags), \
|
||||
}
|
||||
|
||||
#define CLK_DIV(_id, _name, _parent, _reg, _shift, _width, _initval, \
|
||||
_table, _flags) { \
|
||||
.div.id = _id, \
|
||||
.div.name = _name, \
|
||||
.div.reg = _reg, \
|
||||
.div.shift = _shift, \
|
||||
.div.width = _width, \
|
||||
.div.initval = _initval, \
|
||||
.div.table = _table, \
|
||||
.hw.init = CLK_HW_INIT_HW(_name, _parent, \
|
||||
&bm1880_clk_div_ops, \
|
||||
_flags), \
|
||||
}
|
||||
|
||||
static struct clk_parent_data bm1880_pll_parent[] = {
|
||||
{ .fw_name = "osc", .name = "osc" },
|
||||
};
|
||||
|
||||
/*
|
||||
* All PLL clocks are marked as CRITICAL, hence they are very crucial
|
||||
* for the functioning of the SoC
|
||||
*/
|
||||
static struct bm1880_pll_hw_clock bm1880_pll_clks[] = {
|
||||
CLK_PLL(BM1880_CLK_MPLL, "clk_mpll", bm1880_pll_parent,
|
||||
BM1880_CLK_MPLL_CTL, 0),
|
||||
CLK_PLL(BM1880_CLK_SPLL, "clk_spll", bm1880_pll_parent,
|
||||
BM1880_CLK_SPLL_CTL, 0),
|
||||
CLK_PLL(BM1880_CLK_FPLL, "clk_fpll", bm1880_pll_parent,
|
||||
BM1880_CLK_FPLL_CTL, 0),
|
||||
CLK_PLL(BM1880_CLK_DDRPLL, "clk_ddrpll", bm1880_pll_parent,
|
||||
BM1880_CLK_DDRPLL_CTL, 0),
|
||||
};
|
||||
|
||||
/*
|
||||
* Clocks marked as CRITICAL are needed for the proper functioning
|
||||
* of the SoC.
|
||||
*/
|
||||
static const struct bm1880_gate_clock bm1880_gate_clks[] = {
|
||||
{ BM1880_CLK_AHB_ROM, "clk_ahb_rom", "clk_mux_axi6",
|
||||
BM1880_CLK_ENABLE0, 2, 0 },
|
||||
{ BM1880_CLK_AXI_SRAM, "clk_axi_sram", "clk_axi1",
|
||||
BM1880_CLK_ENABLE0, 3, 0 },
|
||||
/*
|
||||
* Since this clock is sourcing the DDR memory, let's mark it as
|
||||
* critical to avoid gating.
|
||||
*/
|
||||
{ BM1880_CLK_DDR_AXI, "clk_ddr_axi", "clk_mux_axi6",
|
||||
BM1880_CLK_ENABLE0, 4, CLK_IS_CRITICAL },
|
||||
{ BM1880_CLK_APB_EFUSE, "clk_apb_efuse", "clk_mux_axi6",
|
||||
BM1880_CLK_ENABLE0, 6, 0 },
|
||||
{ BM1880_CLK_AXI5_EMMC, "clk_axi5_emmc", "clk_axi5",
|
||||
BM1880_CLK_ENABLE0, 7, 0 },
|
||||
{ BM1880_CLK_AXI5_SD, "clk_axi5_sd", "clk_axi5",
|
||||
BM1880_CLK_ENABLE0, 10, 0 },
|
||||
{ BM1880_CLK_AXI4_ETH0, "clk_axi4_eth0", "clk_axi4",
|
||||
BM1880_CLK_ENABLE0, 14, 0 },
|
||||
{ BM1880_CLK_AXI4_ETH1, "clk_axi4_eth1", "clk_axi4",
|
||||
BM1880_CLK_ENABLE0, 16, 0 },
|
||||
{ BM1880_CLK_AXI1_GDMA, "clk_axi1_gdma", "clk_axi1",
|
||||
BM1880_CLK_ENABLE0, 17, 0 },
|
||||
/* Don't gate GPIO clocks as it is not owned by the GPIO driver */
|
||||
{ BM1880_CLK_APB_GPIO, "clk_apb_gpio", "clk_mux_axi6",
|
||||
BM1880_CLK_ENABLE0, 18, CLK_IGNORE_UNUSED },
|
||||
{ BM1880_CLK_APB_GPIO_INTR, "clk_apb_gpio_intr", "clk_mux_axi6",
|
||||
BM1880_CLK_ENABLE0, 19, CLK_IGNORE_UNUSED },
|
||||
{ BM1880_CLK_AXI1_MINER, "clk_axi1_miner", "clk_axi1",
|
||||
BM1880_CLK_ENABLE0, 21, 0 },
|
||||
{ BM1880_CLK_AHB_SF, "clk_ahb_sf", "clk_mux_axi6",
|
||||
BM1880_CLK_ENABLE0, 22, 0 },
|
||||
/*
|
||||
* Not sure which module this clock is sourcing but gating this clock
|
||||
* prevents the system from booting. So, let's mark it as critical.
|
||||
*/
|
||||
{ BM1880_CLK_SDMA_AXI, "clk_sdma_axi", "clk_axi5",
|
||||
BM1880_CLK_ENABLE0, 23, CLK_IS_CRITICAL },
|
||||
{ BM1880_CLK_APB_I2C, "clk_apb_i2c", "clk_mux_axi6",
|
||||
BM1880_CLK_ENABLE0, 25, 0 },
|
||||
{ BM1880_CLK_APB_WDT, "clk_apb_wdt", "clk_mux_axi6",
|
||||
BM1880_CLK_ENABLE0, 26, 0 },
|
||||
{ BM1880_CLK_APB_JPEG, "clk_apb_jpeg", "clk_axi6",
|
||||
BM1880_CLK_ENABLE0, 27, 0 },
|
||||
{ BM1880_CLK_AXI5_NF, "clk_axi5_nf", "clk_axi5",
|
||||
BM1880_CLK_ENABLE0, 29, 0 },
|
||||
{ BM1880_CLK_APB_NF, "clk_apb_nf", "clk_axi6",
|
||||
BM1880_CLK_ENABLE0, 30, 0 },
|
||||
{ BM1880_CLK_APB_PWM, "clk_apb_pwm", "clk_mux_axi6",
|
||||
BM1880_CLK_ENABLE1, 0, 0 },
|
||||
{ BM1880_CLK_RV, "clk_rv", "clk_mux_rv",
|
||||
BM1880_CLK_ENABLE1, 1, 0 },
|
||||
{ BM1880_CLK_APB_SPI, "clk_apb_spi", "clk_mux_axi6",
|
||||
BM1880_CLK_ENABLE1, 2, 0 },
|
||||
{ BM1880_CLK_UART_500M, "clk_uart_500m", "clk_div_uart_500m",
|
||||
BM1880_CLK_ENABLE1, 4, 0 },
|
||||
{ BM1880_CLK_APB_UART, "clk_apb_uart", "clk_axi6",
|
||||
BM1880_CLK_ENABLE1, 5, 0 },
|
||||
{ BM1880_CLK_APB_I2S, "clk_apb_i2s", "clk_axi6",
|
||||
BM1880_CLK_ENABLE1, 6, 0 },
|
||||
{ BM1880_CLK_AXI4_USB, "clk_axi4_usb", "clk_axi4",
|
||||
BM1880_CLK_ENABLE1, 7, 0 },
|
||||
{ BM1880_CLK_APB_USB, "clk_apb_usb", "clk_axi6",
|
||||
BM1880_CLK_ENABLE1, 8, 0 },
|
||||
{ BM1880_CLK_12M_USB, "clk_12m_usb", "clk_div_12m_usb",
|
||||
BM1880_CLK_ENABLE1, 11, 0 },
|
||||
{ BM1880_CLK_APB_VIDEO, "clk_apb_video", "clk_axi6",
|
||||
BM1880_CLK_ENABLE1, 12, 0 },
|
||||
{ BM1880_CLK_APB_VPP, "clk_apb_vpp", "clk_axi6",
|
||||
BM1880_CLK_ENABLE1, 15, 0 },
|
||||
{ BM1880_CLK_AXI6, "clk_axi6", "clk_mux_axi6",
|
||||
BM1880_CLK_ENABLE1, 21, 0 },
|
||||
};
|
||||
|
||||
static const char * const clk_a53_parents[] = { "clk_spll", "clk_mpll" };
|
||||
static const char * const clk_rv_parents[] = { "clk_div_1_rv", "clk_div_0_rv" };
|
||||
static const char * const clk_axi1_parents[] = { "clk_div_1_axi1", "clk_div_0_axi1" };
|
||||
static const char * const clk_axi6_parents[] = { "clk_div_1_axi6", "clk_div_0_axi6" };
|
||||
|
||||
static const struct bm1880_mux_clock bm1880_mux_clks[] = {
|
||||
{ BM1880_CLK_MUX_RV, "clk_mux_rv", clk_rv_parents, 2,
|
||||
BM1880_CLK_SELECT, 1, 0 },
|
||||
{ BM1880_CLK_MUX_AXI6, "clk_mux_axi6", clk_axi6_parents, 2,
|
||||
BM1880_CLK_SELECT, 3, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_div_table bm1880_div_table_0[] = {
|
||||
{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
|
||||
{ 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
|
||||
{ 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
|
||||
{ 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 },
|
||||
{ 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 },
|
||||
{ 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 },
|
||||
{ 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 },
|
||||
{ 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 },
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static const struct clk_div_table bm1880_div_table_1[] = {
|
||||
{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
|
||||
{ 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
|
||||
{ 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
|
||||
{ 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 },
|
||||
{ 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 },
|
||||
{ 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 },
|
||||
{ 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 },
|
||||
{ 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 },
|
||||
{ 127, 128 }, { 0, 0 }
|
||||
};
|
||||
|
||||
static const struct clk_div_table bm1880_div_table_2[] = {
|
||||
{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
|
||||
{ 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
|
||||
{ 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
|
||||
{ 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 },
|
||||
{ 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 },
|
||||
{ 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 },
|
||||
{ 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 },
|
||||
{ 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 },
|
||||
{ 127, 128 }, { 255, 256 }, { 0, 0 }
|
||||
};
|
||||
|
||||
static const struct clk_div_table bm1880_div_table_3[] = {
|
||||
{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
|
||||
{ 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
|
||||
{ 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
|
||||
{ 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 },
|
||||
{ 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 },
|
||||
{ 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 },
|
||||
{ 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 },
|
||||
{ 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 },
|
||||
{ 127, 128 }, { 255, 256 }, { 511, 512 }, { 0, 0 }
|
||||
};
|
||||
|
||||
static const struct clk_div_table bm1880_div_table_4[] = {
|
||||
{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
|
||||
{ 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
|
||||
{ 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
|
||||
{ 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 },
|
||||
{ 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 },
|
||||
{ 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 },
|
||||
{ 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 },
|
||||
{ 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 },
|
||||
{ 127, 128 }, { 255, 256 }, { 511, 512 }, { 65535, 65536 },
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
/*
|
||||
* Clocks marked as CRITICAL are needed for the proper functioning
|
||||
* of the SoC.
|
||||
*/
|
||||
static struct bm1880_div_hw_clock bm1880_div_clks[] = {
|
||||
CLK_DIV(BM1880_CLK_DIV_0_RV, "clk_div_0_rv", &bm1880_pll_clks[1].hw,
|
||||
BM1880_CLK_DIV12, 16, 5, 1, bm1880_div_table_0, 0),
|
||||
CLK_DIV(BM1880_CLK_DIV_1_RV, "clk_div_1_rv", &bm1880_pll_clks[2].hw,
|
||||
BM1880_CLK_DIV13, 16, 5, 1, bm1880_div_table_0, 0),
|
||||
CLK_DIV(BM1880_CLK_DIV_UART_500M, "clk_div_uart_500m", &bm1880_pll_clks[2].hw,
|
||||
BM1880_CLK_DIV15, 16, 7, 3, bm1880_div_table_1, 0),
|
||||
CLK_DIV(BM1880_CLK_DIV_0_AXI1, "clk_div_0_axi1", &bm1880_pll_clks[0].hw,
|
||||
BM1880_CLK_DIV21, 16, 5, 2, bm1880_div_table_0,
|
||||
0),
|
||||
CLK_DIV(BM1880_CLK_DIV_1_AXI1, "clk_div_1_axi1", &bm1880_pll_clks[2].hw,
|
||||
BM1880_CLK_DIV22, 16, 5, 3, bm1880_div_table_0,
|
||||
0),
|
||||
CLK_DIV(BM1880_CLK_DIV_0_AXI6, "clk_div_0_axi6", &bm1880_pll_clks[2].hw,
|
||||
BM1880_CLK_DIV27, 16, 5, 15, bm1880_div_table_0,
|
||||
0),
|
||||
CLK_DIV(BM1880_CLK_DIV_1_AXI6, "clk_div_1_axi6", &bm1880_pll_clks[0].hw,
|
||||
BM1880_CLK_DIV28, 16, 5, 11, bm1880_div_table_0,
|
||||
0),
|
||||
CLK_DIV(BM1880_CLK_DIV_12M_USB, "clk_div_12m_usb", &bm1880_pll_clks[2].hw,
|
||||
BM1880_CLK_DIV18, 16, 7, 125, bm1880_div_table_1, 0),
|
||||
};
|
||||
|
||||
/*
|
||||
* Clocks marked as CRITICAL are all needed for the proper functioning
|
||||
* of the SoC.
|
||||
*/
|
||||
static struct bm1880_composite_clock bm1880_composite_clks[] = {
|
||||
/*
|
||||
* Since clk_a53 and clk_50m_a53 clocks are sourcing the CPU core,
|
||||
* let's mark them as critical to avoid gating.
|
||||
*/
|
||||
GATE_MUX(BM1880_CLK_A53, "clk_a53", clk_a53_parents,
|
||||
BM1880_CLK_ENABLE0, 0, BM1880_CLK_SELECT, 0,
|
||||
CLK_IS_CRITICAL),
|
||||
GATE_DIV(BM1880_CLK_50M_A53, "clk_50m_a53", "clk_fpll",
|
||||
BM1880_CLK_ENABLE0, 1, BM1880_CLK_DIV0, 16, 5, 30,
|
||||
bm1880_div_table_0, CLK_IS_CRITICAL),
|
||||
GATE_DIV(BM1880_CLK_EFUSE, "clk_efuse", "clk_fpll",
|
||||
BM1880_CLK_ENABLE0, 5, BM1880_CLK_DIV1, 16, 7, 60,
|
||||
bm1880_div_table_1, 0),
|
||||
GATE_DIV(BM1880_CLK_EMMC, "clk_emmc", "clk_fpll",
|
||||
BM1880_CLK_ENABLE0, 8, BM1880_CLK_DIV2, 16, 5, 15,
|
||||
bm1880_div_table_0, 0),
|
||||
GATE_DIV(BM1880_CLK_100K_EMMC, "clk_100k_emmc", "clk_div_12m_usb",
|
||||
BM1880_CLK_ENABLE0, 9, BM1880_CLK_DIV3, 16, 8, 120,
|
||||
bm1880_div_table_2, 0),
|
||||
GATE_DIV(BM1880_CLK_SD, "clk_sd", "clk_fpll",
|
||||
BM1880_CLK_ENABLE0, 11, BM1880_CLK_DIV4, 16, 5, 15,
|
||||
bm1880_div_table_0, 0),
|
||||
GATE_DIV(BM1880_CLK_100K_SD, "clk_100k_sd", "clk_div_12m_usb",
|
||||
BM1880_CLK_ENABLE0, 12, BM1880_CLK_DIV5, 16, 8, 120,
|
||||
bm1880_div_table_2, 0),
|
||||
GATE_DIV(BM1880_CLK_500M_ETH0, "clk_500m_eth0", "clk_fpll",
|
||||
BM1880_CLK_ENABLE0, 13, BM1880_CLK_DIV6, 16, 5, 3,
|
||||
bm1880_div_table_0, 0),
|
||||
GATE_DIV(BM1880_CLK_500M_ETH1, "clk_500m_eth1", "clk_fpll",
|
||||
BM1880_CLK_ENABLE0, 15, BM1880_CLK_DIV7, 16, 5, 3,
|
||||
bm1880_div_table_0, 0),
|
||||
/* Don't gate GPIO clocks as it is not owned by the GPIO driver */
|
||||
GATE_DIV(BM1880_CLK_GPIO_DB, "clk_gpio_db", "clk_div_12m_usb",
|
||||
BM1880_CLK_ENABLE0, 20, BM1880_CLK_DIV8, 16, 16, 120,
|
||||
bm1880_div_table_4, CLK_IGNORE_UNUSED),
|
||||
GATE_DIV(BM1880_CLK_SDMA_AUD, "clk_sdma_aud", "clk_fpll",
|
||||
BM1880_CLK_ENABLE0, 24, BM1880_CLK_DIV9, 16, 7, 61,
|
||||
bm1880_div_table_1, 0),
|
||||
GATE_DIV(BM1880_CLK_JPEG_AXI, "clk_jpeg_axi", "clk_fpll",
|
||||
BM1880_CLK_ENABLE0, 28, BM1880_CLK_DIV10, 16, 5, 4,
|
||||
bm1880_div_table_0, 0),
|
||||
GATE_DIV(BM1880_CLK_NF, "clk_nf", "clk_fpll",
|
||||
BM1880_CLK_ENABLE0, 31, BM1880_CLK_DIV11, 16, 5, 30,
|
||||
bm1880_div_table_0, 0),
|
||||
GATE_DIV(BM1880_CLK_TPU_AXI, "clk_tpu_axi", "clk_spll",
|
||||
BM1880_CLK_ENABLE1, 3, BM1880_CLK_DIV14, 16, 5, 1,
|
||||
bm1880_div_table_0, 0),
|
||||
GATE_DIV(BM1880_CLK_125M_USB, "clk_125m_usb", "clk_fpll",
|
||||
BM1880_CLK_ENABLE1, 9, BM1880_CLK_DIV16, 16, 5, 12,
|
||||
bm1880_div_table_0, 0),
|
||||
GATE_DIV(BM1880_CLK_33K_USB, "clk_33k_usb", "clk_div_12m_usb",
|
||||
BM1880_CLK_ENABLE1, 10, BM1880_CLK_DIV17, 16, 9, 363,
|
||||
bm1880_div_table_3, 0),
|
||||
GATE_DIV(BM1880_CLK_VIDEO_AXI, "clk_video_axi", "clk_fpll",
|
||||
BM1880_CLK_ENABLE1, 13, BM1880_CLK_DIV19, 16, 5, 4,
|
||||
bm1880_div_table_0, 0),
|
||||
GATE_DIV(BM1880_CLK_VPP_AXI, "clk_vpp_axi", "clk_fpll",
|
||||
BM1880_CLK_ENABLE1, 14, BM1880_CLK_DIV20, 16, 5, 4,
|
||||
bm1880_div_table_0, 0),
|
||||
GATE_MUX(BM1880_CLK_AXI1, "clk_axi1", clk_axi1_parents,
|
||||
BM1880_CLK_ENABLE1, 15, BM1880_CLK_SELECT, 2, 0),
|
||||
GATE_DIV(BM1880_CLK_AXI2, "clk_axi2", "clk_fpll",
|
||||
BM1880_CLK_ENABLE1, 17, BM1880_CLK_DIV23, 16, 5, 3,
|
||||
bm1880_div_table_0, 0),
|
||||
GATE_DIV(BM1880_CLK_AXI3, "clk_axi3", "clk_mux_rv",
|
||||
BM1880_CLK_ENABLE1, 18, BM1880_CLK_DIV24, 16, 5, 2,
|
||||
bm1880_div_table_0, 0),
|
||||
GATE_DIV(BM1880_CLK_AXI4, "clk_axi4", "clk_fpll",
|
||||
BM1880_CLK_ENABLE1, 19, BM1880_CLK_DIV25, 16, 5, 6,
|
||||
bm1880_div_table_0, 0),
|
||||
GATE_DIV(BM1880_CLK_AXI5, "clk_axi5", "clk_fpll",
|
||||
BM1880_CLK_ENABLE1, 20, BM1880_CLK_DIV26, 16, 5, 15,
|
||||
bm1880_div_table_0, 0),
|
||||
};
|
||||
|
||||
static unsigned long bm1880_pll_rate_calc(u32 regval, unsigned long parent_rate)
|
||||
{
|
||||
u64 numerator;
|
||||
u32 fbdiv, fref, refdiv;
|
||||
u32 postdiv1, postdiv2, denominator;
|
||||
|
||||
fbdiv = (regval >> 16) & 0xfff;
|
||||
fref = parent_rate;
|
||||
refdiv = regval & 0x1f;
|
||||
postdiv1 = (regval >> 8) & 0x7;
|
||||
postdiv2 = (regval >> 12) & 0x7;
|
||||
|
||||
numerator = parent_rate * fbdiv;
|
||||
denominator = refdiv * postdiv1 * postdiv2;
|
||||
do_div(numerator, denominator);
|
||||
|
||||
return (unsigned long)numerator;
|
||||
}
|
||||
|
||||
static unsigned long bm1880_pll_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct bm1880_pll_hw_clock *pll_hw = to_bm1880_pll_clk(hw);
|
||||
unsigned long rate;
|
||||
u32 regval;
|
||||
|
||||
regval = readl(pll_hw->base + pll_hw->pll.reg);
|
||||
rate = bm1880_pll_rate_calc(regval, parent_rate);
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
static const struct clk_ops bm1880_pll_ops = {
|
||||
.recalc_rate = bm1880_pll_recalc_rate,
|
||||
};
|
||||
|
||||
static struct clk_hw *bm1880_clk_register_pll(struct bm1880_pll_hw_clock *pll_clk,
|
||||
void __iomem *sys_base)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
int err;
|
||||
|
||||
pll_clk->base = sys_base;
|
||||
hw = &pll_clk->hw;
|
||||
|
||||
err = clk_hw_register(NULL, hw);
|
||||
if (err)
|
||||
return ERR_PTR(err);
|
||||
|
||||
return hw;
|
||||
}
|
||||
|
||||
static void bm1880_clk_unregister_pll(struct clk_hw *hw)
|
||||
{
|
||||
struct bm1880_pll_hw_clock *pll_hw = to_bm1880_pll_clk(hw);
|
||||
|
||||
clk_hw_unregister(hw);
|
||||
kfree(pll_hw);
|
||||
}
|
||||
|
||||
static int bm1880_clk_register_plls(struct bm1880_pll_hw_clock *clks,
|
||||
int num_clks,
|
||||
struct bm1880_clock_data *data)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
void __iomem *pll_base = data->pll_base;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < num_clks; i++) {
|
||||
struct bm1880_pll_hw_clock *bm1880_clk = &clks[i];
|
||||
|
||||
hw = bm1880_clk_register_pll(bm1880_clk, pll_base);
|
||||
if (IS_ERR(hw)) {
|
||||
pr_err("%s: failed to register clock %s\n",
|
||||
__func__, bm1880_clk->pll.name);
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
data->hw_data.hws[clks[i].pll.id] = hw;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_clk:
|
||||
while (i--)
|
||||
bm1880_clk_unregister_pll(data->hw_data.hws[clks[i].pll.id]);
|
||||
|
||||
return PTR_ERR(hw);
|
||||
}
|
||||
|
||||
static int bm1880_clk_register_mux(const struct bm1880_mux_clock *clks,
|
||||
int num_clks,
|
||||
struct bm1880_clock_data *data)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
void __iomem *sys_base = data->sys_base;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < num_clks; i++) {
|
||||
hw = clk_hw_register_mux(NULL, clks[i].name,
|
||||
clks[i].parents,
|
||||
clks[i].num_parents,
|
||||
clks[i].flags,
|
||||
sys_base + clks[i].reg,
|
||||
clks[i].shift, 1, 0,
|
||||
&bm1880_clk_lock);
|
||||
if (IS_ERR(hw)) {
|
||||
pr_err("%s: failed to register clock %s\n",
|
||||
__func__, clks[i].name);
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
data->hw_data.hws[clks[i].id] = hw;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_clk:
|
||||
while (i--)
|
||||
clk_hw_unregister_mux(data->hw_data.hws[clks[i].id]);
|
||||
|
||||
return PTR_ERR(hw);
|
||||
}
|
||||
|
||||
static unsigned long bm1880_clk_div_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw);
|
||||
struct bm1880_div_clock *div = &div_hw->div;
|
||||
void __iomem *reg_addr = div_hw->base + div->reg;
|
||||
unsigned int val;
|
||||
unsigned long rate;
|
||||
|
||||
if (!(readl(reg_addr) & BIT(3))) {
|
||||
val = div->initval;
|
||||
} else {
|
||||
val = readl(reg_addr) >> div->shift;
|
||||
val &= clk_div_mask(div->width);
|
||||
}
|
||||
|
||||
rate = divider_recalc_rate(hw, parent_rate, val, div->table,
|
||||
div->flags, div->width);
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
static long bm1880_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw);
|
||||
struct bm1880_div_clock *div = &div_hw->div;
|
||||
void __iomem *reg_addr = div_hw->base + div->reg;
|
||||
|
||||
if (div->flags & CLK_DIVIDER_READ_ONLY) {
|
||||
u32 val;
|
||||
|
||||
val = readl(reg_addr) >> div->shift;
|
||||
val &= clk_div_mask(div->width);
|
||||
|
||||
return divider_ro_round_rate(hw, rate, prate, div->table,
|
||||
div->width, div->flags,
|
||||
val);
|
||||
}
|
||||
|
||||
return divider_round_rate(hw, rate, prate, div->table,
|
||||
div->width, div->flags);
|
||||
}
|
||||
|
||||
static int bm1880_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw);
|
||||
struct bm1880_div_clock *div = &div_hw->div;
|
||||
void __iomem *reg_addr = div_hw->base + div->reg;
|
||||
unsigned long flags = 0;
|
||||
int value;
|
||||
u32 val;
|
||||
|
||||
value = divider_get_val(rate, parent_rate, div->table,
|
||||
div->width, div_hw->div.flags);
|
||||
if (value < 0)
|
||||
return value;
|
||||
|
||||
if (div_hw->lock)
|
||||
spin_lock_irqsave(div_hw->lock, flags);
|
||||
else
|
||||
__acquire(div_hw->lock);
|
||||
|
||||
val = readl(reg_addr);
|
||||
val &= ~(clk_div_mask(div->width) << div_hw->div.shift);
|
||||
val |= (u32)value << div->shift;
|
||||
writel(val, reg_addr);
|
||||
|
||||
if (div_hw->lock)
|
||||
spin_unlock_irqrestore(div_hw->lock, flags);
|
||||
else
|
||||
__release(div_hw->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops bm1880_clk_div_ops = {
|
||||
.recalc_rate = bm1880_clk_div_recalc_rate,
|
||||
.round_rate = bm1880_clk_div_round_rate,
|
||||
.set_rate = bm1880_clk_div_set_rate,
|
||||
};
|
||||
|
||||
static struct clk_hw *bm1880_clk_register_div(struct bm1880_div_hw_clock *div_clk,
|
||||
void __iomem *sys_base)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
int err;
|
||||
|
||||
div_clk->div.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO;
|
||||
div_clk->base = sys_base;
|
||||
div_clk->lock = &bm1880_clk_lock;
|
||||
|
||||
hw = &div_clk->hw;
|
||||
err = clk_hw_register(NULL, hw);
|
||||
if (err)
|
||||
return ERR_PTR(err);
|
||||
|
||||
return hw;
|
||||
}
|
||||
|
||||
static void bm1880_clk_unregister_div(struct clk_hw *hw)
|
||||
{
|
||||
struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw);
|
||||
|
||||
clk_hw_unregister(hw);
|
||||
kfree(div_hw);
|
||||
}
|
||||
|
||||
static int bm1880_clk_register_divs(struct bm1880_div_hw_clock *clks,
|
||||
int num_clks,
|
||||
struct bm1880_clock_data *data)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
void __iomem *sys_base = data->sys_base;
|
||||
unsigned int i, id;
|
||||
|
||||
for (i = 0; i < num_clks; i++) {
|
||||
struct bm1880_div_hw_clock *bm1880_clk = &clks[i];
|
||||
|
||||
hw = bm1880_clk_register_div(bm1880_clk, sys_base);
|
||||
if (IS_ERR(hw)) {
|
||||
pr_err("%s: failed to register clock %s\n",
|
||||
__func__, bm1880_clk->div.name);
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
id = clks[i].div.id;
|
||||
data->hw_data.hws[id] = hw;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_clk:
|
||||
while (i--)
|
||||
bm1880_clk_unregister_div(data->hw_data.hws[clks[i].div.id]);
|
||||
|
||||
return PTR_ERR(hw);
|
||||
}
|
||||
|
||||
static int bm1880_clk_register_gate(const struct bm1880_gate_clock *clks,
|
||||
int num_clks,
|
||||
struct bm1880_clock_data *data)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
void __iomem *sys_base = data->sys_base;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < num_clks; i++) {
|
||||
hw = clk_hw_register_gate(NULL, clks[i].name,
|
||||
clks[i].parent,
|
||||
clks[i].flags,
|
||||
sys_base + clks[i].gate_reg,
|
||||
clks[i].gate_shift, 0,
|
||||
&bm1880_clk_lock);
|
||||
if (IS_ERR(hw)) {
|
||||
pr_err("%s: failed to register clock %s\n",
|
||||
__func__, clks[i].name);
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
data->hw_data.hws[clks[i].id] = hw;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_clk:
|
||||
while (i--)
|
||||
clk_hw_unregister_gate(data->hw_data.hws[clks[i].id]);
|
||||
|
||||
return PTR_ERR(hw);
|
||||
}
|
||||
|
||||
static struct clk_hw *bm1880_clk_register_composite(struct bm1880_composite_clock *clks,
|
||||
void __iomem *sys_base)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
struct clk_mux *mux = NULL;
|
||||
struct clk_gate *gate = NULL;
|
||||
struct bm1880_div_hw_clock *div_hws = NULL;
|
||||
struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *div_hw = NULL;
|
||||
const struct clk_ops *mux_ops = NULL, *gate_ops = NULL, *div_ops = NULL;
|
||||
const char * const *parent_names;
|
||||
const char *parent;
|
||||
int num_parents;
|
||||
int ret;
|
||||
|
||||
if (clks->mux_shift >= 0) {
|
||||
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
|
||||
if (!mux)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
mux->reg = sys_base + clks->mux_reg;
|
||||
mux->mask = 1;
|
||||
mux->shift = clks->mux_shift;
|
||||
mux_hw = &mux->hw;
|
||||
mux_ops = &clk_mux_ops;
|
||||
mux->lock = &bm1880_clk_lock;
|
||||
|
||||
parent_names = clks->parents;
|
||||
num_parents = clks->num_parents;
|
||||
} else {
|
||||
parent = clks->parent;
|
||||
parent_names = &parent;
|
||||
num_parents = 1;
|
||||
}
|
||||
|
||||
if (clks->gate_shift >= 0) {
|
||||
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
||||
if (!gate) {
|
||||
ret = -ENOMEM;
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
gate->reg = sys_base + clks->gate_reg;
|
||||
gate->bit_idx = clks->gate_shift;
|
||||
gate->lock = &bm1880_clk_lock;
|
||||
|
||||
gate_hw = &gate->hw;
|
||||
gate_ops = &clk_gate_ops;
|
||||
}
|
||||
|
||||
if (clks->div_shift >= 0) {
|
||||
div_hws = kzalloc(sizeof(*div_hws), GFP_KERNEL);
|
||||
if (!div_hws) {
|
||||
ret = -ENOMEM;
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
div_hws->base = sys_base;
|
||||
div_hws->div.reg = clks->div_reg;
|
||||
div_hws->div.shift = clks->div_shift;
|
||||
div_hws->div.width = clks->div_width;
|
||||
div_hws->div.table = clks->table;
|
||||
div_hws->div.initval = clks->div_initval;
|
||||
div_hws->lock = &bm1880_clk_lock;
|
||||
div_hws->div.flags = CLK_DIVIDER_ONE_BASED |
|
||||
CLK_DIVIDER_ALLOW_ZERO;
|
||||
|
||||
div_hw = &div_hws->hw;
|
||||
div_ops = &bm1880_clk_div_ops;
|
||||
}
|
||||
|
||||
hw = clk_hw_register_composite(NULL, clks->name, parent_names,
|
||||
num_parents, mux_hw, mux_ops, div_hw,
|
||||
div_ops, gate_hw, gate_ops,
|
||||
clks->flags);
|
||||
|
||||
if (IS_ERR(hw)) {
|
||||
ret = PTR_ERR(hw);
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
return hw;
|
||||
|
||||
err_out:
|
||||
kfree(div_hws);
|
||||
kfree(gate);
|
||||
kfree(mux);
|
||||
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
static int bm1880_clk_register_composites(struct bm1880_composite_clock *clks,
|
||||
int num_clks,
|
||||
struct bm1880_clock_data *data)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
void __iomem *sys_base = data->sys_base;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < num_clks; i++) {
|
||||
struct bm1880_composite_clock *bm1880_clk = &clks[i];
|
||||
|
||||
hw = bm1880_clk_register_composite(bm1880_clk, sys_base);
|
||||
if (IS_ERR(hw)) {
|
||||
pr_err("%s: failed to register clock %s\n",
|
||||
__func__, bm1880_clk->name);
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
data->hw_data.hws[clks[i].id] = hw;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_clk:
|
||||
while (i--)
|
||||
clk_hw_unregister_composite(data->hw_data.hws[clks[i].id]);
|
||||
|
||||
return PTR_ERR(hw);
|
||||
}
|
||||
|
||||
static int bm1880_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct bm1880_clock_data *clk_data;
|
||||
void __iomem *pll_base, *sys_base;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct resource *res;
|
||||
int num_clks, i;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
pll_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(pll_base))
|
||||
return PTR_ERR(pll_base);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
sys_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(sys_base))
|
||||
return PTR_ERR(sys_base);
|
||||
|
||||
num_clks = ARRAY_SIZE(bm1880_pll_clks) +
|
||||
ARRAY_SIZE(bm1880_div_clks) +
|
||||
ARRAY_SIZE(bm1880_mux_clks) +
|
||||
ARRAY_SIZE(bm1880_composite_clks) +
|
||||
ARRAY_SIZE(bm1880_gate_clks);
|
||||
|
||||
clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws,
|
||||
num_clks), GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
clk_data->pll_base = pll_base;
|
||||
clk_data->sys_base = sys_base;
|
||||
|
||||
for (i = 0; i < num_clks; i++)
|
||||
clk_data->hw_data.hws[i] = ERR_PTR(-ENOENT);
|
||||
|
||||
clk_data->hw_data.num = num_clks;
|
||||
|
||||
bm1880_clk_register_plls(bm1880_pll_clks,
|
||||
ARRAY_SIZE(bm1880_pll_clks),
|
||||
clk_data);
|
||||
|
||||
bm1880_clk_register_divs(bm1880_div_clks,
|
||||
ARRAY_SIZE(bm1880_div_clks),
|
||||
clk_data);
|
||||
|
||||
bm1880_clk_register_mux(bm1880_mux_clks,
|
||||
ARRAY_SIZE(bm1880_mux_clks),
|
||||
clk_data);
|
||||
|
||||
bm1880_clk_register_composites(bm1880_composite_clks,
|
||||
ARRAY_SIZE(bm1880_composite_clks),
|
||||
clk_data);
|
||||
|
||||
bm1880_clk_register_gate(bm1880_gate_clks,
|
||||
ARRAY_SIZE(bm1880_gate_clks),
|
||||
clk_data);
|
||||
|
||||
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
|
||||
&clk_data->hw_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id bm1880_of_match[] = {
|
||||
{ .compatible = "bitmain,bm1880-clk", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, bm1880_of_match);
|
||||
|
||||
static struct platform_driver bm1880_clk_driver = {
|
||||
.driver = {
|
||||
.name = "bm1880-clk",
|
||||
.of_match_table = bm1880_of_match,
|
||||
},
|
||||
.probe = bm1880_clk_probe,
|
||||
};
|
||||
module_platform_driver(bm1880_clk_driver);
|
||||
|
||||
MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
|
||||
MODULE_DESCRIPTION("Clock driver for Bitmain BM1880 SoC");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -207,7 +207,7 @@ struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
|
|||
unsigned long flags)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
struct clk_composite *composite;
|
||||
struct clk_ops *clk_composite_ops;
|
||||
int ret;
|
||||
|
|
@ -343,3 +343,14 @@ void clk_unregister_composite(struct clk *clk)
|
|||
clk_unregister(clk);
|
||||
kfree(composite);
|
||||
}
|
||||
|
||||
void clk_hw_unregister_composite(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_composite *composite;
|
||||
|
||||
composite = to_clk_composite(hw);
|
||||
|
||||
clk_hw_unregister(hw);
|
||||
kfree(composite);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_hw_unregister_composite);
|
||||
|
|
|
|||
|
|
@ -471,7 +471,7 @@ static struct clk_hw *_register_divider(struct device *dev, const char *name,
|
|||
{
|
||||
struct clk_divider *div;
|
||||
struct clk_hw *hw;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
int ret;
|
||||
|
||||
if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,
|
|||
{
|
||||
struct clk_fixed_rate *fixed;
|
||||
struct clk_hw *hw;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
int ret;
|
||||
|
||||
/* allocate fixed-rate clock */
|
||||
|
|
|
|||
|
|
@ -141,7 +141,7 @@ struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
|
|||
{
|
||||
struct clk_gate *gate;
|
||||
struct clk_hw *hw;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
int ret;
|
||||
|
||||
if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
|
||||
|
|
|
|||
|
|
@ -153,7 +153,7 @@ struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
|
|||
{
|
||||
struct clk_mux *mux;
|
||||
struct clk_hw *hw;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
u8 width = 0;
|
||||
int ret;
|
||||
|
||||
|
|
|
|||
|
|
@ -1187,7 +1187,7 @@ static void clk_core_disable_unprepare(struct clk_core *core)
|
|||
clk_core_unprepare_lock(core);
|
||||
}
|
||||
|
||||
static void clk_unprepare_unused_subtree(struct clk_core *core)
|
||||
static void __init clk_unprepare_unused_subtree(struct clk_core *core)
|
||||
{
|
||||
struct clk_core *child;
|
||||
|
||||
|
|
@ -1217,7 +1217,7 @@ static void clk_unprepare_unused_subtree(struct clk_core *core)
|
|||
clk_pm_runtime_put(core);
|
||||
}
|
||||
|
||||
static void clk_disable_unused_subtree(struct clk_core *core)
|
||||
static void __init clk_disable_unused_subtree(struct clk_core *core)
|
||||
{
|
||||
struct clk_core *child;
|
||||
unsigned long flags;
|
||||
|
|
@ -1263,7 +1263,7 @@ unprepare_out:
|
|||
clk_core_disable_unprepare(core->parent);
|
||||
}
|
||||
|
||||
static bool clk_ignore_unused;
|
||||
static bool clk_ignore_unused __initdata;
|
||||
static int __init clk_ignore_unused_setup(char *__unused)
|
||||
{
|
||||
clk_ignore_unused = true;
|
||||
|
|
@ -1271,7 +1271,7 @@ static int __init clk_ignore_unused_setup(char *__unused)
|
|||
}
|
||||
__setup("clk_ignore_unused", clk_ignore_unused_setup);
|
||||
|
||||
static int clk_disable_unused(void)
|
||||
static int __init clk_disable_unused(void)
|
||||
{
|
||||
struct clk_core *core;
|
||||
|
||||
|
|
@ -3897,6 +3897,7 @@ void clk_unregister(struct clk *clk)
|
|||
__func__, clk->core->name);
|
||||
|
||||
kref_put(&clk->core->ref, __clk_release);
|
||||
free_clk(clk);
|
||||
unlock:
|
||||
clk_prepare_unlock();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
menu "Ingenic SoCs drivers"
|
||||
depends on MIPS
|
||||
depends on MIPS || COMPILE_TEST
|
||||
|
||||
config INGENIC_CGU_COMMON
|
||||
bool
|
||||
|
|
@ -45,6 +45,16 @@ config INGENIC_CGU_JZ4780
|
|||
|
||||
If building for a JZ4780 SoC, you want to say Y here.
|
||||
|
||||
config INGENIC_CGU_X1000
|
||||
bool "Ingenic X1000 CGU driver"
|
||||
default MACH_X1000
|
||||
select INGENIC_CGU_COMMON
|
||||
help
|
||||
Support the clocks provided by the CGU hardware on Ingenic X1000
|
||||
and compatible SoCs.
|
||||
|
||||
If building for a X1000 SoC, you want to say Y here.
|
||||
|
||||
config INGENIC_TCU_CLK
|
||||
bool "Ingenic JZ47xx TCU clocks driver"
|
||||
default MACH_INGENIC
|
||||
|
|
|
|||
|
|
@ -4,4 +4,5 @@ obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
|
|||
obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
|
||||
obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
|
||||
obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
|
||||
obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o
|
||||
obj-$(CONFIG_INGENIC_TCU_CLK) += tcu.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,274 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* X1000 SoC CGU driver
|
||||
* Copyright (c) 2019 Zhou Yanjie <zhouyanjie@zoho.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/of.h>
|
||||
#include <dt-bindings/clock/x1000-cgu.h>
|
||||
#include "cgu.h"
|
||||
#include "pm.h"
|
||||
|
||||
/* CGU register offsets */
|
||||
#define CGU_REG_CPCCR 0x00
|
||||
#define CGU_REG_APLL 0x10
|
||||
#define CGU_REG_MPLL 0x14
|
||||
#define CGU_REG_CLKGR 0x20
|
||||
#define CGU_REG_OPCR 0x24
|
||||
#define CGU_REG_DDRCDR 0x2c
|
||||
#define CGU_REG_MACCDR 0x54
|
||||
#define CGU_REG_I2SCDR 0x60
|
||||
#define CGU_REG_LPCDR 0x64
|
||||
#define CGU_REG_MSC0CDR 0x68
|
||||
#define CGU_REG_I2SCDR1 0x70
|
||||
#define CGU_REG_SSICDR 0x74
|
||||
#define CGU_REG_CIMCDR 0x7c
|
||||
#define CGU_REG_PCMCDR 0x84
|
||||
#define CGU_REG_MSC1CDR 0xa4
|
||||
#define CGU_REG_CMP_INTR 0xb0
|
||||
#define CGU_REG_CMP_INTRE 0xb4
|
||||
#define CGU_REG_DRCG 0xd0
|
||||
#define CGU_REG_CPCSR 0xd4
|
||||
#define CGU_REG_PCMCDR1 0xe0
|
||||
#define CGU_REG_MACPHYC 0xe8
|
||||
|
||||
/* bits within the OPCR register */
|
||||
#define OPCR_SPENDN0 BIT(7)
|
||||
#define OPCR_SPENDN1 BIT(6)
|
||||
|
||||
static struct ingenic_cgu *cgu;
|
||||
|
||||
static const s8 pll_od_encoding[8] = {
|
||||
0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
|
||||
};
|
||||
|
||||
static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
|
||||
|
||||
/* External clocks */
|
||||
|
||||
[X1000_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
|
||||
[X1000_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
|
||||
|
||||
/* PLLs */
|
||||
|
||||
[X1000_CLK_APLL] = {
|
||||
"apll", CGU_CLK_PLL,
|
||||
.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
|
||||
.pll = {
|
||||
.reg = CGU_REG_APLL,
|
||||
.m_shift = 24,
|
||||
.m_bits = 7,
|
||||
.m_offset = 1,
|
||||
.n_shift = 18,
|
||||
.n_bits = 5,
|
||||
.n_offset = 1,
|
||||
.od_shift = 16,
|
||||
.od_bits = 2,
|
||||
.od_max = 8,
|
||||
.od_encoding = pll_od_encoding,
|
||||
.bypass_bit = 9,
|
||||
.enable_bit = 8,
|
||||
.stable_bit = 10,
|
||||
},
|
||||
},
|
||||
|
||||
[X1000_CLK_MPLL] = {
|
||||
"mpll", CGU_CLK_PLL,
|
||||
.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
|
||||
.pll = {
|
||||
.reg = CGU_REG_MPLL,
|
||||
.m_shift = 24,
|
||||
.m_bits = 7,
|
||||
.m_offset = 1,
|
||||
.n_shift = 18,
|
||||
.n_bits = 5,
|
||||
.n_offset = 1,
|
||||
.od_shift = 16,
|
||||
.od_bits = 2,
|
||||
.od_max = 8,
|
||||
.od_encoding = pll_od_encoding,
|
||||
.bypass_bit = 6,
|
||||
.enable_bit = 7,
|
||||
.stable_bit = 0,
|
||||
},
|
||||
},
|
||||
|
||||
/* Muxes & dividers */
|
||||
|
||||
[X1000_CLK_SCLKA] = {
|
||||
"sclk_a", CGU_CLK_MUX,
|
||||
.parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
|
||||
.mux = { CGU_REG_CPCCR, 30, 2 },
|
||||
},
|
||||
|
||||
[X1000_CLK_CPUMUX] = {
|
||||
"cpu_mux", CGU_CLK_MUX,
|
||||
.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
|
||||
.mux = { CGU_REG_CPCCR, 28, 2 },
|
||||
},
|
||||
|
||||
[X1000_CLK_CPU] = {
|
||||
"cpu", CGU_CLK_DIV,
|
||||
.parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
|
||||
.div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
|
||||
},
|
||||
|
||||
[X1000_CLK_L2CACHE] = {
|
||||
"l2cache", CGU_CLK_DIV,
|
||||
.parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
|
||||
.div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
|
||||
},
|
||||
|
||||
[X1000_CLK_AHB0] = {
|
||||
"ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
|
||||
.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
|
||||
.mux = { CGU_REG_CPCCR, 26, 2 },
|
||||
.div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 },
|
||||
},
|
||||
|
||||
[X1000_CLK_AHB2PMUX] = {
|
||||
"ahb2_apb_mux", CGU_CLK_MUX,
|
||||
.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
|
||||
.mux = { CGU_REG_CPCCR, 24, 2 },
|
||||
},
|
||||
|
||||
[X1000_CLK_AHB2] = {
|
||||
"ahb2", CGU_CLK_DIV,
|
||||
.parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
|
||||
.div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 },
|
||||
},
|
||||
|
||||
[X1000_CLK_PCLK] = {
|
||||
"pclk", CGU_CLK_DIV,
|
||||
.parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
|
||||
.div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
|
||||
},
|
||||
|
||||
[X1000_CLK_DDR] = {
|
||||
"ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
|
||||
.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
|
||||
.mux = { CGU_REG_DDRCDR, 30, 2 },
|
||||
.div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
|
||||
.gate = { CGU_REG_CLKGR, 31 },
|
||||
},
|
||||
|
||||
[X1000_CLK_MAC] = {
|
||||
"mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
|
||||
.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
|
||||
.mux = { CGU_REG_MACCDR, 31, 1 },
|
||||
.div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 },
|
||||
.gate = { CGU_REG_CLKGR, 25 },
|
||||
},
|
||||
|
||||
[X1000_CLK_MSCMUX] = {
|
||||
"msc_mux", CGU_CLK_MUX,
|
||||
.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
|
||||
.mux = { CGU_REG_MSC0CDR, 31, 1 },
|
||||
},
|
||||
|
||||
[X1000_CLK_MSC0] = {
|
||||
"msc0", CGU_CLK_DIV | CGU_CLK_GATE,
|
||||
.parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
|
||||
.div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 },
|
||||
.gate = { CGU_REG_CLKGR, 4 },
|
||||
},
|
||||
|
||||
[X1000_CLK_MSC1] = {
|
||||
"msc1", CGU_CLK_DIV | CGU_CLK_GATE,
|
||||
.parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
|
||||
.div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 },
|
||||
.gate = { CGU_REG_CLKGR, 5 },
|
||||
},
|
||||
|
||||
[X1000_CLK_SSIPLL] = {
|
||||
"ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
|
||||
.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 },
|
||||
.mux = { CGU_REG_SSICDR, 31, 1 },
|
||||
.div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 },
|
||||
},
|
||||
|
||||
[X1000_CLK_SSIMUX] = {
|
||||
"ssi_mux", CGU_CLK_MUX,
|
||||
.parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL, -1, -1 },
|
||||
.mux = { CGU_REG_SSICDR, 30, 1 },
|
||||
},
|
||||
|
||||
/* Gate-only clocks */
|
||||
|
||||
[X1000_CLK_SFC] = {
|
||||
"sfc", CGU_CLK_GATE,
|
||||
.parents = { X1000_CLK_SSIPLL, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR, 2 },
|
||||
},
|
||||
|
||||
[X1000_CLK_I2C0] = {
|
||||
"i2c0", CGU_CLK_GATE,
|
||||
.parents = { X1000_CLK_PCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR, 7 },
|
||||
},
|
||||
|
||||
[X1000_CLK_I2C1] = {
|
||||
"i2c1", CGU_CLK_GATE,
|
||||
.parents = { X1000_CLK_PCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR, 8 },
|
||||
},
|
||||
|
||||
[X1000_CLK_I2C2] = {
|
||||
"i2c2", CGU_CLK_GATE,
|
||||
.parents = { X1000_CLK_PCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR, 9 },
|
||||
},
|
||||
|
||||
[X1000_CLK_UART0] = {
|
||||
"uart0", CGU_CLK_GATE,
|
||||
.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR, 14 },
|
||||
},
|
||||
|
||||
[X1000_CLK_UART1] = {
|
||||
"uart1", CGU_CLK_GATE,
|
||||
.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR, 15 },
|
||||
},
|
||||
|
||||
[X1000_CLK_UART2] = {
|
||||
"uart2", CGU_CLK_GATE,
|
||||
.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR, 16 },
|
||||
},
|
||||
|
||||
[X1000_CLK_SSI] = {
|
||||
"ssi", CGU_CLK_GATE,
|
||||
.parents = { X1000_CLK_SSIMUX, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR, 19 },
|
||||
},
|
||||
|
||||
[X1000_CLK_PDMA] = {
|
||||
"pdma", CGU_CLK_GATE,
|
||||
.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR, 21 },
|
||||
},
|
||||
};
|
||||
|
||||
static void __init x1000_cgu_init(struct device_node *np)
|
||||
{
|
||||
int retval;
|
||||
|
||||
cgu = ingenic_cgu_new(x1000_cgu_clocks,
|
||||
ARRAY_SIZE(x1000_cgu_clocks), np);
|
||||
if (!cgu) {
|
||||
pr_err("%s: failed to initialise CGU\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
retval = ingenic_cgu_register_clocks(cgu);
|
||||
if (retval) {
|
||||
pr_err("%s: failed to register CGU Clocks\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
ingenic_cgu_register_syscore_ops(cgu);
|
||||
}
|
||||
CLK_OF_DECLARE(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Device Tree binding constants for Bitmain BM1880 SoC
|
||||
*
|
||||
* Copyright (c) 2019 Linaro Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_BM1880_H
|
||||
#define __DT_BINDINGS_CLOCK_BM1880_H
|
||||
|
||||
#define BM1880_CLK_OSC 0
|
||||
#define BM1880_CLK_MPLL 1
|
||||
#define BM1880_CLK_SPLL 2
|
||||
#define BM1880_CLK_FPLL 3
|
||||
#define BM1880_CLK_DDRPLL 4
|
||||
#define BM1880_CLK_A53 5
|
||||
#define BM1880_CLK_50M_A53 6
|
||||
#define BM1880_CLK_AHB_ROM 7
|
||||
#define BM1880_CLK_AXI_SRAM 8
|
||||
#define BM1880_CLK_DDR_AXI 9
|
||||
#define BM1880_CLK_EFUSE 10
|
||||
#define BM1880_CLK_APB_EFUSE 11
|
||||
#define BM1880_CLK_AXI5_EMMC 12
|
||||
#define BM1880_CLK_EMMC 13
|
||||
#define BM1880_CLK_100K_EMMC 14
|
||||
#define BM1880_CLK_AXI5_SD 15
|
||||
#define BM1880_CLK_SD 16
|
||||
#define BM1880_CLK_100K_SD 17
|
||||
#define BM1880_CLK_500M_ETH0 18
|
||||
#define BM1880_CLK_AXI4_ETH0 19
|
||||
#define BM1880_CLK_500M_ETH1 20
|
||||
#define BM1880_CLK_AXI4_ETH1 21
|
||||
#define BM1880_CLK_AXI1_GDMA 22
|
||||
#define BM1880_CLK_APB_GPIO 23
|
||||
#define BM1880_CLK_APB_GPIO_INTR 24
|
||||
#define BM1880_CLK_GPIO_DB 25
|
||||
#define BM1880_CLK_AXI1_MINER 26
|
||||
#define BM1880_CLK_AHB_SF 27
|
||||
#define BM1880_CLK_SDMA_AXI 28
|
||||
#define BM1880_CLK_SDMA_AUD 29
|
||||
#define BM1880_CLK_APB_I2C 30
|
||||
#define BM1880_CLK_APB_WDT 31
|
||||
#define BM1880_CLK_APB_JPEG 32
|
||||
#define BM1880_CLK_JPEG_AXI 33
|
||||
#define BM1880_CLK_AXI5_NF 34
|
||||
#define BM1880_CLK_APB_NF 35
|
||||
#define BM1880_CLK_NF 36
|
||||
#define BM1880_CLK_APB_PWM 37
|
||||
#define BM1880_CLK_DIV_0_RV 38
|
||||
#define BM1880_CLK_DIV_1_RV 39
|
||||
#define BM1880_CLK_MUX_RV 40
|
||||
#define BM1880_CLK_RV 41
|
||||
#define BM1880_CLK_APB_SPI 42
|
||||
#define BM1880_CLK_TPU_AXI 43
|
||||
#define BM1880_CLK_DIV_UART_500M 44
|
||||
#define BM1880_CLK_UART_500M 45
|
||||
#define BM1880_CLK_APB_UART 46
|
||||
#define BM1880_CLK_APB_I2S 47
|
||||
#define BM1880_CLK_AXI4_USB 48
|
||||
#define BM1880_CLK_APB_USB 49
|
||||
#define BM1880_CLK_125M_USB 50
|
||||
#define BM1880_CLK_33K_USB 51
|
||||
#define BM1880_CLK_DIV_12M_USB 52
|
||||
#define BM1880_CLK_12M_USB 53
|
||||
#define BM1880_CLK_APB_VIDEO 54
|
||||
#define BM1880_CLK_VIDEO_AXI 55
|
||||
#define BM1880_CLK_VPP_AXI 56
|
||||
#define BM1880_CLK_APB_VPP 57
|
||||
#define BM1880_CLK_DIV_0_AXI1 58
|
||||
#define BM1880_CLK_DIV_1_AXI1 59
|
||||
#define BM1880_CLK_AXI1 60
|
||||
#define BM1880_CLK_AXI2 61
|
||||
#define BM1880_CLK_AXI3 62
|
||||
#define BM1880_CLK_AXI4 63
|
||||
#define BM1880_CLK_AXI5 64
|
||||
#define BM1880_CLK_DIV_0_AXI6 65
|
||||
#define BM1880_CLK_DIV_1_AXI6 66
|
||||
#define BM1880_CLK_MUX_AXI6 67
|
||||
#define BM1880_CLK_AXI6 68
|
||||
#define BM1880_NR_CLKS 69
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_BM1880_H */
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* This header provides clock numbers for the ingenic,x1000-cgu DT binding.
|
||||
*
|
||||
* They are roughly ordered as:
|
||||
* - external clocks
|
||||
* - PLLs
|
||||
* - muxes/dividers in the order they appear in the x1000 programmers manual
|
||||
* - gates in order of their bit in the CLKGR* registers
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__
|
||||
#define __DT_BINDINGS_CLOCK_X1000_CGU_H__
|
||||
|
||||
#define X1000_CLK_EXCLK 0
|
||||
#define X1000_CLK_RTCLK 1
|
||||
#define X1000_CLK_APLL 2
|
||||
#define X1000_CLK_MPLL 3
|
||||
#define X1000_CLK_SCLKA 4
|
||||
#define X1000_CLK_CPUMUX 5
|
||||
#define X1000_CLK_CPU 6
|
||||
#define X1000_CLK_L2CACHE 7
|
||||
#define X1000_CLK_AHB0 8
|
||||
#define X1000_CLK_AHB2PMUX 9
|
||||
#define X1000_CLK_AHB2 10
|
||||
#define X1000_CLK_PCLK 11
|
||||
#define X1000_CLK_DDR 12
|
||||
#define X1000_CLK_MAC 13
|
||||
#define X1000_CLK_MSCMUX 14
|
||||
#define X1000_CLK_MSC0 15
|
||||
#define X1000_CLK_MSC1 16
|
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#define X1000_CLK_SSIPLL 17
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#define X1000_CLK_SSIMUX 18
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#define X1000_CLK_SFC 19
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#define X1000_CLK_I2C0 20
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#define X1000_CLK_I2C1 21
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#define X1000_CLK_I2C2 22
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#define X1000_CLK_UART0 23
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#define X1000_CLK_UART1 24
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#define X1000_CLK_UART2 25
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#define X1000_CLK_SSI 26
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#define X1000_CLK_PDMA 27
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|
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#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
|
||||
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Reference in New Issue