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clk: at91: add register definition for sama7g5's master clock 

Add register definitions for SAMA7G5's master clock. These would be
also used by architecture specific power saving code.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20210719080317.1045832-3-claudiu.beznea@microchip.com
This commit is contained in:
Claudiu Beznea 2021-07-19 11:03:17 +03:00 committed by Nicolas Ferre
parent e73f0f0ee7
commit ec03f18cc2
1 changed files with 26 additions and 0 deletions
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26
include/linux/clk/at91_pmc.h
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@ -137,6 +137,32 @@
#define AT91_PMC_PLLADIV2_ON (1 << 12)
#define AT91_PMC_H32MXDIV BIT(24)
#define AT91_PMC_MCR_V2 0x30 /* Master Clock Register [SAMA7G5 only] */
#define AT91_PMC_MCR_V2_ID_MSK (0xF)
#define AT91_PMC_MCR_V2_ID(_id) ((_id) & AT91_PMC_MCR_V2_ID_MSK)
#define AT91_PMC_MCR_V2_CMD (1 << 7)
#define AT91_PMC_MCR_V2_DIV (7 << 8)
#define AT91_PMC_MCR_V2_DIV1 (0 << 8)
#define AT91_PMC_MCR_V2_DIV2 (1 << 8)
#define AT91_PMC_MCR_V2_DIV4 (2 << 8)
#define AT91_PMC_MCR_V2_DIV8 (3 << 8)
#define AT91_PMC_MCR_V2_DIV16 (4 << 8)
#define AT91_PMC_MCR_V2_DIV32 (5 << 8)
#define AT91_PMC_MCR_V2_DIV64 (6 << 8)
#define AT91_PMC_MCR_V2_DIV3 (7 << 8)
#define AT91_PMC_MCR_V2_CSS (0x1F << 16)
#define AT91_PMC_MCR_V2_CSS_MD_SLCK (0 << 16)
#define AT91_PMC_MCR_V2_CSS_TD_SLCK (1 << 16)
#define AT91_PMC_MCR_V2_CSS_MAINCK (2 << 16)
#define AT91_PMC_MCR_V2_CSS_MCK0 (3 << 16)
#define AT91_PMC_MCR_V2_CSS_SYSPLL (5 << 16)
#define AT91_PMC_MCR_V2_CSS_DDRPLL (6 << 16)
#define AT91_PMC_MCR_V2_CSS_IMGPLL (7 << 16)
#define AT91_PMC_MCR_V2_CSS_BAUDPLL (8 << 16)
#define AT91_PMC_MCR_V2_CSS_AUDIOPLL (9 << 16)
#define AT91_PMC_MCR_V2_CSS_ETHPLL (10 << 16)
#define AT91_PMC_MCR_V2_EN (1 << 28)
#define AT91_PMC_XTALF 0x34 /* Main XTAL Frequency Register [SAMA7G5 only] */
#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */