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drm/vmwgfx: Update device headers 

Historically our device headers have been forked versions of the
internal device headers, this has made maintaining them a bit
of a burden. To fix the situation, going forward, the device headers
will be verbatim copies of the internal headers.
To do that the driver code has to be adapted to use pristine
device headers. This will make future update to the device
headers trivial and automatic.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Martin Krastev <krastevm@vmware.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210615182336.995192-2-zackr@vmware.com
This commit is contained in:
Zack Rusin 2021-06-15 14:23:33 -04:00
parent 3f35b6b041
commit ebc9ac7c3d
28 changed files with 7066 additions and 10005 deletions
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3
drivers/gpu/drm/vmwgfx/device_include/includeCheck.h
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@ -1,3 +0,0 @@
/*
* Intentionally empty file.
*/

111
drivers/gpu/drm/vmwgfx/device_include/svga3d_caps.h
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@ -1,111 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
* Copyright 2007-2015 VMware, Inc.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
/*
* svga3d_caps.h --
*
* Definitions for SVGA3D hardware capabilities. Capabilities
* are used to query for optional rendering features during
* driver initialization. The capability data is stored as very
* basic key/value dictionary within the "FIFO register" memory
* area at the beginning of BAR2.
*
* Note that these definitions are only for 3D capabilities.
* The SVGA device also has "device capabilities" and "FIFO
* capabilities", which are non-3D-specific and are stored as
* bitfields rather than key/value pairs.
*/
#ifndef _SVGA3D_CAPS_H_
#define _SVGA3D_CAPS_H_
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#include "includeCheck.h"
#include "svga_reg.h"
#define SVGA_FIFO_3D_CAPS_SIZE (SVGA_FIFO_3D_CAPS_LAST - \
SVGA_FIFO_3D_CAPS + 1)
/*
* SVGA3dCapsRecordType
*
* Record types that can be found in the caps block.
* Related record types are grouped together numerically so that
* SVGA3dCaps_FindRecord() can be applied on a range of record
* types.
*/
typedef enum {
SVGA3DCAPS_RECORD_UNKNOWN = 0,
SVGA3DCAPS_RECORD_DEVCAPS_MIN = 0x100,
SVGA3DCAPS_RECORD_DEVCAPS = 0x100,
SVGA3DCAPS_RECORD_DEVCAPS_MAX = 0x1ff,
} SVGA3dCapsRecordType;
/*
* SVGA3dCapsRecordHeader
*
* Header field leading each caps block record. Contains the offset (in
* register words, NOT bytes) to the next caps block record (or the end
* of caps block records which will be a zero word) and the record type
* as defined above.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCapsRecordHeader {
uint32 length;
SVGA3dCapsRecordType type;
}
#include "vmware_pack_end.h"
SVGA3dCapsRecordHeader;
/*
* SVGA3dCapsRecord
*
* Caps block record; "data" is a placeholder for the actual data structure
* contained within the record;
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCapsRecord {
SVGA3dCapsRecordHeader header;
uint32 data[1];
}
#include "vmware_pack_end.h"
SVGA3dCapsRecord;
typedef uint32 SVGA3dCapPair[2];
#endif

3272
drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h
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731
drivers/gpu/drm/vmwgfx/device_include/svga3d_devcaps.h
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@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
* Copyright 1998-2019 VMware, Inc.
* Copyright 1998-2021 VMware, Inc.
* SPDX-License-Identifier: GPL-2.0 OR MIT
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
@ -27,484 +27,345 @@
/*
* svga3d_devcaps.h --
*
* SVGA 3d caps definitions
* SVGA 3d caps definitions
*/
#ifndef _SVGA3D_DEVCAPS_H_
#define _SVGA3D_DEVCAPS_H_
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#define INCLUDE_ALLOW_VMCORE
#include "includeCheck.h"
#include "svga3d_types.h"
/*
* 3D Hardware Version
*
* The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo
* register. Is set by the host and read by the guest. This lets
* us make new guest drivers which are backwards-compatible with old
* SVGA hardware revisions. It does not let us support old guest
* drivers. Good enough for now.
*
*/
#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
#define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF)
#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor)&0xFF))
#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
#define SVGA3D_MINOR_HWVERSION(version) ((version)&0xFF)
typedef enum {
SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1),
SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1,
SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1),
SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1,
} SVGA3dHardwareVersion;
/*
* DevCap indexes.
*/
typedef uint32 SVGA3dDevCapIndex;
#define SVGA3D_DEVCAP_INVALID ((uint32)-1)
#define SVGA3D_DEVCAP_3D 0
#define SVGA3D_DEVCAP_MAX_LIGHTS 1
#define SVGA3D_DEVCAP_INVALID ((uint32)-1)
#define SVGA3D_DEVCAP_3D 0
#define SVGA3D_DEVCAP_MAX_LIGHTS 1
/*
* SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of
* fixed-function texture units available. Each of these units
* work in both FFP and Shader modes, and they support texture
* transforms and texture coordinates. The host may have additional
* texture image units that are only usable with shaders.
*/
#define SVGA3D_DEVCAP_MAX_TEXTURES 2
#define SVGA3D_DEVCAP_MAX_CLIP_PLANES 3
#define SVGA3D_DEVCAP_VERTEX_SHADER_VERSION 4
#define SVGA3D_DEVCAP_VERTEX_SHADER 5
#define SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION 6
#define SVGA3D_DEVCAP_FRAGMENT_SHADER 7
#define SVGA3D_DEVCAP_MAX_RENDER_TARGETS 8
#define SVGA3D_DEVCAP_S23E8_TEXTURES 9
#define SVGA3D_DEVCAP_S10E5_TEXTURES 10
#define SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND 11
#define SVGA3D_DEVCAP_D16_BUFFER_FORMAT 12
#define SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT 13
#define SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT 14
#define SVGA3D_DEVCAP_QUERY_TYPES 15
#define SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING 16
#define SVGA3D_DEVCAP_MAX_POINT_SIZE 17
#define SVGA3D_DEVCAP_MAX_SHADER_TEXTURES 18
#define SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH 19
#define SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT 20
#define SVGA3D_DEVCAP_MAX_VOLUME_EXTENT 21
#define SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT 22
#define SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO 23
#define SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY 24
#define SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT 25
#define SVGA3D_DEVCAP_MAX_VERTEX_INDEX 26
#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS 27
#define SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS 28
#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS 29
#define SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS 30
#define SVGA3D_DEVCAP_TEXTURE_OPS 31
#define SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 32
#define SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 33
#define SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 34
#define SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 35
#define SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 36
#define SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 37
#define SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 38
#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 39
#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 40
#define SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 41
#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 42
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D16 43
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 44
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 45
#define SVGA3D_DEVCAP_SURFACEFMT_DXT1 46
#define SVGA3D_DEVCAP_SURFACEFMT_DXT2 47
#define SVGA3D_DEVCAP_SURFACEFMT_DXT3 48
#define SVGA3D_DEVCAP_SURFACEFMT_DXT4 49
#define SVGA3D_DEVCAP_SURFACEFMT_DXT5 50
#define SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 51
#define SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 52
#define SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 53
#define SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 54
#define SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 55
#define SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 56
#define SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 57
#define SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 58
#define SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 59
#define SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 60
#define SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 61
#define SVGA3D_DEVCAP_MAX_TEXTURES 2
#define SVGA3D_DEVCAP_MAX_CLIP_PLANES 3
#define SVGA3D_DEVCAP_VERTEX_SHADER_VERSION 4
#define SVGA3D_DEVCAP_VERTEX_SHADER 5
#define SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION 6
#define SVGA3D_DEVCAP_FRAGMENT_SHADER 7
#define SVGA3D_DEVCAP_MAX_RENDER_TARGETS 8
#define SVGA3D_DEVCAP_S23E8_TEXTURES 9
#define SVGA3D_DEVCAP_S10E5_TEXTURES 10
#define SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND 11
#define SVGA3D_DEVCAP_D16_BUFFER_FORMAT 12
#define SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT 13
#define SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT 14
#define SVGA3D_DEVCAP_QUERY_TYPES 15
#define SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING 16
#define SVGA3D_DEVCAP_MAX_POINT_SIZE 17
#define SVGA3D_DEVCAP_MAX_SHADER_TEXTURES 18
#define SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH 19
#define SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT 20
#define SVGA3D_DEVCAP_MAX_VOLUME_EXTENT 21
#define SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT 22
#define SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO 23
#define SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY 24
#define SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT 25
#define SVGA3D_DEVCAP_MAX_VERTEX_INDEX 26
#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS 27
#define SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS 28
#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS 29
#define SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS 30
#define SVGA3D_DEVCAP_TEXTURE_OPS 31
#define SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 32
#define SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 33
#define SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 34
#define SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 35
#define SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 36
#define SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 37
#define SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 38
#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 39
#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 40
#define SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 41
#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 42
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D16 43
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 44
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 45
#define SVGA3D_DEVCAP_SURFACEFMT_DXT1 46
#define SVGA3D_DEVCAP_SURFACEFMT_DXT2 47
#define SVGA3D_DEVCAP_SURFACEFMT_DXT3 48
#define SVGA3D_DEVCAP_SURFACEFMT_DXT4 49
#define SVGA3D_DEVCAP_SURFACEFMT_DXT5 50
#define SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 51
#define SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 52
#define SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 53
#define SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 54
#define SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 55
#define SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 56
#define SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 57
#define SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 58
#define SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 59
#define SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 60
#define SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 61
/*
* There is a hole in our devcap definitions for
* historical reasons.
*
* Define a constant just for completeness.
*/
#define SVGA3D_DEVCAP_MISSING62 62
#define SVGA3D_DEVCAP_MISSING62 62
#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES 63
#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES 63
/*
* Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color
* render targets. This does not include the depth or stencil targets.
*/
#define SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS 64
#define SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS 64
#define SVGA3D_DEVCAP_SURFACEFMT_V16U16 65
#define SVGA3D_DEVCAP_SURFACEFMT_G16R16 66
#define SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 67
#define SVGA3D_DEVCAP_SURFACEFMT_UYVY 68
#define SVGA3D_DEVCAP_SURFACEFMT_YUY2 69
#define SVGA3D_DEVCAP_SURFACEFMT_V16U16 65
#define SVGA3D_DEVCAP_SURFACEFMT_G16R16 66
#define SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 67
#define SVGA3D_DEVCAP_SURFACEFMT_UYVY 68
#define SVGA3D_DEVCAP_SURFACEFMT_YUY2 69
/*
* Deprecated.
*/
#define SVGA3D_DEVCAP_DEAD4 70
#define SVGA3D_DEVCAP_DEAD5 71
#define SVGA3D_DEVCAP_DEAD7 72
#define SVGA3D_DEVCAP_DEAD6 73
#define SVGA3D_DEVCAP_DEAD4 70
#define SVGA3D_DEVCAP_DEAD5 71
#define SVGA3D_DEVCAP_DEAD7 72
#define SVGA3D_DEVCAP_DEAD6 73
#define SVGA3D_DEVCAP_AUTOGENMIPMAPS 74
#define SVGA3D_DEVCAP_SURFACEFMT_NV12 75
#define SVGA3D_DEVCAP_DEAD10 76
#define SVGA3D_DEVCAP_AUTOGENMIPMAPS 74
#define SVGA3D_DEVCAP_SURFACEFMT_NV12 75
#define SVGA3D_DEVCAP_DEAD10 76
/*
* This is the maximum number of SVGA context IDs that the guest
* can define using SVGA_3D_CMD_CONTEXT_DEFINE.
*/
#define SVGA3D_DEVCAP_MAX_CONTEXT_IDS 77
#define SVGA3D_DEVCAP_MAX_CONTEXT_IDS 77
/*
* This is the maximum number of SVGA surface IDs that the guest
* can define using SVGA_3D_CMD_SURFACE_DEFINE*.
*/
#define SVGA3D_DEVCAP_MAX_SURFACE_IDS 78
#define SVGA3D_DEVCAP_MAX_SURFACE_IDS 78
#define SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 79
#define SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 80
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT 81
#define SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 79
#define SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 80
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT 81
#define SVGA3D_DEVCAP_SURFACEFMT_ATI1 82
#define SVGA3D_DEVCAP_SURFACEFMT_ATI2 83
#define SVGA3D_DEVCAP_SURFACEFMT_ATI1 82
#define SVGA3D_DEVCAP_SURFACEFMT_ATI2 83
/*
* Deprecated.
*/
#define SVGA3D_DEVCAP_DEAD1 84
#define SVGA3D_DEVCAP_DEAD8 85
#define SVGA3D_DEVCAP_DEAD9 86
#define SVGA3D_DEVCAP_DEAD1 84
#define SVGA3D_DEVCAP_DEAD8 85
#define SVGA3D_DEVCAP_DEAD9 86
#define SVGA3D_DEVCAP_LINE_AA 87 /* boolean */
#define SVGA3D_DEVCAP_LINE_STIPPLE 88 /* boolean */
#define SVGA3D_DEVCAP_MAX_LINE_WIDTH 89 /* float */
#define SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH 90 /* float */
#define SVGA3D_DEVCAP_LINE_AA 87
#define SVGA3D_DEVCAP_LINE_STIPPLE 88
#define SVGA3D_DEVCAP_MAX_LINE_WIDTH 89
#define SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH 90
#define SVGA3D_DEVCAP_SURFACEFMT_YV12 91
#define SVGA3D_DEVCAP_SURFACEFMT_YV12 91
/*
* Deprecated.
*/
#define SVGA3D_DEVCAP_DEAD3 92
#define SVGA3D_DEVCAP_DEAD3 92
/*
* Are TS_CONSTANT, TS_COLOR_KEY, and TS_COLOR_KEY_ENABLE supported?
*/
#define SVGA3D_DEVCAP_TS_COLOR_KEY 93 /* boolean */
#define SVGA3D_DEVCAP_TS_COLOR_KEY 93
/*
* Deprecated.
*/
#define SVGA3D_DEVCAP_DEAD2 94
#define SVGA3D_DEVCAP_DEAD2 94
/*
* Does the device support DXContexts?
*/
#define SVGA3D_DEVCAP_DXCONTEXT 95
#define SVGA3D_DEVCAP_DXCONTEXT 95
/*
* Deprecated.
*/
#define SVGA3D_DEVCAP_DEAD11 96
#define SVGA3D_DEVCAP_DEAD11 96
/*
* What is the maximum number of vertex buffers or vertex input registers
* that can be expected to work correctly with a DXContext?
*
* The guest is allowed to set up to SVGA3D_DX_MAX_VERTEXBUFFERS, but
* anything in excess of this cap is not guaranteed to render correctly.
*
* Similarly, the guest can set up to SVGA3D_DX_MAX_VERTEXINPUTREGISTERS
* input registers without the SVGA3D_DEVCAP_SM4_1 cap, or
* SVGA3D_DX_SM41_MAX_VERTEXINPUTREGISTERS with the SVGA3D_DEVCAP_SM4_1,
* but only the registers up to this cap value are guaranteed to render
* correctly.
*
* If guest-drivers are able to expose a lower-limit, it's recommended
* that they clamp to this value. Otherwise, the host will make a
* best-effort on case-by-case basis if guests exceed this.
*/
#define SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS 97
#define SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS 97
/*
* What is the maximum number of constant buffers that can be expected to
* work correctly with a DX context?
*
* The guest is allowed to set up to SVGA3D_DX_MAX_CONSTBUFFERS, but
* anything in excess of this cap is not guaranteed to render correctly.
*
* If guest-drivers are able to expose a lower-limit, it's recommended
* that they clamp to this value. Otherwise, the host will make a
* best-effort on case-by-case basis if guests exceed this.
*/
#define SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS 98
#define SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS 98
/*
* Does the device support provoking vertex control?
*
* If this cap is present, the provokingVertexLast field in the
* rasterizer state is enabled. (Guests can then set it to FALSE,
* meaning that the first vertex is the provoking vertex, or TRUE,
* meaning that the last verteix is the provoking vertex.)
*
* If this cap is FALSE, then guests should set the provokingVertexLast
* to FALSE, otherwise rendering behavior is undefined.
*/
#define SVGA3D_DEVCAP_DX_PROVOKING_VERTEX 99
#define SVGA3D_DEVCAP_DX_PROVOKING_VERTEX 99
#define SVGA3D_DEVCAP_DXFMT_X8R8G8B8 100
#define SVGA3D_DEVCAP_DXFMT_A8R8G8B8 101
#define SVGA3D_DEVCAP_DXFMT_R5G6B5 102
#define SVGA3D_DEVCAP_DXFMT_X1R5G5B5 103
#define SVGA3D_DEVCAP_DXFMT_A1R5G5B5 104
#define SVGA3D_DEVCAP_DXFMT_A4R4G4B4 105
#define SVGA3D_DEVCAP_DXFMT_Z_D32 106
#define SVGA3D_DEVCAP_DXFMT_Z_D16 107
#define SVGA3D_DEVCAP_DXFMT_Z_D24S8 108
#define SVGA3D_DEVCAP_DXFMT_Z_D15S1 109
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE8 110
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4 111
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE16 112
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8 113
#define SVGA3D_DEVCAP_DXFMT_DXT1 114
#define SVGA3D_DEVCAP_DXFMT_DXT2 115
#define SVGA3D_DEVCAP_DXFMT_DXT3 116
#define SVGA3D_DEVCAP_DXFMT_DXT4 117
#define SVGA3D_DEVCAP_DXFMT_DXT5 118
#define SVGA3D_DEVCAP_DXFMT_BUMPU8V8 119
#define SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5 120
#define SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8 121
#define SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1 122
#define SVGA3D_DEVCAP_DXFMT_ARGB_S10E5 123
#define SVGA3D_DEVCAP_DXFMT_ARGB_S23E8 124
#define SVGA3D_DEVCAP_DXFMT_A2R10G10B10 125
#define SVGA3D_DEVCAP_DXFMT_V8U8 126
#define SVGA3D_DEVCAP_DXFMT_Q8W8V8U8 127
#define SVGA3D_DEVCAP_DXFMT_CxV8U8 128
#define SVGA3D_DEVCAP_DXFMT_X8L8V8U8 129
#define SVGA3D_DEVCAP_DXFMT_A2W10V10U10 130
#define SVGA3D_DEVCAP_DXFMT_ALPHA8 131
#define SVGA3D_DEVCAP_DXFMT_R_S10E5 132
#define SVGA3D_DEVCAP_DXFMT_R_S23E8 133
#define SVGA3D_DEVCAP_DXFMT_RG_S10E5 134
#define SVGA3D_DEVCAP_DXFMT_RG_S23E8 135
#define SVGA3D_DEVCAP_DXFMT_BUFFER 136
#define SVGA3D_DEVCAP_DXFMT_Z_D24X8 137
#define SVGA3D_DEVCAP_DXFMT_V16U16 138
#define SVGA3D_DEVCAP_DXFMT_G16R16 139
#define SVGA3D_DEVCAP_DXFMT_A16B16G16R16 140
#define SVGA3D_DEVCAP_DXFMT_UYVY 141
#define SVGA3D_DEVCAP_DXFMT_YUY2 142
#define SVGA3D_DEVCAP_DXFMT_NV12 143
#define SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2 144
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS 145
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT 146
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT 147
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS 148
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT 149
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT 150
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT 151
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS 152
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT 153
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM 154
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT 155
#define SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS 156
#define SVGA3D_DEVCAP_DXFMT_R32G32_UINT 157
#define SVGA3D_DEVCAP_DXFMT_R32G32_SINT 158
#define SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS 159
#define SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT 160
#define SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24 161
#define SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT 162
#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS 163
#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT 164
#define SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT 165
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS 166
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM 167
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB 168
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT 169
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT 170
#define SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS 171
#define SVGA3D_DEVCAP_DXFMT_R16G16_UINT 172
#define SVGA3D_DEVCAP_DXFMT_R16G16_SINT 173
#define SVGA3D_DEVCAP_DXFMT_R32_TYPELESS 174
#define SVGA3D_DEVCAP_DXFMT_D32_FLOAT 175
#define SVGA3D_DEVCAP_DXFMT_R32_UINT 176
#define SVGA3D_DEVCAP_DXFMT_R32_SINT 177
#define SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS 178
#define SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT 179
#define SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8 180
#define SVGA3D_DEVCAP_DXFMT_X24_G8_UINT 181
#define SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS 182
#define SVGA3D_DEVCAP_DXFMT_R8G8_UNORM 183
#define SVGA3D_DEVCAP_DXFMT_R8G8_UINT 184
#define SVGA3D_DEVCAP_DXFMT_R8G8_SINT 185
#define SVGA3D_DEVCAP_DXFMT_R16_TYPELESS 186
#define SVGA3D_DEVCAP_DXFMT_R16_UNORM 187
#define SVGA3D_DEVCAP_DXFMT_R16_UINT 188
#define SVGA3D_DEVCAP_DXFMT_R16_SNORM 189
#define SVGA3D_DEVCAP_DXFMT_R16_SINT 190
#define SVGA3D_DEVCAP_DXFMT_R8_TYPELESS 191
#define SVGA3D_DEVCAP_DXFMT_R8_UNORM 192
#define SVGA3D_DEVCAP_DXFMT_R8_UINT 193
#define SVGA3D_DEVCAP_DXFMT_R8_SNORM 194
#define SVGA3D_DEVCAP_DXFMT_R8_SINT 195
#define SVGA3D_DEVCAP_DXFMT_P8 196
#define SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP 197
#define SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM 198
#define SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM 199
#define SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS 200
#define SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB 201
#define SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS 202
#define SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB 203
#define SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS 204
#define SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB 205
#define SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS 206
#define SVGA3D_DEVCAP_DXFMT_ATI1 207
#define SVGA3D_DEVCAP_DXFMT_BC4_SNORM 208
#define SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS 209
#define SVGA3D_DEVCAP_DXFMT_ATI2 210
#define SVGA3D_DEVCAP_DXFMT_BC5_SNORM 211
#define SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM 212
#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS 213
#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB 214
#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS 215
#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB 216
#define SVGA3D_DEVCAP_DXFMT_Z_DF16 217
#define SVGA3D_DEVCAP_DXFMT_Z_DF24 218
#define SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT 219
#define SVGA3D_DEVCAP_DXFMT_YV12 220
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT 221
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT 222
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM 223
#define SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT 224
#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM 225
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM 226
#define SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT 227
#define SVGA3D_DEVCAP_DXFMT_R16G16_UNORM 228
#define SVGA3D_DEVCAP_DXFMT_R16G16_SNORM 229
#define SVGA3D_DEVCAP_DXFMT_R32_FLOAT 230
#define SVGA3D_DEVCAP_DXFMT_R8G8_SNORM 231
#define SVGA3D_DEVCAP_DXFMT_R16_FLOAT 232
#define SVGA3D_DEVCAP_DXFMT_D16_UNORM 233
#define SVGA3D_DEVCAP_DXFMT_A8_UNORM 234
#define SVGA3D_DEVCAP_DXFMT_BC1_UNORM 235
#define SVGA3D_DEVCAP_DXFMT_BC2_UNORM 236
#define SVGA3D_DEVCAP_DXFMT_BC3_UNORM 237
#define SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM 238
#define SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM 239
#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM 240
#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM 241
#define SVGA3D_DEVCAP_DXFMT_BC4_UNORM 242
#define SVGA3D_DEVCAP_DXFMT_BC5_UNORM 243
#define SVGA3D_DEVCAP_DXFMT_X8R8G8B8 100
#define SVGA3D_DEVCAP_DXFMT_A8R8G8B8 101
#define SVGA3D_DEVCAP_DXFMT_R5G6B5 102
#define SVGA3D_DEVCAP_DXFMT_X1R5G5B5 103
#define SVGA3D_DEVCAP_DXFMT_A1R5G5B5 104
#define SVGA3D_DEVCAP_DXFMT_A4R4G4B4 105
#define SVGA3D_DEVCAP_DXFMT_Z_D32 106
#define SVGA3D_DEVCAP_DXFMT_Z_D16 107
#define SVGA3D_DEVCAP_DXFMT_Z_D24S8 108
#define SVGA3D_DEVCAP_DXFMT_Z_D15S1 109
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE8 110
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4 111
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE16 112
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8 113
#define SVGA3D_DEVCAP_DXFMT_DXT1 114
#define SVGA3D_DEVCAP_DXFMT_DXT2 115
#define SVGA3D_DEVCAP_DXFMT_DXT3 116
#define SVGA3D_DEVCAP_DXFMT_DXT4 117
#define SVGA3D_DEVCAP_DXFMT_DXT5 118
#define SVGA3D_DEVCAP_DXFMT_BUMPU8V8 119
#define SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5 120
#define SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8 121
#define SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1 122
#define SVGA3D_DEVCAP_DXFMT_ARGB_S10E5 123
#define SVGA3D_DEVCAP_DXFMT_ARGB_S23E8 124
#define SVGA3D_DEVCAP_DXFMT_A2R10G10B10 125
#define SVGA3D_DEVCAP_DXFMT_V8U8 126
#define SVGA3D_DEVCAP_DXFMT_Q8W8V8U8 127
#define SVGA3D_DEVCAP_DXFMT_CxV8U8 128
#define SVGA3D_DEVCAP_DXFMT_X8L8V8U8 129
#define SVGA3D_DEVCAP_DXFMT_A2W10V10U10 130
#define SVGA3D_DEVCAP_DXFMT_ALPHA8 131
#define SVGA3D_DEVCAP_DXFMT_R_S10E5 132
#define SVGA3D_DEVCAP_DXFMT_R_S23E8 133
#define SVGA3D_DEVCAP_DXFMT_RG_S10E5 134
#define SVGA3D_DEVCAP_DXFMT_RG_S23E8 135
#define SVGA3D_DEVCAP_DXFMT_BUFFER 136
#define SVGA3D_DEVCAP_DXFMT_Z_D24X8 137
#define SVGA3D_DEVCAP_DXFMT_V16U16 138
#define SVGA3D_DEVCAP_DXFMT_G16R16 139
#define SVGA3D_DEVCAP_DXFMT_A16B16G16R16 140
#define SVGA3D_DEVCAP_DXFMT_UYVY 141
#define SVGA3D_DEVCAP_DXFMT_YUY2 142
#define SVGA3D_DEVCAP_DXFMT_NV12 143
#define SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2 144
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS 145
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT 146
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT 147
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS 148
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT 149
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT 150
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT 151
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS 152
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT 153
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM 154
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT 155
#define SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS 156
#define SVGA3D_DEVCAP_DXFMT_R32G32_UINT 157
#define SVGA3D_DEVCAP_DXFMT_R32G32_SINT 158
#define SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS 159
#define SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT 160
#define SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24 161
#define SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT 162
#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS 163
#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT 164
#define SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT 165
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS 166
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM 167
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB 168
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT 169
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT 170
#define SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS 171
#define SVGA3D_DEVCAP_DXFMT_R16G16_UINT 172
#define SVGA3D_DEVCAP_DXFMT_R16G16_SINT 173
#define SVGA3D_DEVCAP_DXFMT_R32_TYPELESS 174
#define SVGA3D_DEVCAP_DXFMT_D32_FLOAT 175
#define SVGA3D_DEVCAP_DXFMT_R32_UINT 176
#define SVGA3D_DEVCAP_DXFMT_R32_SINT 177
#define SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS 178
#define SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT 179
#define SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8 180
#define SVGA3D_DEVCAP_DXFMT_X24_G8_UINT 181
#define SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS 182
#define SVGA3D_DEVCAP_DXFMT_R8G8_UNORM 183
#define SVGA3D_DEVCAP_DXFMT_R8G8_UINT 184
#define SVGA3D_DEVCAP_DXFMT_R8G8_SINT 185
#define SVGA3D_DEVCAP_DXFMT_R16_TYPELESS 186
#define SVGA3D_DEVCAP_DXFMT_R16_UNORM 187
#define SVGA3D_DEVCAP_DXFMT_R16_UINT 188
#define SVGA3D_DEVCAP_DXFMT_R16_SNORM 189
#define SVGA3D_DEVCAP_DXFMT_R16_SINT 190
#define SVGA3D_DEVCAP_DXFMT_R8_TYPELESS 191
#define SVGA3D_DEVCAP_DXFMT_R8_UNORM 192
#define SVGA3D_DEVCAP_DXFMT_R8_UINT 193
#define SVGA3D_DEVCAP_DXFMT_R8_SNORM 194
#define SVGA3D_DEVCAP_DXFMT_R8_SINT 195
#define SVGA3D_DEVCAP_DXFMT_P8 196
#define SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP 197
#define SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM 198
#define SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM 199
#define SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS 200
#define SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB 201
#define SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS 202
#define SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB 203
#define SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS 204
#define SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB 205
#define SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS 206
#define SVGA3D_DEVCAP_DXFMT_ATI1 207
#define SVGA3D_DEVCAP_DXFMT_BC4_SNORM 208
#define SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS 209
#define SVGA3D_DEVCAP_DXFMT_ATI2 210
#define SVGA3D_DEVCAP_DXFMT_BC5_SNORM 211
#define SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM 212
#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS 213
#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB 214
#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS 215
#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB 216
#define SVGA3D_DEVCAP_DXFMT_Z_DF16 217
#define SVGA3D_DEVCAP_DXFMT_Z_DF24 218
#define SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT 219
#define SVGA3D_DEVCAP_DXFMT_YV12 220
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT 221
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT 222
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM 223
#define SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT 224
#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM 225
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM 226
#define SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT 227
#define SVGA3D_DEVCAP_DXFMT_R16G16_UNORM 228
#define SVGA3D_DEVCAP_DXFMT_R16G16_SNORM 229
#define SVGA3D_DEVCAP_DXFMT_R32_FLOAT 230
#define SVGA3D_DEVCAP_DXFMT_R8G8_SNORM 231
#define SVGA3D_DEVCAP_DXFMT_R16_FLOAT 232
#define SVGA3D_DEVCAP_DXFMT_D16_UNORM 233
#define SVGA3D_DEVCAP_DXFMT_A8_UNORM 234
#define SVGA3D_DEVCAP_DXFMT_BC1_UNORM 235
#define SVGA3D_DEVCAP_DXFMT_BC2_UNORM 236
#define SVGA3D_DEVCAP_DXFMT_BC3_UNORM 237
#define SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM 238
#define SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM 239
#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM 240
#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM 241
#define SVGA3D_DEVCAP_DXFMT_BC4_UNORM 242
#define SVGA3D_DEVCAP_DXFMT_BC5_UNORM 243
/*
* Advertises shaderModel 4.1 support, independent blend-states,
* cube-map arrays, and a higher vertex input registers limit.
*
* (See documentation on SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS.)
*/
#define SVGA3D_DEVCAP_SM41 244
#define SVGA3D_DEVCAP_MULTISAMPLE_2X 245
#define SVGA3D_DEVCAP_MULTISAMPLE_4X 246
#define SVGA3D_DEVCAP_SM41 244
#define SVGA3D_DEVCAP_MULTISAMPLE_2X 245
#define SVGA3D_DEVCAP_MULTISAMPLE_4X 246
/*
* Indicates that the device has rendering support for
* the full multisample quality. If this cap is not present,
* the host may or may not support full quality rendering.
*
* See also SVGA_REG_MS_HINT_RESOLVED.
*/
#define SVGA3D_DEVCAP_MS_FULL_QUALITY 247
#define SVGA3D_DEVCAP_MS_FULL_QUALITY 247
/*
* Advertises support for the SVGA3D LogicOps commands.
*/
#define SVGA3D_DEVCAP_LOGICOPS 248
#define SVGA3D_DEVCAP_LOGICOPS 248
/*
* Advertises support for using logicOps in the DXBlendStates.
*/
#define SVGA3D_DEVCAP_LOGIC_BLENDOPS 249
#define SVGA3D_DEVCAP_LOGIC_BLENDOPS 249
/*
* Note DXFMT range is now non-contiguous.
*/
#define SVGA3D_DEVCAP_RESERVED_1 250
#define SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS 251
#define SVGA3D_DEVCAP_DXFMT_BC6H_UF16 252
#define SVGA3D_DEVCAP_DXFMT_BC6H_SF16 253
#define SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS 254
#define SVGA3D_DEVCAP_DXFMT_BC7_UNORM 255
#define SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB 256
#define SVGA3D_DEVCAP_RESERVED_2 257
#define SVGA3D_DEVCAP_DEAD12 250
#define SVGA3D_DEVCAP_SM5 258
#define SVGA3D_DEVCAP_MULTISAMPLE_8X 259
#define SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS 251
#define SVGA3D_DEVCAP_DXFMT_BC6H_UF16 252
#define SVGA3D_DEVCAP_DXFMT_BC6H_SF16 253
#define SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS 254
#define SVGA3D_DEVCAP_DXFMT_BC7_UNORM 255
#define SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB 256
/* This must be the last index. */
#define SVGA3D_DEVCAP_MAX 260
#define SVGA3D_DEVCAP_DEAD13 257
/*
* Bit definitions for DXFMT devcaps
*
*
* SUPPORTED: Can the format be defined?
* SHADER_SAMPLE: Can the format be sampled from a shader?
* COLOR_RENDERTARGET: Can the format be a color render target?
* DEPTH_RENDERTARGET: Can the format be a depth render target?
* BLENDABLE: Is the format blendable?
* MIPS: Does the format support mip levels?
* ARRAY: Does the format support texture arrays?
* VOLUME: Does the format support having volume?
* MULTISAMPLE: Does the format support multisample?
*/
#define SVGA3D_DXFMT_SUPPORTED (1 << 0)
#define SVGA3D_DXFMT_SHADER_SAMPLE (1 << 1)
#define SVGA3D_DXFMT_COLOR_RENDERTARGET (1 << 2)
#define SVGA3D_DXFMT_DEPTH_RENDERTARGET (1 << 3)
#define SVGA3D_DXFMT_BLENDABLE (1 << 4)
#define SVGA3D_DXFMT_MIPS (1 << 5)
#define SVGA3D_DXFMT_ARRAY (1 << 6)
#define SVGA3D_DXFMT_VOLUME (1 << 7)
#define SVGA3D_DXFMT_DX_VERTEX_BUFFER (1 << 8)
#define SVGA3D_DXFMT_MULTISAMPLE (1 << 9)
#define SVGA3D_DXFMT_MAX (1 << 10)
#define SVGA3D_DEVCAP_SM5 258
#define SVGA3D_DEVCAP_MULTISAMPLE_8X 259
#define SVGA3D_DEVCAP_MAX 262
#define SVGA3D_DXFMT_SUPPORTED (1 << 0)
#define SVGA3D_DXFMT_SHADER_SAMPLE (1 << 1)
#define SVGA3D_DXFMT_COLOR_RENDERTARGET (1 << 2)
#define SVGA3D_DXFMT_DEPTH_RENDERTARGET (1 << 3)
#define SVGA3D_DXFMT_BLENDABLE (1 << 4)
#define SVGA3D_DXFMT_MIPS (1 << 5)
#define SVGA3D_DXFMT_ARRAY (1 << 6)
#define SVGA3D_DXFMT_VOLUME (1 << 7)
#define SVGA3D_DXFMT_DX_VERTEX_BUFFER (1 << 8)
#define SVGA3D_DXFMT_MULTISAMPLE (1 << 9)
#define SVGA3D_DXFMT_MAX (1 << 10)
typedef union {
SVGA3dBool b;
uint32 u;
int32 i;
float f;
SVGA3dBool b;
uint32 u;
int32 i;
float f;
} SVGA3dDevCapResult;
#endif /* _SVGA3D_DEVCAPS_H_ */
#endif

3169
drivers/gpu/drm/vmwgfx/device_include/svga3d_dx.h
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101
drivers/gpu/drm/vmwgfx/device_include/svga3d_limits.h
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@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
* Copyright 2007-2019 VMware, Inc.
* Copyright 2012-2021 VMware, Inc.
* SPDX-License-Identifier: GPL-2.0 OR MIT
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
@ -27,104 +27,59 @@
/*
* svga3d_limits.h --
*
* SVGA 3d hardware limits
* SVGA 3d hardware limits
*/
#ifndef _SVGA3D_LIMITS_H_
#define _SVGA3D_LIMITS_H_
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#define INCLUDE_ALLOW_VMCORE
#define SVGA3D_HB_MAX_CONTEXT_IDS 256
#define SVGA3D_HB_MAX_SURFACE_IDS (32 * 1024)
#include "includeCheck.h"
#define SVGA3D_DX_MAX_RENDER_TARGETS 8
#define SVGA3D_DX11_MAX_UAVIEWS 8
#define SVGA3D_DX11_1_MAX_UAVIEWS 64
#define SVGA3D_MAX_UAVIEWS (SVGA3D_DX11_1_MAX_UAVIEWS)
#define SVGA3D_DX11_MAX_SIMULTANEOUS_RTUAV (SVGA3D_DX11_MAX_UAVIEWS)
#define SVGA3D_DX11_1_MAX_SIMULTANEOUS_RTUAV (SVGA3D_DX11_1_MAX_UAVIEWS)
#define SVGA3D_MAX_SIMULTANEOUS_RTUAV (SVGA3D_MAX_UAVIEWS)
#define SVGA3D_NUM_CLIPPLANES 6
#define SVGA3D_MAX_CONTEXT_IDS 256
#define SVGA3D_MAX_SURFACE_IDS (32 * 1024)
/*
* While there are separate bind-points for RenderTargetViews and
* UnorderedAccessViews in a DXContext, there is in fact one shared
* semantic space that the guest-driver can use on any given draw call.
* So there are really only 8 slots that can be spilt up between them, with the
* spliceIndex controlling where the UAV's sit in the collapsed array.
*/
#define SVGA3D_MAX_RENDER_TARGETS 8
#define SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS (SVGA3D_MAX_RENDER_TARGETS)
#define SVGA3D_MAX_UAVIEWS 8
#define SVGA3D_DX11_1_MAX_UAVIEWS 64
/*
* Maximum canonical size of a surface in host-backed mode (pre-GBObjects).
*/
#define SVGA3D_HB_MAX_SURFACE_SIZE MBYTES_2_BYTES(128)
/*
* Maximum ID a shader can be assigned on a given context.
*/
#define SVGA3D_MAX_SHADERIDS 5000
/*
* Maximum number of shaders of a given type that can be defined
* (including all contexts).
*/
#define SVGA3D_MAX_SIMULTANEOUS_SHADERS 20000
#define SVGA3D_MAX_SHADERIDS 5000
#define SVGA3D_NUM_TEXTURE_UNITS 32
#define SVGA3D_NUM_LIGHTS 8
#define SVGA3D_MAX_SIMULTANEOUS_SHADERS 20000
#define SVGA3D_MAX_VIDEOPROCESSOR_SAMPLERS 32
#define SVGA3D_NUM_TEXTURE_UNITS 32
#define SVGA3D_NUM_LIGHTS 8
#define SVGA3D_MAX_VIDEOPROCESSOR_SAMPLERS 32
/*
* Maximum size in dwords of shader text the SVGA device will allow.
* Currently 8 MB.
*/
#define SVGA3D_MAX_SHADER_MEMORY_BYTES (8 * 1024 * 1024)
#define SVGA3D_MAX_SHADER_MEMORY (SVGA3D_MAX_SHADER_MEMORY_BYTES / \
sizeof(uint32))
#define SVGA3D_MAX_SHADER_MEMORY \
(SVGA3D_MAX_SHADER_MEMORY_BYTES / sizeof(uint32))
/*
* The maximum value of threadGroupCount in each dimension
*/
#define SVGA3D_MAX_SHADER_THREAD_GROUPS 65535
#define SVGA3D_MAX_CLIP_PLANES 6
#define SVGA3D_MAX_CLIP_PLANES 6
/*
* This is the limit to the number of fixed-function texture
* transforms and texture coordinates we can support. It does *not*
* correspond to the number of texture image units (samplers) we
* support!
*/
#define SVGA3D_MAX_TEXTURE_COORDS 8
/*
* Number of faces in a cubemap.
*/
#define SVGA3D_MAX_SURFACE_FACES 6
/*
* Maximum number of array indexes in a GB surface (with DX enabled).
*/
#define SVGA3D_SM4_MAX_SURFACE_ARRAYSIZE 512
#define SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE 2048
#define SVGA3D_MAX_SURFACE_ARRAYSIZE SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE
/*
* The maximum number of vertex arrays we're guaranteed to support in
* SVGA_3D_CMD_DRAWPRIMITIVES.
*/
#define SVGA3D_MAX_VERTEX_ARRAYS 32
#define SVGA3D_MAX_VERTEX_ARRAYS 32
/*
* The maximum number of primitive ranges we're guaranteed to support
* in SVGA_3D_CMD_DRAWPRIMITIVES.
*/
#define SVGA3D_MAX_DRAW_PRIMITIVE_RANGES 32
/*
* The maximum number of samples that can be contained in a surface.
*/
#define SVGA3D_MAX_SAMPLES 8
#endif /* _SVGA3D_LIMITS_H_ */
#define SVGA3D_MIN_SBX_DATA_SIZE (GBYTES_2_BYTES(1))
#define SVGA3D_MAX_SBX_DATA_SIZE (GBYTES_2_BYTES(4))
#endif

15
drivers/gpu/drm/vmwgfx/device_include/svga3d_reg.h
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@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
* Copyright 1998-2015 VMware, Inc.
* SPDX-License-Identifier: GPL-2.0 OR MIT
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
@ -27,18 +27,14 @@
/*
* svga3d_reg.h --
*
* SVGA 3d hardware definitions
* SVGA 3d hardware definitions
*/
#ifndef _SVGA3D_REG_H_
#define _SVGA3D_REG_H_
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#define INCLUDE_ALLOW_VMCORE
#include "includeCheck.h"
#include "svga_reg.h"
#include "svga3d_types.h"
@ -47,5 +43,4 @@
#include "svga3d_dx.h"
#include "svga3d_devcaps.h"
#endif /* _SVGA3D_REG_H_ */
#endif

3096
drivers/gpu/drm/vmwgfx/device_include/svga3d_surfacedefs.h
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2880
drivers/gpu/drm/vmwgfx/device_include/svga3d_types.h
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68
drivers/gpu/drm/vmwgfx/device_include/svga_escape.h
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@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
* Copyright 2007-2015 VMware, Inc.
* Copyright 2007,2020 VMware, Inc.
* SPDX-License-Identifier: GPL-2.0 OR MIT
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
@ -30,61 +30,27 @@
* Definitions for our own (vendor-specific) SVGA Escape commands.
*/
#ifndef _SVGA_ESCAPE_H_
#define _SVGA_ESCAPE_H_
/*
* Namespace IDs for the escape command
*/
#define SVGA_ESCAPE_NSID_VMWARE 0x00000000
#define SVGA_ESCAPE_NSID_DEVEL 0xFFFFFFFF
#define SVGA_ESCAPE_NSID_DEVEL 0xFFFFFFFF
#define SVGA_ESCAPE_VMWARE_MAJOR_MASK 0xFFFF0000
/*
* Within SVGA_ESCAPE_NSID_VMWARE, we multiplex commands according to
* the first DWORD of escape data (after the nsID and size). As a
* guideline we're using the high word and low word as a major and
* minor command number, respectively.
*
* Major command number allocation:
*
* 0000: Reserved
* 0001: SVGA_ESCAPE_VMWARE_LOG (svga_binary_logger.h)
* 0002: SVGA_ESCAPE_VMWARE_VIDEO (svga_overlay.h)
* 0003: SVGA_ESCAPE_VMWARE_HINT (svga_escape.h)
*/
#define SVGA_ESCAPE_VMWARE_HINT 0x00030000
#define SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN 0x00030001
#define SVGA_ESCAPE_VMWARE_MAJOR_MASK 0xFFFF0000
/*
* SVGA Hint commands.
*
* These escapes let the SVGA driver provide optional information to
* he host about the state of the guest or guest applications. The
* host can use these hints to make user interface or performance
* decisions.
*
* Notes:
*
* - SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN is deprecated for guests
* that use the SVGA Screen Object extension. Instead of sending
* this escape, use the SVGA_SCREEN_FULLSCREEN_HINT flag on your
* Screen Object.
*/
#define SVGA_ESCAPE_VMWARE_HINT 0x00030000
#define SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN 0x00030001 /* Deprecated */
typedef
struct {
uint32 command;
uint32 fullscreen;
struct {
int32 x, y;
} monitorPosition;
#pragma pack(push, 1)
typedef struct {
uint32 command;
uint32 fullscreen;
struct {
int32 x, y;
} monitorPosition;
} SVGAEscapeHintFullscreen;
#pragma pack(pop)
#endif /* _SVGA_ESCAPE_H_ */
#endif

199
drivers/gpu/drm/vmwgfx/device_include/svga_overlay.h
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@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
* Copyright 2007-2015 VMware, Inc.
* Copyright 2007-2021 VMware, Inc.
* SPDX-License-Identifier: GPL-2.0 OR MIT
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
@ -30,171 +30,88 @@
* Definitions for video-overlay support.
*/
#ifndef _SVGA_OVERLAY_H_
#define _SVGA_OVERLAY_H_
#include "svga_reg.h"
/*
* Video formats we support
*/
#if defined __cplusplus
extern "C" {
#endif
#define VMWARE_FOURCC_YV12 0x32315659 /* 'Y' 'V' '1' '2' */
#define VMWARE_FOURCC_YUY2 0x32595559 /* 'Y' 'U' 'Y' '2' */
#define VMWARE_FOURCC_UYVY 0x59565955 /* 'U' 'Y' 'V' 'Y' */
#define VMWARE_FOURCC_YV12 0x32315659
#define VMWARE_FOURCC_YUY2 0x32595559
#define VMWARE_FOURCC_UYVY 0x59565955
typedef enum {
SVGA_OVERLAY_FORMAT_INVALID = 0,
SVGA_OVERLAY_FORMAT_YV12 = VMWARE_FOURCC_YV12,
SVGA_OVERLAY_FORMAT_YUY2 = VMWARE_FOURCC_YUY2,
SVGA_OVERLAY_FORMAT_UYVY = VMWARE_FOURCC_UYVY,
SVGA_OVERLAY_FORMAT_INVALID = 0,
SVGA_OVERLAY_FORMAT_YV12 = VMWARE_FOURCC_YV12,
SVGA_OVERLAY_FORMAT_YUY2 = VMWARE_FOURCC_YUY2,
SVGA_OVERLAY_FORMAT_UYVY = VMWARE_FOURCC_UYVY,
} SVGAOverlayFormat;
#define SVGA_VIDEO_COLORKEY_MASK 0x00ffffff
#define SVGA_VIDEO_COLORKEY_MASK 0x00ffffff
#define SVGA_ESCAPE_VMWARE_VIDEO 0x00020000
#define SVGA_ESCAPE_VMWARE_VIDEO 0x00020000
#define SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS 0x00020001
/* FIFO escape layout:
* Type, Stream Id, (Register Id, Value) pairs */
#define SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS 0x00020001
#define SVGA_ESCAPE_VMWARE_VIDEO_FLUSH 0x00020002
/* FIFO escape layout:
* Type, Stream Id */
#define SVGA_ESCAPE_VMWARE_VIDEO_FLUSH 0x00020002
typedef
struct SVGAEscapeVideoSetRegs {
struct {
uint32 cmdType;
uint32 streamId;
} header;
typedef struct SVGAEscapeVideoSetRegs {
struct {
uint32 cmdType;
uint32 streamId;
} header;
/* May include zero or more items. */
struct {
uint32 registerId;
uint32 value;
} items[1];
struct {
uint32 registerId;
uint32 value;
} items[1];
} SVGAEscapeVideoSetRegs;
typedef
struct SVGAEscapeVideoFlush {
uint32 cmdType;
uint32 streamId;
typedef struct SVGAEscapeVideoFlush {
uint32 cmdType;
uint32 streamId;
} SVGAEscapeVideoFlush;
/*
* Struct definitions for the video overlay commands built on
* SVGAFifoCmdEscape.
*/
typedef
struct {
uint32 command;
uint32 overlay;
#pragma pack(push, 1)
typedef struct {
uint32 command;
uint32 overlay;
} SVGAFifoEscapeCmdVideoBase;
#pragma pack(pop)
typedef
struct {
SVGAFifoEscapeCmdVideoBase videoCmd;
#pragma pack(push, 1)
typedef struct {
SVGAFifoEscapeCmdVideoBase videoCmd;
} SVGAFifoEscapeCmdVideoFlush;
#pragma pack(pop)
typedef
struct {
SVGAFifoEscapeCmdVideoBase videoCmd;
struct {
uint32 regId;
uint32 value;
} items[1];
#pragma pack(push, 1)
typedef struct {
SVGAFifoEscapeCmdVideoBase videoCmd;
struct {
uint32 regId;
uint32 value;
} items[1];
} SVGAFifoEscapeCmdVideoSetRegs;
#pragma pack(pop)
typedef
struct {
SVGAFifoEscapeCmdVideoBase videoCmd;
struct {
uint32 regId;
uint32 value;
} items[SVGA_VIDEO_NUM_REGS];
#pragma pack(push, 1)
typedef struct {
SVGAFifoEscapeCmdVideoBase videoCmd;
struct {
uint32 regId;
uint32 value;
} items[SVGA_VIDEO_NUM_REGS];
} SVGAFifoEscapeCmdVideoSetAllRegs;
#pragma pack(pop)
/*
*----------------------------------------------------------------------
*
* VMwareVideoGetAttributes --
*
* Computes the size, pitches and offsets for YUV frames.
*
* Results:
* TRUE on success; otherwise FALSE on failure.
*
* Side effects:
* Pitches and offsets for the given YUV frame are put in 'pitches'
* and 'offsets' respectively. They are both optional though.
*
*----------------------------------------------------------------------
*/
static inline bool
VMwareVideoGetAttributes(const SVGAOverlayFormat format, /* IN */
uint32 *width, /* IN / OUT */
uint32 *height, /* IN / OUT */
uint32 *size, /* OUT */
uint32 *pitches, /* OUT (optional) */
uint32 *offsets) /* OUT (optional) */
{
int tmp;
*width = (*width + 1) & ~1;
if (offsets) {
offsets[0] = 0;
}
switch (format) {
case VMWARE_FOURCC_YV12:
*height = (*height + 1) & ~1;
*size = (*width) * (*height);
if (pitches) {
pitches[0] = *width;
}
if (offsets) {
offsets[1] = *size;
}
tmp = *width >> 1;
if (pitches) {
pitches[1] = pitches[2] = tmp;
}
tmp *= (*height >> 1);
*size += tmp;
if (offsets) {
offsets[2] = *size;
}
*size += tmp;
break;
case VMWARE_FOURCC_YUY2:
case VMWARE_FOURCC_UYVY:
*size = *width * 2;
if (pitches) {
pitches[0] = *size;
}
*size *= *height;
break;
default:
return false;
}
return true;
#if defined __cplusplus
}
#endif
#endif /* _SVGA_OVERLAY_H_ */
#endif

2715
drivers/gpu/drm/vmwgfx/device_include/svga_reg.h
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14
drivers/gpu/drm/vmwgfx/device_include/svga_types.h → drivers/gpu/drm/vmwgfx/device_include/vm_basic_types.h
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@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
* Copyright 2015 VMware, Inc.
* Copyright 2015-2021 VMware, Inc.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
@ -23,8 +23,9 @@
* SOFTWARE.
*
**********************************************************/
#ifndef _SVGA_TYPES_H_
#define _SVGA_TYPES_H_
#ifndef VM_BASIC_TYPES_H
#define VM_BASIC_TYPES_H
#include <linux/kernel.h>
#include <linux/mm.h>
#include <asm/page.h>
@ -50,6 +51,13 @@ typedef bool Bool;
#define CONST64U(x) x##ULL
#ifndef MBYTES_SHIFT
#define MBYTES_SHIFT 20
#endif
#ifndef MBYTES_2_BYTES
#define MBYTES_2_BYTES(_nbytes) ((uint64)(_nbytes) << MBYTES_SHIFT)
#endif
/*
* MKS Guest Stats types
*/

2
drivers/gpu/drm/vmwgfx/device_include/vmware_pack_begin.h
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@ -1,2 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <linux/compiler.h>

2
drivers/gpu/drm/vmwgfx/device_include/vmware_pack_end.h
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@ -1,2 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
__packed

539
drivers/gpu/drm/vmwgfx/vmw_surface_cache.h Normal file
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@ -0,0 +1,539 @@
/**********************************************************
* Copyright 2021 VMware, Inc.
* SPDX-License-Identifier: GPL-2.0 OR MIT
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
#ifndef VMW_SURFACE_CACHE_H
#define VMW_SURFACE_CACHE_H
#include "device_include/svga3d_surfacedefs.h"
#include <drm/vmwgfx_drm.h>
static inline u32 clamped_umul32(u32 a, u32 b)
{
uint64_t tmp = (uint64_t) a*b;
return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp;
}
/**
* vmw_surface_get_desc - Look up the appropriate SVGA3dSurfaceDesc for the
* given format.
*/
static inline const SVGA3dSurfaceDesc *
vmw_surface_get_desc(SVGA3dSurfaceFormat format)
{
if (format < ARRAY_SIZE(g_SVGA3dSurfaceDescs))
return &g_SVGA3dSurfaceDescs[format];
return &g_SVGA3dSurfaceDescs[SVGA3D_FORMAT_INVALID];
}
/**
* vmw_surface_get_mip_size - Given a base level size and the mip level,
* compute the size of the mip level.
*/
static inline struct drm_vmw_size
vmw_surface_get_mip_size(struct drm_vmw_size base_level, u32 mip_level)
{
struct drm_vmw_size size = {
.width = max_t(u32, base_level.width >> mip_level, 1),
.height = max_t(u32, base_level.height >> mip_level, 1),
.depth = max_t(u32, base_level.depth >> mip_level, 1)
};
return size;
}
static inline void
vmw_surface_get_size_in_blocks(const SVGA3dSurfaceDesc *desc,
const struct drm_vmw_size *pixel_size,
SVGA3dSize *block_size)
{
block_size->width = __KERNEL_DIV_ROUND_UP(pixel_size->width,
desc->blockSize.width);
block_size->height = __KERNEL_DIV_ROUND_UP(pixel_size->height,
desc->blockSize.height);
block_size->depth = __KERNEL_DIV_ROUND_UP(pixel_size->depth,
desc->blockSize.depth);
}
static inline bool
vmw_surface_is_planar_surface(const SVGA3dSurfaceDesc *desc)
{
return (desc->blockDesc & SVGA3DBLOCKDESC_PLANAR_YUV) != 0;
}
static inline u32
vmw_surface_calculate_pitch(const SVGA3dSurfaceDesc *desc,
const struct drm_vmw_size *size)
{
u32 pitch;
SVGA3dSize blocks;
vmw_surface_get_size_in_blocks(desc, size, &blocks);
pitch = blocks.width * desc->pitchBytesPerBlock;
return pitch;
}
/**
* vmw_surface_get_image_buffer_size - Calculates image buffer size.
*
* Return the number of bytes of buffer space required to store one image of a
* surface, optionally using the specified pitch.
*
* If pitch is zero, it is assumed that rows are tightly packed.
*
* This function is overflow-safe. If the result would have overflowed, instead
* we return MAX_UINT32.
*/
static inline u32
vmw_surface_get_image_buffer_size(const SVGA3dSurfaceDesc *desc,
const struct drm_vmw_size *size,
u32 pitch)
{
SVGA3dSize image_blocks;
u32 slice_size, total_size;
vmw_surface_get_size_in_blocks(desc, size, &image_blocks);
if (vmw_surface_is_planar_surface(desc)) {
total_size = clamped_umul32(image_blocks.width,
image_blocks.height);
total_size = clamped_umul32(total_size, image_blocks.depth);
total_size = clamped_umul32(total_size, desc->bytesPerBlock);
return total_size;
}
if (pitch == 0)
pitch = vmw_surface_calculate_pitch(desc, size);
slice_size = clamped_umul32(image_blocks.height, pitch);
total_size = clamped_umul32(slice_size, image_blocks.depth);
return total_size;
}
/**
* vmw_surface_get_serialized_size - Get the serialized size for the image.
*/
static inline u32
vmw_surface_get_serialized_size(SVGA3dSurfaceFormat format,
struct drm_vmw_size base_level_size,
u32 num_mip_levels,
u32 num_layers)
{
const SVGA3dSurfaceDesc *desc = vmw_surface_get_desc(format);
u32 total_size = 0;
u32 mip;
for (mip = 0; mip < num_mip_levels; mip++) {
struct drm_vmw_size size =
vmw_surface_get_mip_size(base_level_size, mip);
total_size += vmw_surface_get_image_buffer_size(desc,
&size, 0);
}
return total_size * num_layers;
}
/**
* vmw_surface_get_serialized_size_extended - Returns the number of bytes
* required for a surface with given parameters. Support for sample count.
*/
static inline u32
vmw_surface_get_serialized_size_extended(SVGA3dSurfaceFormat format,
struct drm_vmw_size base_level_size,
u32 num_mip_levels,
u32 num_layers,
u32 num_samples)
{
uint64_t total_size =
vmw_surface_get_serialized_size(format,
base_level_size,
num_mip_levels,
num_layers);
total_size *= max_t(u32, 1, num_samples);
return min_t(uint64_t, total_size, (uint64_t)U32_MAX);
}
/**
* vmw_surface_get_pixel_offset - Compute the offset (in bytes) to a pixel
* in an image (or volume).
*
* @width: The image width in pixels.
* @height: The image height in pixels
*/
static inline u32
vmw_surface_get_pixel_offset(SVGA3dSurfaceFormat format,
u32 width, u32 height,
u32 x, u32 y, u32 z)
{
const SVGA3dSurfaceDesc *desc = vmw_surface_get_desc(format);
const u32 bw = desc->blockSize.width, bh = desc->blockSize.height;
const u32 bd = desc->blockSize.depth;
const u32 rowstride = __KERNEL_DIV_ROUND_UP(width, bw) *
desc->bytesPerBlock;
const u32 imgstride = __KERNEL_DIV_ROUND_UP(height, bh) * rowstride;
const u32 offset = (z / bd * imgstride +
y / bh * rowstride +
x / bw * desc->bytesPerBlock);
return offset;
}
static inline u32
vmw_surface_get_image_offset(SVGA3dSurfaceFormat format,
struct drm_vmw_size baseLevelSize,
u32 numMipLevels,
u32 face,
u32 mip)
{
u32 offset;
u32 mipChainBytes;
u32 mipChainBytesToLevel;
u32 i;
const SVGA3dSurfaceDesc *desc;
struct drm_vmw_size mipSize;
u32 bytes;
desc = vmw_surface_get_desc(format);
mipChainBytes = 0;
mipChainBytesToLevel = 0;
for (i = 0; i < numMipLevels; i++) {
mipSize = vmw_surface_get_mip_size(baseLevelSize, i);
bytes = vmw_surface_get_image_buffer_size(desc, &mipSize, 0);
mipChainBytes += bytes;
if (i < mip)
mipChainBytesToLevel += bytes;
}
offset = mipChainBytes * face + mipChainBytesToLevel;
return offset;
}
/**
* vmw_surface_is_gb_screen_target_format - Is the specified format usable as
* a ScreenTarget?
* (with just the GBObjects cap-bit
* set)
* @format: format to queried
*
* RETURNS:
* true if queried format is valid for screen targets
*/
static inline bool
vmw_surface_is_gb_screen_target_format(SVGA3dSurfaceFormat format)
{
return (format == SVGA3D_X8R8G8B8 ||
format == SVGA3D_A8R8G8B8 ||
format == SVGA3D_R5G6B5 ||
format == SVGA3D_X1R5G5B5 ||
format == SVGA3D_A1R5G5B5 ||
format == SVGA3D_P8);
}
/**
* vmw_surface_is_dx_screen_target_format - Is the specified format usable as
* a ScreenTarget?
* (with DX10 enabled)
*
* @format: format to queried
*
* Results:
* true if queried format is valid for screen targets
*/
static inline bool
vmw_surface_is_dx_screen_target_format(SVGA3dSurfaceFormat format)
{
return (format == SVGA3D_R8G8B8A8_UNORM ||
format == SVGA3D_B8G8R8A8_UNORM ||
format == SVGA3D_B8G8R8X8_UNORM);
}
/**
* vmw_surface_is_screen_target_format - Is the specified format usable as a
* ScreenTarget?
* (for some combination of caps)
*
* @format: format to queried
*
* Results:
* true if queried format is valid for screen targets
*/
static inline bool
vmw_surface_is_screen_target_format(SVGA3dSurfaceFormat format)
{
if (vmw_surface_is_gb_screen_target_format(format)) {
return true;
}
return vmw_surface_is_dx_screen_target_format(format);
}
/**
* struct vmw_surface_mip - Mimpmap level information
* @bytes: Bytes required in the backing store of this mipmap level.
* @img_stride: Byte stride per image.
* @row_stride: Byte stride per block row.
* @size: The size of the mipmap.
*/
struct vmw_surface_mip {
size_t bytes;
size_t img_stride;
size_t row_stride;
struct drm_vmw_size size;
};
/**
* struct vmw_surface_cache - Cached surface information
* @desc: Pointer to the surface descriptor
* @mip: Array of mipmap level information. Valid size is @num_mip_levels.
* @mip_chain_bytes: Bytes required in the backing store for the whole chain
* of mip levels.
* @sheet_bytes: Bytes required in the backing store for a sheet
* representing a single sample.
* @num_mip_levels: Valid size of the @mip array. Number of mipmap levels in
* a chain.
* @num_layers: Number of slices in an array texture or number of faces in
* a cubemap texture.
*/
struct vmw_surface_cache {
const SVGA3dSurfaceDesc *desc;
struct vmw_surface_mip mip[DRM_VMW_MAX_MIP_LEVELS];
size_t mip_chain_bytes;
size_t sheet_bytes;
u32 num_mip_levels;
u32 num_layers;
};
/**
* struct vmw_surface_loc - Surface location
* @sheet: The multisample sheet.
* @sub_resource: Surface subresource. Defined as layer * num_mip_levels +
* mip_level.
* @x: X coordinate.
* @y: Y coordinate.
* @z: Z coordinate.
*/
struct vmw_surface_loc {
u32 sheet;
u32 sub_resource;
u32 x, y, z;
};
/**
* vmw_surface_subres - Compute the subresource from layer and mipmap.
* @cache: Surface layout data.
* @mip_level: The mipmap level.
* @layer: The surface layer (face or array slice).
*
* Return: The subresource.
*/
static inline u32 vmw_surface_subres(const struct vmw_surface_cache *cache,
u32 mip_level, u32 layer)
{
return cache->num_mip_levels * layer + mip_level;
}
/**
* vmw_surface_setup_cache - Build a surface cache entry
* @size: The surface base level dimensions.
* @format: The surface format.
* @num_mip_levels: Number of mipmap levels.
* @num_layers: Number of layers.
* @cache: Pointer to a struct vmw_surface_cach object to be filled in.
*
* Return: Zero on success, -EINVAL on invalid surface layout.
*/
static inline int vmw_surface_setup_cache(const struct drm_vmw_size *size,
SVGA3dSurfaceFormat format,
u32 num_mip_levels,
u32 num_layers,
u32 num_samples,
struct vmw_surface_cache *cache)
{
const SVGA3dSurfaceDesc *desc;
u32 i;
memset(cache, 0, sizeof(*cache));
cache->desc = desc = vmw_surface_get_desc(format);
cache->num_mip_levels = num_mip_levels;
cache->num_layers = num_layers;
for (i = 0; i < cache->num_mip_levels; i++) {
struct vmw_surface_mip *mip = &cache->mip[i];
mip->size = vmw_surface_get_mip_size(*size, i);
mip->bytes = vmw_surface_get_image_buffer_size
(desc, &mip->size, 0);
mip->row_stride =
__KERNEL_DIV_ROUND_UP(mip->size.width,
desc->blockSize.width) *
desc->bytesPerBlock * num_samples;
if (!mip->row_stride)
goto invalid_dim;
mip->img_stride =
__KERNEL_DIV_ROUND_UP(mip->size.height,
desc->blockSize.height) *
mip->row_stride;
if (!mip->img_stride)
goto invalid_dim;
cache->mip_chain_bytes += mip->bytes;
}
cache->sheet_bytes = cache->mip_chain_bytes * num_layers;
if (!cache->sheet_bytes)
goto invalid_dim;
return 0;
invalid_dim:
VMW_DEBUG_USER("Invalid surface layout for dirty tracking.\n");
return -EINVAL;
}
/**
* vmw_surface_get_loc - Get a surface location from an offset into the
* backing store
* @cache: Surface layout data.
* @loc: Pointer to a struct vmw_surface_loc to be filled in.
* @offset: Offset into the surface backing store.
*/
static inline void
vmw_surface_get_loc(const struct vmw_surface_cache *cache,
struct vmw_surface_loc *loc,
size_t offset)
{
const struct vmw_surface_mip *mip = &cache->mip[0];
const SVGA3dSurfaceDesc *desc = cache->desc;
u32 layer;
int i;
loc->sheet = offset / cache->sheet_bytes;
offset -= loc->sheet * cache->sheet_bytes;
layer = offset / cache->mip_chain_bytes;
offset -= layer * cache->mip_chain_bytes;
for (i = 0; i < cache->num_mip_levels; ++i, ++mip) {
if (mip->bytes > offset)
break;
offset -= mip->bytes;
}
loc->sub_resource = vmw_surface_subres(cache, i, layer);
loc->z = offset / mip->img_stride;
offset -= loc->z * mip->img_stride;
loc->z *= desc->blockSize.depth;
loc->y = offset / mip->row_stride;
offset -= loc->y * mip->row_stride;
loc->y *= desc->blockSize.height;
loc->x = offset / desc->bytesPerBlock;
loc->x *= desc->blockSize.width;
}
/**
* vmw_surface_inc_loc - Clamp increment a surface location with one block
* size
* in each dimension.
* @loc: Pointer to a struct vmw_surface_loc to be incremented.
*
* When computing the size of a range as size = end - start, the range does not
* include the end element. However a location representing the last byte
* of a touched region in the backing store *is* included in the range.
* This function modifies such a location to match the end definition
* given as start + size which is the one used in a SVGA3dBox.
*/
static inline void
vmw_surface_inc_loc(const struct vmw_surface_cache *cache,
struct vmw_surface_loc *loc)
{
const SVGA3dSurfaceDesc *desc = cache->desc;
u32 mip = loc->sub_resource % cache->num_mip_levels;
const struct drm_vmw_size *size = &cache->mip[mip].size;
loc->sub_resource++;
loc->x += desc->blockSize.width;
if (loc->x > size->width)
loc->x = size->width;
loc->y += desc->blockSize.height;
if (loc->y > size->height)
loc->y = size->height;
loc->z += desc->blockSize.depth;
if (loc->z > size->depth)
loc->z = size->depth;
}
/**
* vmw_surface_min_loc - The start location in a subresource
* @cache: Surface layout data.
* @sub_resource: The subresource.
* @loc: Pointer to a struct vmw_surface_loc to be filled in.
*/
static inline void
vmw_surface_min_loc(const struct vmw_surface_cache *cache,
u32 sub_resource,
struct vmw_surface_loc *loc)
{
loc->sheet = 0;
loc->sub_resource = sub_resource;
loc->x = loc->y = loc->z = 0;
}
/**
* vmw_surface_min_loc - The end location in a subresource
* @cache: Surface layout data.
* @sub_resource: The subresource.
* @loc: Pointer to a struct vmw_surface_loc to be filled in.
*
* Following the end definition given in vmw_surface_inc_loc(),
* Compute the end location of a surface subresource.
*/
static inline void
vmw_surface_max_loc(const struct vmw_surface_cache *cache,
u32 sub_resource,
struct vmw_surface_loc *loc)
{
const struct drm_vmw_size *size;
u32 mip;
loc->sheet = 0;
loc->sub_resource = sub_resource + 1;
mip = sub_resource % cache->num_mip_levels;
size = &cache->mip[mip].size;
loc->x = size->width;
loc->y = size->height;
loc->z = size->depth;
}
#endif /* VMW_SURFACE_CACHE_H */

4
drivers/gpu/drm/vmwgfx/vmwgfx_binding.c
View File

@ -844,7 +844,7 @@ static int vmw_emit_set_rt(struct vmw_ctx_binding_state *cbs)
size_t cmd_size, view_id_size;
const struct vmw_resource *ctx = vmw_cbs_context(cbs);
vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS);
vmw_collect_view_ids(cbs, loc, SVGA3D_DX_MAX_RENDER_TARGETS);
view_id_size = cbs->bind_cmd_count*sizeof(uint32);
cmd_size = sizeof(*cmd) + view_id_size;
cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
@ -1440,7 +1440,7 @@ u32 vmw_binding_dirtying(enum vmw_ctx_binding_type binding_type)
static void vmw_binding_build_asserts(void)
{
BUILD_BUG_ON(SVGA3D_NUM_SHADERTYPE_DX10 != 3);
BUILD_BUG_ON(SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS > SVGA3D_RT_MAX);
BUILD_BUG_ON(SVGA3D_DX_MAX_RENDER_TARGETS > SVGA3D_RT_MAX);
BUILD_BUG_ON(sizeof(uint32) != sizeof(u32));
/*

4
drivers/gpu/drm/vmwgfx/vmwgfx_context.c
View File

@ -185,7 +185,7 @@ static int vmw_gb_context_init(struct vmw_private *dev_priv,
container_of(res, struct vmw_user_context, res);
res->backup_size = (dx ? sizeof(SVGADXContextMobFormat) :
SVGA3D_CONTEXT_DATA_SIZE);
sizeof(SVGAGBContextData));
ret = vmw_resource_init(dev_priv, res, true,
res_free,
dx ? &vmw_dx_context_func :
@ -259,7 +259,7 @@ static int vmw_context_init(struct vmw_private *dev_priv,
goto out_early;
}
if (unlikely(res->id >= SVGA3D_MAX_CONTEXT_IDS)) {
if (unlikely(res->id >= SVGA3D_HB_MAX_CONTEXT_IDS)) {
DRM_ERROR("Out of hw context ids.\n");
vmw_resource_unreference(&res);
return -ENOMEM;

10
drivers/gpu/drm/vmwgfx/vmwgfx_devcaps.c
View File

@ -31,8 +31,8 @@
struct svga_3d_compat_cap {
SVGA3dCapsRecordHeader header;
SVGA3dCapPair pairs[SVGA3D_DEVCAP_MAX];
SVGA3dFifoCapsRecordHeader header;
SVGA3dFifoCapPair pairs[SVGA3D_DEVCAP_MAX];
};
@ -64,14 +64,14 @@ static int vmw_fill_compat_cap(struct vmw_private *dev_priv, void *bounce,
if (size < pair_offset)
return -EINVAL;
max_size = (size - pair_offset) / sizeof(SVGA3dCapPair);
max_size = (size - pair_offset) / sizeof(SVGA3dFifoCapPair);
if (max_size > SVGA3D_DEVCAP_MAX)
max_size = SVGA3D_DEVCAP_MAX;
compat_cap->header.length =
(pair_offset + max_size * sizeof(SVGA3dCapPair)) / sizeof(u32);
compat_cap->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
(pair_offset + max_size * sizeof(SVGA3dFifoCapPair)) / sizeof(u32);
compat_cap->header.type = SVGA3D_FIFO_CAPS_RECORD_DEVCAPS;
for (i = 0; i < max_size; ++i) {
compat_cap->pairs[i][0] = i;

2
drivers/gpu/drm/vmwgfx/vmwgfx_devcaps.h
View File

@ -30,7 +30,7 @@
#include "vmwgfx_drv.h"
#include "device_include/svga3d_caps.h"
#include "device_include/svga_reg.h"
int vmw_devcaps_create(struct vmw_private *vmw);
void vmw_devcaps_destroy(struct vmw_private *vmw);

9
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
View File

@ -891,9 +891,8 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
mem_size *= 3;
dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
dev_priv->prim_bb_mem =
vmw_read(dev_priv,
SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
dev_priv->max_primary_mem =
vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM);
dev_priv->max_mob_size =
vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
dev_priv->stdu_max_width =
@ -912,7 +911,7 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
} else {
dev_priv->texture_max_width = 8192;
dev_priv->texture_max_height = 8192;
dev_priv->prim_bb_mem = dev_priv->vram_size;
dev_priv->max_primary_mem = dev_priv->vram_size;
}
vmw_print_capabilities(dev_priv->capabilities);
@ -936,7 +935,7 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
(unsigned)dev_priv->memory_size / 1024);
}
DRM_INFO("Maximum display memory size is %llu kiB\n",
(uint64_t)dev_priv->prim_bb_mem / 1024);
(uint64_t)dev_priv->max_primary_mem / 1024);
/* Need mmio memory to check for fifo pitchlock cap. */
if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&

2
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
View File

@ -491,7 +491,7 @@ struct vmw_private {
resource_size_t io_start;
resource_size_t vram_start;
resource_size_t vram_size;
resource_size_t prim_bb_mem;
resource_size_t max_primary_mem;
void __iomem *rmmio;
u32 *fifo_mem;
resource_size_t fifo_mem_size;

2
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
View File

@ -2365,7 +2365,7 @@ static int vmw_cmd_dx_set_rendertargets(struct vmw_private *dev_priv,
sizeof(SVGA3dRenderTargetViewId);
int ret;
if (num_rt_view > SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS) {
if (num_rt_view > SVGA3D_DX_MAX_RENDER_TARGETS) {
VMW_DEBUG_USER("Invalid DX Rendertarget binding.\n");
return -EINVAL;
}

2
drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
View File

@ -58,7 +58,7 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data,
param->value = vmw_fifo_caps(dev_priv);
break;
case DRM_VMW_PARAM_MAX_FB_SIZE:
param->value = dev_priv->prim_bb_mem;
param->value = dev_priv->max_primary_mem;
break;
case DRM_VMW_PARAM_FIFO_HW_VERSION:
{

6
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
View File

@ -1487,7 +1487,7 @@ static int vmw_kms_check_display_memory(struct drm_device *dev,
* SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM is not present vram size is
* limit on primary bounding box
*/
if (pixel_mem > dev_priv->prim_bb_mem) {
if (pixel_mem > dev_priv->max_primary_mem) {
VMW_DEBUG_KMS("Combined output size too large.\n");
return -EINVAL;
}
@ -1497,7 +1497,7 @@ static int vmw_kms_check_display_memory(struct drm_device *dev,
!(dev_priv->capabilities & SVGA_CAP_NO_BB_RESTRICTION)) {
bb_mem = (u64) bounding_box.x2 * bounding_box.y2 * 4;
if (bb_mem > dev_priv->prim_bb_mem) {
if (bb_mem > dev_priv->max_primary_mem) {
VMW_DEBUG_KMS("Topology is beyond supported limits.\n");
return -EINVAL;
}
@ -1897,7 +1897,7 @@ bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
{
return ((u64) pitch * (u64) height) < (u64)
((dev_priv->active_display_unit == vmw_du_screen_target) ?
dev_priv->prim_bb_mem : dev_priv->vram_size);
dev_priv->max_primary_mem : dev_priv->vram_size);
}

36
drivers/gpu/drm/vmwgfx/vmwgfx_mob.c
View File

@ -37,14 +37,14 @@
#ifdef CONFIG_64BIT
#define VMW_PPN_SIZE 8
#define VMW_MOBFMT_PTDEPTH_0 SVGA3D_MOBFMT_PTDEPTH64_0
#define VMW_MOBFMT_PTDEPTH_1 SVGA3D_MOBFMT_PTDEPTH64_1
#define VMW_MOBFMT_PTDEPTH_2 SVGA3D_MOBFMT_PTDEPTH64_2
#define VMW_MOBFMT_PTDEPTH_0 SVGA3D_MOBFMT_PT64_0
#define VMW_MOBFMT_PTDEPTH_1 SVGA3D_MOBFMT_PT64_1
#define VMW_MOBFMT_PTDEPTH_2 SVGA3D_MOBFMT_PT64_2
#else
#define VMW_PPN_SIZE 4
#define VMW_MOBFMT_PTDEPTH_0 SVGA3D_MOBFMT_PTDEPTH_0
#define VMW_MOBFMT_PTDEPTH_1 SVGA3D_MOBFMT_PTDEPTH_1
#define VMW_MOBFMT_PTDEPTH_2 SVGA3D_MOBFMT_PTDEPTH_2
#define VMW_MOBFMT_PTDEPTH_0 SVGA3D_MOBFMT_PT_0
#define VMW_MOBFMT_PTDEPTH_1 SVGA3D_MOBFMT_PT_1
#define VMW_MOBFMT_PTDEPTH_2 SVGA3D_MOBFMT_PT_2
#endif
/*
@ -70,20 +70,20 @@ struct vmw_mob {
* @page_table: Pointer to a struct vmw_mob holding the page table.
*/
static const struct vmw_otable pre_dx_tables[] = {
{VMWGFX_NUM_MOB * SVGA3D_OTABLE_MOB_ENTRY_SIZE, NULL, true},
{VMWGFX_NUM_GB_SURFACE * SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, NULL, true},
{VMWGFX_NUM_GB_CONTEXT * SVGA3D_OTABLE_CONTEXT_ENTRY_SIZE, NULL, true},
{VMWGFX_NUM_GB_SHADER * SVGA3D_OTABLE_SHADER_ENTRY_SIZE, NULL, true},
{VMWGFX_NUM_GB_SCREEN_TARGET * SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE,
{VMWGFX_NUM_MOB * sizeof(SVGAOTableMobEntry), NULL, true},
{VMWGFX_NUM_GB_SURFACE * sizeof(SVGAOTableSurfaceEntry), NULL, true},
{VMWGFX_NUM_GB_CONTEXT * sizeof(SVGAOTableContextEntry), NULL, true},
{VMWGFX_NUM_GB_SHADER * sizeof(SVGAOTableShaderEntry), NULL, true},
{VMWGFX_NUM_GB_SCREEN_TARGET * sizeof(SVGAOTableScreenTargetEntry),
NULL, VMWGFX_ENABLE_SCREEN_TARGET_OTABLE}
};
static const struct vmw_otable dx_tables[] = {
{VMWGFX_NUM_MOB * SVGA3D_OTABLE_MOB_ENTRY_SIZE, NULL, true},
{VMWGFX_NUM_GB_SURFACE * SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, NULL, true},
{VMWGFX_NUM_GB_CONTEXT * SVGA3D_OTABLE_CONTEXT_ENTRY_SIZE, NULL, true},
{VMWGFX_NUM_GB_SHADER * SVGA3D_OTABLE_SHADER_ENTRY_SIZE, NULL, true},
{VMWGFX_NUM_GB_SCREEN_TARGET * SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE,
{VMWGFX_NUM_MOB * sizeof(SVGAOTableMobEntry), NULL, true},
{VMWGFX_NUM_GB_SURFACE * sizeof(SVGAOTableSurfaceEntry), NULL, true},
{VMWGFX_NUM_GB_CONTEXT * sizeof(SVGAOTableContextEntry), NULL, true},
{VMWGFX_NUM_GB_SHADER * sizeof(SVGAOTableShaderEntry), NULL, true},
{VMWGFX_NUM_GB_SCREEN_TARGET * sizeof(SVGAOTableScreenTargetEntry),
NULL, VMWGFX_ENABLE_SCREEN_TARGET_OTABLE},
{VMWGFX_NUM_DXCONTEXT * sizeof(SVGAOTableDXContextEntry), NULL, true},
};
@ -155,7 +155,7 @@ static int vmw_setup_otable_base(struct vmw_private *dev_priv,
goto out_no_populate;
vmw_mob_pt_setup(mob, iter, otable->size >> PAGE_SHIFT);
mob->pt_level += VMW_MOBFMT_PTDEPTH_1 - SVGA3D_MOBFMT_PTDEPTH_1;
mob->pt_level += VMW_MOBFMT_PTDEPTH_1 - SVGA3D_MOBFMT_PT_1;
}
cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
@ -636,7 +636,7 @@ int vmw_mob_bind(struct vmw_private *dev_priv,
vmw_mob_pt_setup(mob, data_iter, num_data_pages);
pt_set_up = true;
mob->pt_level += VMW_MOBFMT_PTDEPTH_1 - SVGA3D_MOBFMT_PTDEPTH_1;
mob->pt_level += VMW_MOBFMT_PTDEPTH_1 - SVGA3D_MOBFMT_PT_1;
}
vmw_fifo_resource_inc(dev_priv);

2
drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
View File

@ -33,7 +33,7 @@
#include <drm/drm_vblank.h>
#include "vmwgfx_kms.h"
#include "device_include/svga3d_surfacedefs.h"
#include "vmw_surface_cache.h"
#define vmw_crtc_to_stdu(x) \
container_of(x, struct vmw_screen_target_display_unit, base.crtc)

75
drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
View File

@ -31,6 +31,7 @@
#include "vmwgfx_resource_priv.h"
#include "vmwgfx_so.h"
#include "vmwgfx_binding.h"
#include "vmw_surface_cache.h"
#include "device_include/svga3d_surfacedefs.h"
#define SVGA3D_FLAGS_64(upper32, lower32) (((uint64_t)upper32 << 32) | lower32)
@ -78,7 +79,7 @@ struct vmw_surface_offset {
* @boxes: Array of SVGA3dBoxes indicating dirty regions. One per subresource.
*/
struct vmw_surface_dirty {
struct svga3dsurface_cache cache;
struct vmw_surface_cache cache;
size_t size;
u32 num_subres;
SVGA3dBox boxes[];
@ -307,8 +308,8 @@ static void vmw_surface_dma_encode(struct vmw_surface *srf,
{
uint32_t i;
struct vmw_surface_dma *cmd = (struct vmw_surface_dma *)cmd_space;
const struct svga3d_surface_desc *desc =
svga3dsurface_get_desc(srf->metadata.format);
const struct SVGA3dSurfaceDesc *desc =
vmw_surface_get_desc(srf->metadata.format);
for (i = 0; i < srf->metadata.num_sizes; ++i) {
SVGA3dCmdHeader *header = &cmd->header;
@ -323,8 +324,7 @@ static void vmw_surface_dma_encode(struct vmw_surface *srf,
body->guest.ptr = *ptr;
body->guest.ptr.offset += cur_offset->bo_offset;
body->guest.pitch = svga3dsurface_calculate_pitch(desc,
cur_size);
body->guest.pitch = vmw_surface_calculate_pitch(desc, cur_size);
body->host.sid = srf->res.id;
body->host.face = cur_offset->face;
body->host.mipmap = cur_offset->mip;
@ -342,7 +342,7 @@ static void vmw_surface_dma_encode(struct vmw_surface *srf,
suffix->suffixSize = sizeof(*suffix);
suffix->maximumOffset =
svga3dsurface_get_image_buffer_size(desc, cur_size,
vmw_surface_get_image_buffer_size(desc, cur_size,
body->guest.pitch);
suffix->flags.discard = 0;
suffix->flags.unsynchronized = 0;
@ -432,7 +432,7 @@ static int vmw_legacy_srf_create(struct vmw_resource *res)
goto out_no_id;
}
if (unlikely(res->id >= SVGA3D_MAX_SURFACE_IDS)) {
if (unlikely(res->id >= SVGA3D_HB_MAX_SURFACE_IDS)) {
ret = -EBUSY;
goto out_no_fifo;
}
@ -751,7 +751,7 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
struct vmw_surface_offset *cur_offset;
uint32_t num_sizes;
uint32_t size;
const struct svga3d_surface_desc *desc;
const SVGA3dSurfaceDesc *desc;
if (unlikely(vmw_user_surface_size == 0))
vmw_user_surface_size = ttm_round_pot(sizeof(*user_srf)) +
@ -772,8 +772,8 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
ttm_round_pot(num_sizes * sizeof(struct drm_vmw_size)) +
ttm_round_pot(num_sizes * sizeof(struct vmw_surface_offset));
desc = svga3dsurface_get_desc(req->format);
if (unlikely(desc->block_desc == SVGA3DBLOCKDESC_NONE)) {
desc = vmw_surface_get_desc(req->format);
if (unlikely(desc->blockDesc == SVGA3DBLOCKDESC_NONE)) {
VMW_DEBUG_USER("Invalid format %d for surface creation.\n",
req->format);
return -EINVAL;
@ -833,13 +833,13 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
for (i = 0; i < DRM_VMW_MAX_SURFACE_FACES; ++i) {
for (j = 0; j < metadata->mip_levels[i]; ++j) {
uint32_t stride = svga3dsurface_calculate_pitch
(desc, cur_size);
uint32_t stride = vmw_surface_calculate_pitch(
desc, cur_size);
cur_offset->face = i;
cur_offset->mip = j;
cur_offset->bo_offset = cur_bo_offset;
cur_bo_offset += svga3dsurface_get_image_buffer_size
cur_bo_offset += vmw_surface_get_image_buffer_size
(desc, cur_size, stride);
++cur_offset;
++cur_size;
@ -1711,10 +1711,10 @@ out_bad_resource:
* than partial z slices are dirtied.
*/
static void vmw_subres_dirty_add(struct vmw_surface_dirty *dirty,
const struct svga3dsurface_loc *loc_start,
const struct svga3dsurface_loc *loc_end)
const struct vmw_surface_loc *loc_start,
const struct vmw_surface_loc *loc_end)
{
const struct svga3dsurface_cache *cache = &dirty->cache;
const struct vmw_surface_cache *cache = &dirty->cache;
SVGA3dBox *box = &dirty->boxes[loc_start->sub_resource];
u32 mip = loc_start->sub_resource % cache->num_mip_levels;
const struct drm_vmw_size *size = &cache->mip[mip].size;
@ -1760,7 +1760,7 @@ static void vmw_subres_dirty_add(struct vmw_surface_dirty *dirty,
*/
static void vmw_subres_dirty_full(struct vmw_surface_dirty *dirty, u32 subres)
{
const struct svga3dsurface_cache *cache = &dirty->cache;
const struct vmw_surface_cache *cache = &dirty->cache;
u32 mip = subres % cache->num_mip_levels;
const struct drm_vmw_size *size = &cache->mip[mip].size;
SVGA3dBox *box = &dirty->boxes[subres];
@ -1783,15 +1783,15 @@ static void vmw_surface_tex_dirty_range_add(struct vmw_resource *res,
struct vmw_surface_dirty *dirty =
(struct vmw_surface_dirty *) res->dirty;
size_t backup_end = res->backup_offset + res->backup_size;
struct svga3dsurface_loc loc1, loc2;
const struct svga3dsurface_cache *cache;
struct vmw_surface_loc loc1, loc2;
const struct vmw_surface_cache *cache;
start = max_t(size_t, start, res->backup_offset) - res->backup_offset;
end = min(end, backup_end) - res->backup_offset;
cache = &dirty->cache;
svga3dsurface_get_loc(cache, &loc1, start);
svga3dsurface_get_loc(cache, &loc2, end - 1);
svga3dsurface_inc_loc(cache, &loc2);
vmw_surface_get_loc(cache, &loc1, start);
vmw_surface_get_loc(cache, &loc2, end - 1);
vmw_surface_inc_loc(cache, &loc2);
if (loc1.sheet != loc2.sheet) {
u32 sub_res;
@ -1811,12 +1811,12 @@ static void vmw_surface_tex_dirty_range_add(struct vmw_resource *res,
vmw_subres_dirty_add(dirty, &loc1, &loc2);
} else {
/* Dirty range covers multiple sub-resources */
struct svga3dsurface_loc loc_min, loc_max;
struct vmw_surface_loc loc_min, loc_max;
u32 sub_res;
svga3dsurface_max_loc(cache, loc1.sub_resource, &loc_max);
vmw_surface_max_loc(cache, loc1.sub_resource, &loc_max);
vmw_subres_dirty_add(dirty, &loc1, &loc_max);
svga3dsurface_min_loc(cache, loc2.sub_resource - 1, &loc_min);
vmw_surface_min_loc(cache, loc2.sub_resource - 1, &loc_min);
vmw_subres_dirty_add(dirty, &loc_min, &loc2);
for (sub_res = loc1.sub_resource + 1;
sub_res < loc2.sub_resource - 1; ++sub_res)
@ -1833,7 +1833,7 @@ static void vmw_surface_buf_dirty_range_add(struct vmw_resource *res,
{
struct vmw_surface_dirty *dirty =
(struct vmw_surface_dirty *) res->dirty;
const struct svga3dsurface_cache *cache = &dirty->cache;
const struct vmw_surface_cache *cache = &dirty->cache;
size_t backup_end = res->backup_offset + cache->mip_chain_bytes;
SVGA3dBox *box = &dirty->boxes[0];
u32 box_c2;
@ -1876,7 +1876,7 @@ static int vmw_surface_dirty_sync(struct vmw_resource *res)
struct vmw_surface_dirty *dirty =
(struct vmw_surface_dirty *) res->dirty;
size_t alloc_size;
const struct svga3dsurface_cache *cache = &dirty->cache;
const struct vmw_surface_cache *cache = &dirty->cache;
struct {
SVGA3dCmdHeader header;
SVGA3dCmdDXUpdateSubResource body;
@ -1989,7 +1989,7 @@ static int vmw_surface_dirty_alloc(struct vmw_resource *res)
}
num_samples = max_t(u32, 1, metadata->multisample_count);
ret = svga3dsurface_setup_cache(&metadata->base_size, metadata->format,
ret = vmw_surface_setup_cache(&metadata->base_size, metadata->format,
num_mip, num_layers, num_samples,
&dirty->cache);
if (ret)
@ -2080,7 +2080,7 @@ int vmw_gb_surface_define(struct vmw_private *dev_priv,
*srf_out = NULL;
if (req->scanout) {
if (!svga3dsurface_is_screen_target_format(req->format)) {
if (!vmw_surface_is_screen_target_format(req->format)) {
VMW_DEBUG_USER("Invalid Screen Target surface format.");
return -EINVAL;
}
@ -2095,10 +2095,10 @@ int vmw_gb_surface_define(struct vmw_private *dev_priv,
return -EINVAL;
}
} else {
const struct svga3d_surface_desc *desc =
svga3dsurface_get_desc(req->format);
const SVGA3dSurfaceDesc *desc =
vmw_surface_get_desc(req->format);
if (desc->block_desc == SVGA3DBLOCKDESC_NONE) {
if (desc->blockDesc == SVGA3DBLOCKDESC_NONE) {
VMW_DEBUG_USER("Invalid surface format.\n");
return -EINVAL;
}
@ -2147,11 +2147,12 @@ int vmw_gb_surface_define(struct vmw_private *dev_priv,
sample_count = metadata->multisample_count;
srf->res.backup_size =
svga3dsurface_get_serialized_size_extended(metadata->format,
metadata->base_size,
metadata->mip_levels[0],
num_layers,
sample_count);
vmw_surface_get_serialized_size_extended(
metadata->format,
metadata->base_size,
metadata->mip_levels[0],
num_layers,
sample_count);
if (metadata->flags & SVGA3D_SURFACE_BIND_STREAM_OUTPUT)
srf->res.backup_size += sizeof(SVGA3dDXSOState);