KVM: selftests: Verify APIC_ID is set when forcing x2APIC=>xAPIC transition
Add a sub-test to verify that KVM stuffs the APIC_ID when userspace forces a transition from x2APIC to xAPIC without first disabling the APIC. Such a transition is architecturally disallowed (WRMSR will #GP), but needs to be handled by KVM to allow userspace to emulate RESET (ignoring that userspace should also stuff local APIC state on RESET). Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Link: https://lore.kernel.org/r/20230109130605.2013555-3-eesposit@redhat.com Co-developed-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Sean Christopherson <seanjc@google.com>
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@ -132,6 +132,59 @@ static void test_icr(struct xapic_vcpu *x)
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__test_icr(x, -1ull & ~APIC_DM_FIXED_MASK);
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}
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static void __test_apic_id(struct kvm_vcpu *vcpu, uint64_t apic_base)
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{
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uint32_t apic_id, expected;
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struct kvm_lapic_state xapic;
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vcpu_set_msr(vcpu, MSR_IA32_APICBASE, apic_base);
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vcpu_ioctl(vcpu, KVM_GET_LAPIC, &xapic);
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expected = apic_base & X2APIC_ENABLE ? vcpu->id : vcpu->id << 24;
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apic_id = *((u32 *)&xapic.regs[APIC_ID]);
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TEST_ASSERT(apic_id == expected,
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"APIC_ID not set back to %s format; wanted = %x, got = %x",
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(apic_base & X2APIC_ENABLE) ? "x2APIC" : "xAPIC",
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expected, apic_id);
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}
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/*
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* Verify that KVM switches the APIC_ID between xAPIC and x2APIC when userspace
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* stuffs MSR_IA32_APICBASE. Setting the APIC_ID when x2APIC is enabled and
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* when the APIC transitions for DISABLED to ENABLED is architectural behavior
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* (on Intel), whereas the x2APIC => xAPIC transition behavior is KVM ABI since
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* attempted to transition from x2APIC to xAPIC without disabling the APIC is
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* architecturally disallowed.
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*/
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static void test_apic_id(void)
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{
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const uint32_t NR_VCPUS = 3;
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struct kvm_vcpu *vcpus[NR_VCPUS];
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uint64_t apic_base;
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struct kvm_vm *vm;
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int i;
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vm = vm_create_with_vcpus(NR_VCPUS, NULL, vcpus);
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vm_enable_cap(vm, KVM_CAP_X2APIC_API, KVM_X2APIC_API_USE_32BIT_IDS);
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for (i = 0; i < NR_VCPUS; i++) {
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apic_base = vcpu_get_msr(vcpus[i], MSR_IA32_APICBASE);
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TEST_ASSERT(apic_base & MSR_IA32_APICBASE_ENABLE,
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"APIC not in ENABLED state at vCPU RESET");
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TEST_ASSERT(!(apic_base & X2APIC_ENABLE),
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"APIC not in xAPIC mode at vCPU RESET");
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__test_apic_id(vcpus[i], apic_base);
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__test_apic_id(vcpus[i], apic_base | X2APIC_ENABLE);
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__test_apic_id(vcpus[i], apic_base);
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}
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kvm_vm_free(vm);
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}
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int main(int argc, char *argv[])
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{
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struct xapic_vcpu x = {
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@ -157,4 +210,6 @@ int main(int argc, char *argv[])
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virt_pg_map(vm, APIC_DEFAULT_GPA, APIC_DEFAULT_GPA);
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test_icr(&x);
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kvm_vm_free(vm);
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test_apic_id();
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}
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