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drm/i915/xehpsdv: Add maximum sseu limits 

Due to the removal of legacy slices and the transition to a
gslice/cslice/mslice/etc. design, we'll internally store all DSS under
"slice0."

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Caz Yokoyama <caz.yokoyama@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210729170008.2836648-10-matthew.d.roper@intel.com
This commit is contained in:
Matt Roper 2021-07-29 09:59:59 -07:00
parent 05b78d291d
commit eb962fae00
3 changed files with 6 additions and 3 deletions
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5
drivers/gpu/drm/i915/gt/intel_sseu.c
View File

@ -145,7 +145,10 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
* across the entire device. Then calculate out the DSS for each
* workload type within that software slice.
*/
intel_sseu_set_info(sseu, 1, 6, 16);
if (IS_XEHPSDV(gt->i915))
intel_sseu_set_info(sseu, 1, 32, 16);
else
intel_sseu_set_info(sseu, 1, 6, 16);
/*
* As mentioned above, Xe_HP does not have the concept of a slice.

2
drivers/gpu/drm/i915/gt/intel_sseu.h
View File

@ -16,7 +16,7 @@ struct intel_gt;
struct drm_printer;
#define GEN_MAX_SLICES (3) /* SKL upper bound */
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
#define GEN_MAX_SUBSLICES (32) /* XEHPSDV upper bound */
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
#define GEN_MAX_EUS (16) /* TGL upper bound */

2
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
View File

@ -53,7 +53,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
static void gen11_sseu_device_status(struct intel_gt *gt,
struct sseu_dev_info *sseu)
{
#define SS_MAX 6
#define SS_MAX 8
struct intel_uncore *uncore = gt->uncore;
const struct intel_gt_info *info = &gt->info;
u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];