RDMA/i40iw: Use core helpers to get aligned DMA address within a supported page size
Call the core helpers to retrieve the HW aligned address to use for the
MR, within a supported i40iw page size.
Remove code in i40iw to determine when MR is backed by 2M huge pages which
involves checking the umem->hugetlb flag and VMA inspection. The new DMA
iterator will return the 2M aligned address if the MR is backed by 2M
pages.
Fixes: f26c7c8339
("i40iw: Add 2MB page support")
Reviewed-by: Michael J. Ruhl <michael.j.ruhl@intel.com>
Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com>
Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
This commit is contained in:
parent
a808273a49
commit
eb52c0333f
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@ -1338,52 +1338,21 @@ static void i40iw_copy_user_pgaddrs(struct i40iw_mr *iwmr,
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struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
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struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
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struct i40iw_pble_info *pinfo;
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struct sg_dma_page_iter sg_iter;
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u64 pg_addr = 0;
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struct ib_block_iter biter;
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u32 idx = 0;
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bool first_pg = true;
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pinfo = (level == I40IW_LEVEL_1) ? NULL : palloc->level2.leaf;
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if (iwmr->type == IW_MEMREG_TYPE_QP)
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iwpbl->qp_mr.sq_page = sg_page(region->sg_head.sgl);
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for_each_sg_dma_page (region->sg_head.sgl, &sg_iter, region->nmap, 0) {
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pg_addr = sg_page_iter_dma_address(&sg_iter);
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if (first_pg)
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*pbl = cpu_to_le64(pg_addr & iwmr->page_msk);
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else if (!(pg_addr & ~iwmr->page_msk))
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*pbl = cpu_to_le64(pg_addr);
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else
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continue;
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first_pg = false;
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rdma_for_each_block(region->sg_head.sgl, &biter, region->nmap,
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iwmr->page_size) {
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*pbl = rdma_block_iter_dma_address(&biter);
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pbl = i40iw_next_pbl_addr(pbl, &pinfo, &idx);
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}
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}
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/**
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* i40iw_set_hugetlb_params - set MR pg size and mask to huge pg values.
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* @addr: virtual address
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* @iwmr: mr pointer for this memory registration
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*/
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static void i40iw_set_hugetlb_values(u64 addr, struct i40iw_mr *iwmr)
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{
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struct vm_area_struct *vma;
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struct hstate *h;
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down_read(¤t->mm->mmap_sem);
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vma = find_vma(current->mm, addr);
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if (vma && is_vm_hugetlb_page(vma)) {
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h = hstate_vma(vma);
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if (huge_page_size(h) == 0x200000) {
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iwmr->page_size = huge_page_size(h);
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iwmr->page_msk = huge_page_mask(h);
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}
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}
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up_read(¤t->mm->mmap_sem);
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}
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/**
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* i40iw_check_mem_contiguous - check if pbls stored in arr are contiguous
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* @arr: lvl1 pbl array
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@ -1839,10 +1808,9 @@ static struct ib_mr *i40iw_reg_user_mr(struct ib_pd *pd,
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iwmr->ibmr.device = pd->device;
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iwmr->page_size = PAGE_SIZE;
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iwmr->page_msk = PAGE_MASK;
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if (region->hugetlb && (req.reg_type == IW_MEMREG_TYPE_MEM))
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i40iw_set_hugetlb_values(start, iwmr);
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if (req.reg_type == IW_MEMREG_TYPE_MEM)
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iwmr->page_size = ib_umem_find_best_pgsz(region, SZ_4K | SZ_2M,
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virt);
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region_length = region->length + (start & (iwmr->page_size - 1));
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pg_shift = ffs(iwmr->page_size) - 1;
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@ -94,8 +94,7 @@ struct i40iw_mr {
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struct ib_umem *region;
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u16 type;
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u32 page_cnt;
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u32 page_size;
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u64 page_msk;
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u64 page_size;
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u32 npages;
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u32 stag;
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u64 length;
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