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arm64: dts: zx: support cpu-freq for zx296718 

This patch adds the CPU clock phandle in CPU's node
and uses operating-points-v2 to register operating points.

So it can be used by cpufreq-dt driver.

Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Baoyou Xie 2016-12-02 13:52:36 +08:00 committed by Shawn Guo
parent 0c744ea4f7
commit eb2e2a8168
1 changed files with 39 additions and 0 deletions
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39
arch/arm64/boot/dts/zte/zx296718.dtsi
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@ -44,6 +44,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/zx296718-clock.h>
/ {
compatible = "zte,zx296718";
@ -81,6 +82,8 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@1 {
@ -88,6 +91,8 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@2 {
@ -95,6 +100,8 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@3 {
@ -102,6 +109,38 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
};
cluster0_opp: opp-table0 {
compatible = "operating-points-v2";
opp-shared;
opp@500000000 {
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <500000>;
};
opp@648000000 {
opp-hz = /bits/ 64 <648000000>;
clock-latency-ns = <500000>;
};
opp@800000000 {
opp-hz = /bits/ 64 <800000000>;
clock-latency-ns = <500000>;
};
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
clock-latency-ns = <500000>;
};
opp@1188000000 {
opp-hz = /bits/ 64 <1188000000>;
clock-latency-ns = <500000>;
};
};