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clocksource/arm_arch_timer: Add build-time guards for unhandled register accesses 

As we are about to change the registers that are used by the driver,
start by adding build-time checks to ensure that we always handle
all registers and access modes.

Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-2-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
This commit is contained in:
Marc Zyngier 2021-10-17 13:42:09 +01:00 committed by Jianping Liu
parent 4427b501ef
commit ea9b4217be
3 changed files with 32 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm/include/asm/arch_timer.h
View File

@ -34,6 +34,8 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
case ARCH_TIMER_REG_TVAL: case ARCH_TIMER_REG_TVAL:
asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val)); asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
break; break;
default:
BUILD_BUG();
} }
} else if (access == ARCH_TIMER_VIRT_ACCESS) { } else if (access == ARCH_TIMER_VIRT_ACCESS) {
switch (reg) { switch (reg) {
@ -43,7 +45,11 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
case ARCH_TIMER_REG_TVAL: case ARCH_TIMER_REG_TVAL:
asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val)); asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
break; break;
default:
BUILD_BUG();
} }
} else {
BUILD_BUG();
} }
isb(); isb();
@ -62,6 +68,8 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
case ARCH_TIMER_REG_TVAL: case ARCH_TIMER_REG_TVAL:
asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val)); asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
break; break;
default:
BUILD_BUG();
} }
} else if (access == ARCH_TIMER_VIRT_ACCESS) { } else if (access == ARCH_TIMER_VIRT_ACCESS) {
switch (reg) { switch (reg) {
@ -71,7 +79,11 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
case ARCH_TIMER_REG_TVAL: case ARCH_TIMER_REG_TVAL:
asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val)); asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
break; break;
default:
BUILD_BUG();
} }
} else {
BUILD_BUG();
} }
return val; return val;

13
arch/arm64/include/asm/arch_timer.h
View File

@ -112,6 +112,8 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
case ARCH_TIMER_REG_TVAL: case ARCH_TIMER_REG_TVAL:
write_sysreg(val, cntp_tval_el0); write_sysreg(val, cntp_tval_el0);
break; break;
default:
BUILD_BUG();
} }
} else if (access == ARCH_TIMER_VIRT_ACCESS) { } else if (access == ARCH_TIMER_VIRT_ACCESS) {
switch (reg) { switch (reg) {
@ -121,7 +123,11 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
case ARCH_TIMER_REG_TVAL: case ARCH_TIMER_REG_TVAL:
write_sysreg(val, cntv_tval_el0); write_sysreg(val, cntv_tval_el0);
break; break;
default:
BUILD_BUG();
} }
} else {
BUILD_BUG();
} }
isb(); isb();
@ -136,6 +142,8 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
return read_sysreg(cntp_ctl_el0); return read_sysreg(cntp_ctl_el0);
case ARCH_TIMER_REG_TVAL: case ARCH_TIMER_REG_TVAL:
return arch_timer_reg_read_stable(cntp_tval_el0); return arch_timer_reg_read_stable(cntp_tval_el0);
default:
BUILD_BUG();
} }
} else if (access == ARCH_TIMER_VIRT_ACCESS) { } else if (access == ARCH_TIMER_VIRT_ACCESS) {
switch (reg) { switch (reg) {
@ -143,10 +151,13 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
return read_sysreg(cntv_ctl_el0); return read_sysreg(cntv_ctl_el0);
case ARCH_TIMER_REG_TVAL: case ARCH_TIMER_REG_TVAL:
return arch_timer_reg_read_stable(cntv_tval_el0); return arch_timer_reg_read_stable(cntv_tval_el0);
default:
BUILD_BUG();
} }
} }
BUG(); BUILD_BUG();
unreachable();
} }
static inline u32 arch_timer_get_cntfrq(void) static inline u32 arch_timer_get_cntfrq(void)

8
drivers/clocksource/arm_arch_timer.c
View File

@ -97,6 +97,8 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
case ARCH_TIMER_REG_TVAL: case ARCH_TIMER_REG_TVAL:
writel_relaxed(val, timer->base + CNTP_TVAL); writel_relaxed(val, timer->base + CNTP_TVAL);
break; break;
default:
BUILD_BUG();
} }
} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
struct arch_timer *timer = to_arch_timer(clk); struct arch_timer *timer = to_arch_timer(clk);
@ -107,6 +109,8 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
case ARCH_TIMER_REG_TVAL: case ARCH_TIMER_REG_TVAL:
writel_relaxed(val, timer->base + CNTV_TVAL); writel_relaxed(val, timer->base + CNTV_TVAL);
break; break;
default:
BUILD_BUG();
} }
} else { } else {
arch_timer_reg_write_cp15(access, reg, val); arch_timer_reg_write_cp15(access, reg, val);
@ -128,6 +132,8 @@ u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
case ARCH_TIMER_REG_TVAL: case ARCH_TIMER_REG_TVAL:
val = readl_relaxed(timer->base + CNTP_TVAL); val = readl_relaxed(timer->base + CNTP_TVAL);
break; break;
default:
BUILD_BUG();
} }
} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
struct arch_timer *timer = to_arch_timer(clk); struct arch_timer *timer = to_arch_timer(clk);
@ -138,6 +144,8 @@ u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
case ARCH_TIMER_REG_TVAL: case ARCH_TIMER_REG_TVAL:
val = readl_relaxed(timer->base + CNTV_TVAL); val = readl_relaxed(timer->base + CNTV_TVAL);
break; break;
default:
BUILD_BUG();
} }
} else { } else {
val = arch_timer_reg_read_cp15(access, reg); val = arch_timer_reg_read_cp15(access, reg);