ARM64: dts: meson-gxl: Add ethernet nodes with internal PHY
Add Ethernet node with Internal PHY selection for the Amlogic GXL SoCs Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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@ -49,6 +49,22 @@
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compatible = "amlogic,meson-gxl";
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};
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ðmac {
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reg = <0x0 0xc9410000 0x0 0x10000
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0x0 0xc8834540 0x0 0x4>;
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clocks = <&clkc CLKID_ETH>,
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<&clkc CLKID_FCLK_DIV2>,
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<&clkc CLKID_MPLL2>;
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clock-names = "stmmaceth", "clkin0", "clkin1";
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mdio0: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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};
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};
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&aobus {
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pinctrl_aobus: pinctrl@14 {
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compatible = "amlogic,meson-gxl-aobus-pinctrl";
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@ -214,6 +230,33 @@
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};
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};
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};
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eth-phy-mux {
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compatible = "mdio-mux-mmioreg", "mdio-mux";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x55c 0x0 0x4>;
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mux-mask = <0xffffffff>;
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mdio-parent-bus = <&mdio0>;
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internal_mdio: mdio@e40908ff {
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reg = <0xe40908ff>;
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#address-cells = <1>;
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#size-cells = <0>;
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internal_phy: ethernet-phy@8 {
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compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
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reg = <8>;
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max-speed = <100>;
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};
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};
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external_mdio: mdio@2009087f {
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reg = <0x2009087f>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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&hiubus {
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