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drm/amd/display: use num_timing_generator instead of pipe_count 

The two are not necessarily the same.

Signed-off-by: Ken Chalmers <ken.chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ken Chalmers 2017-11-02 10:45:12 -04:00 committed by Alex Deucher
parent 6ef39a6224
commit e99a30de13
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
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@ -202,7 +202,7 @@ static void dcn10_log_hw_state(struct dc *dc)
DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t "
"h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n");
for (i = 0; i < pool->pipe_count; i++) {
for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
struct timing_generator *tg = pool->timing_generators[i];
struct dcn_otg_state s = {0};