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rtc: abx80x: Add nvmem support 

This adds support for the 256-byte internal RAM. There are two windows
which can be used to access this RAM: 64 bytes at 0x40 (the "standard"
address space) and 128 bytes at 0x80 (the "alternate" address space). We
use the standard address space because it is also accessible over SPI
(if such a port is ever done). We are limited to 32-byte reads for SMBus
compatibility, so there's no advantage to using the alternate address
space.

There are some reserved bits in the EXTRAM register, and the datasheet
doesn't say what to do with them. I've opted to skip a read/modify/write
and just write the whole thing. If this driver is ever converted to
regmap, this would be a good place to use regmap_update_bits.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Link: https://lore.kernel.org/r/20221222214532.1873718-1-sean.anderson@seco.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This commit is contained in:
Sean Anderson 2022-12-22 16:45:31 -05:00 committed by Alexandre Belloni
parent 38892c48e5
commit e90ff8ede7
1 changed files with 77 additions and 0 deletions
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77
drivers/rtc/rtc-abx80x.c
View File

@ -11,6 +11,7 @@
*/
#include <linux/bcd.h>
#include <linux/bitfield.h>
#include <linux/i2c.h>
#include <linux/kstrtox.h>
#include <linux/module.h>
@ -88,6 +89,16 @@
#define ABX8XX_TRICKLE_STANDARD_DIODE 0x8
#define ABX8XX_TRICKLE_SCHOTTKY_DIODE 0x4
#define ABX8XX_REG_EXTRAM 0x3f
#define ABX8XX_EXTRAM_XADS GENMASK(1, 0)
#define ABX8XX_SRAM_BASE 0x40
#define ABX8XX_SRAM_WIN_SIZE 0x40
#define ABX8XX_RAM_SIZE 256
#define NVMEM_ADDR_LOWER GENMASK(5, 0)
#define NVMEM_ADDR_UPPER GENMASK(7, 6)
static u8 trickle_resistors[] = {0, 3, 6, 11};
enum abx80x_chip {AB0801, AB0803, AB0804, AB0805,
@ -674,6 +685,68 @@ static int abx80x_setup_watchdog(struct abx80x_priv *priv)
}
#endif
static int abx80x_nvmem_xfer(struct abx80x_priv *priv, unsigned int offset,
void *val, size_t bytes, bool write)
{
int ret;
while (bytes) {
u8 extram, reg, len, lower, upper;
lower = FIELD_GET(NVMEM_ADDR_LOWER, offset);
upper = FIELD_GET(NVMEM_ADDR_UPPER, offset);
extram = FIELD_PREP(ABX8XX_EXTRAM_XADS, upper);
reg = ABX8XX_SRAM_BASE + lower;
len = min(lower + bytes, (size_t)ABX8XX_SRAM_WIN_SIZE) - lower;
len = min_t(u8, len, I2C_SMBUS_BLOCK_MAX);
ret = i2c_smbus_write_byte_data(priv->client, ABX8XX_REG_EXTRAM,
extram);
if (ret)
return ret;
if (write)
ret = i2c_smbus_write_i2c_block_data(priv->client, reg,
len, val);
else
ret = i2c_smbus_read_i2c_block_data(priv->client, reg,
len, val);
if (ret)
return ret;
offset += len;
val += len;
bytes -= len;
}
return 0;
}
static int abx80x_nvmem_read(void *priv, unsigned int offset, void *val,
size_t bytes)
{
return abx80x_nvmem_xfer(priv, offset, val, bytes, false);
}
static int abx80x_nvmem_write(void *priv, unsigned int offset, void *val,
size_t bytes)
{
return abx80x_nvmem_xfer(priv, offset, val, bytes, true);
}
static int abx80x_setup_nvmem(struct abx80x_priv *priv)
{
struct nvmem_config config = {
.type = NVMEM_TYPE_BATTERY_BACKED,
.reg_read = abx80x_nvmem_read,
.reg_write = abx80x_nvmem_write,
.size = ABX8XX_RAM_SIZE,
.priv = priv,
};
return devm_rtc_nvmem_register(priv->rtc, &config);
}
static const struct i2c_device_id abx80x_id[] = {
{ "abx80x", ABX80X },
{ "ab0801", AB0801 },
@ -840,6 +913,10 @@ static int abx80x_probe(struct i2c_client *client)
return err;
}
err = abx80x_setup_nvmem(priv);
if (err)
return err;
if (client->irq > 0) {
dev_info(&client->dev, "IRQ %d supplied\n", client->irq);
err = devm_request_threaded_irq(&client->dev, client->irq, NULL,