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ARM: dts: meson8b: add the cortex-a5-pmu compatible PMU 

Enable the performance monitor unit on Meson8b.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This commit is contained in:
Martin Blumenstingl 2018-04-22 12:45:02 +02:00 committed by Kevin Hilman
parent 17b66027e6
commit e8d85d7679
1 changed files with 13 additions and 4 deletions
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17
arch/arm/boot/dts/meson8b.dtsi
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@ -55,7 +55,7 @@
#address-cells = <1>;
#size-cells = <0>;
cpu@200 {
cpu0: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
@ -64,7 +64,7 @@
resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
};
cpu@201 {
cpu1: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
@ -73,7 +73,7 @@
resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
};
cpu@202 {
cpu2: cpu@202 {
device_type = "cpu";
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
@ -82,7 +82,7 @@
resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
};
cpu@203 {
cpu3: cpu@203 {
device_type = "cpu";
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
@ -92,6 +92,15 @@
};
};
pmu {
compatible = "arm,cortex-a5-pmu";
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;