net: phy: broadcom: Add LPI counter

Add the ability to read the PHY maintained LPI counter which is in the
Clause 45 vendor space, device address 7, offset 0x803F. The counter is
cleared on read.

Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20230531231729.1873932-1-florian.fainelli@broadcom.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Florian Fainelli 2023-05-31 16:17:29 -07:00 committed by Jakub Kicinski
parent 733b3e2765
commit e8b6f79b41
2 changed files with 14 additions and 7 deletions

View File

@ -496,18 +496,20 @@ EXPORT_SYMBOL_GPL(bcm_phy_downshift_set);
struct bcm_phy_hw_stat {
const char *string;
u8 reg;
int devad;
u16 reg;
u8 shift;
u8 bits;
};
/* Counters freeze at either 0xffff or 0xff, better than nothing */
static const struct bcm_phy_hw_stat bcm_phy_hw_stats[] = {
{ "phy_receive_errors", MII_BRCM_CORE_BASE12, 0, 16 },
{ "phy_serdes_ber_errors", MII_BRCM_CORE_BASE13, 8, 8 },
{ "phy_false_carrier_sense_errors", MII_BRCM_CORE_BASE13, 0, 8 },
{ "phy_local_rcvr_nok", MII_BRCM_CORE_BASE14, 8, 8 },
{ "phy_remote_rcv_nok", MII_BRCM_CORE_BASE14, 0, 8 },
{ "phy_receive_errors", -1, MII_BRCM_CORE_BASE12, 0, 16 },
{ "phy_serdes_ber_errors", -1, MII_BRCM_CORE_BASE13, 8, 8 },
{ "phy_false_carrier_sense_errors", -1, MII_BRCM_CORE_BASE13, 0, 8 },
{ "phy_local_rcvr_nok", -1, MII_BRCM_CORE_BASE14, 8, 8 },
{ "phy_remote_rcv_nok", -1, MII_BRCM_CORE_BASE14, 0, 8 },
{ "phy_lpi_count", MDIO_MMD_AN, BRCM_CL45VEN_EEE_LPI_CNT, 0, 16 },
};
int bcm_phy_get_sset_count(struct phy_device *phydev)
@ -536,7 +538,10 @@ static u64 bcm_phy_get_stat(struct phy_device *phydev, u64 *shadow,
int val;
u64 ret;
val = phy_read(phydev, stat.reg);
if (stat.devad < 0)
val = phy_read(phydev, stat.reg);
else
val = phy_read_mmd(phydev, stat.devad, stat.reg);
if (val < 0) {
ret = U64_MAX;
} else {

View File

@ -359,6 +359,8 @@
#define LPI_FEATURE_EN 0x8000
#define LPI_FEATURE_EN_DIG1000X 0x4000
#define BRCM_CL45VEN_EEE_LPI_CNT 0x803f
/* Core register definitions*/
#define MII_BRCM_CORE_BASE12 0x12
#define MII_BRCM_CORE_BASE13 0x13