powerpc/ftrace: Use PPC_RAW_xxx() macros instead of opencoding.
PPC_RAW_xxx() macros are self explanatory and less error prone than open coding. Use them in ftrace.c Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/9292094c9a69cef6d29ee83f435a557b59c45065.1652074503.git.christophe.leroy@csgroup.eu
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@ -363,6 +363,10 @@
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#define PPC_HIGHER(v) (((v) >> 32) & 0xffff)
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#define PPC_HIGHEST(v) (((v) >> 48) & 0xffff)
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/* LI Field */
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#define PPC_LI_MASK 0x03fffffc
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#define PPC_LI(v) ((v) & PPC_LI_MASK)
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/*
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* Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
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* larx with EH set as an illegal instruction.
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@ -583,6 +587,7 @@
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#define PPC_RAW_EIEIO() (0x7c0006ac)
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#define PPC_RAW_BRANCH(addr) (PPC_INST_BRANCH | ((addr) & 0x03fffffc))
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#define PPC_RAW_BL(offset) (0x48000001 | PPC_LI(offset))
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/* Deal with instructions that older assemblers aren't aware of */
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#define PPC_BCCTR_FLUSH stringify_in_c(.long PPC_INST_BCCTR_FLUSH)
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@ -90,19 +90,19 @@ static int test_24bit_addr(unsigned long ip, unsigned long addr)
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static int is_bl_op(ppc_inst_t op)
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{
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return (ppc_inst_val(op) & 0xfc000003) == 0x48000001;
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return (ppc_inst_val(op) & ~PPC_LI_MASK) == PPC_RAW_BL(0);
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}
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static int is_b_op(ppc_inst_t op)
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{
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return (ppc_inst_val(op) & 0xfc000003) == 0x48000000;
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return (ppc_inst_val(op) & ~PPC_LI_MASK) == PPC_RAW_BRANCH(0);
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}
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static unsigned long find_bl_target(unsigned long ip, ppc_inst_t op)
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{
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int offset;
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offset = (ppc_inst_val(op) & 0x03fffffc);
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offset = PPC_LI(ppc_inst_val(op));
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/* make it signed */
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if (offset & 0x02000000)
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offset |= 0xfe000000;
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@ -182,7 +182,7 @@ __ftrace_make_nop(struct module *mod,
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* Use a b +8 to jump over the load.
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*/
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pop = ppc_inst(PPC_INST_BRANCH | 8); /* b +8 */
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pop = ppc_inst(PPC_RAW_BRANCH(8)); /* b +8 */
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/*
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* Check what is in the next instruction. We can see ld r2,40(r1), but
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@ -394,17 +394,8 @@ int ftrace_make_nop(struct module *mod,
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static int
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expected_nop_sequence(void *ip, ppc_inst_t op0, ppc_inst_t op1)
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{
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/*
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* We expect to see:
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*
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* b +8
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* ld r2,XX(r1)
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*
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* The load offset is different depending on the ABI. For simplicity
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* just mask it out when doing the compare.
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*/
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if (!ppc_inst_equal(op0, ppc_inst(0x48000008)) ||
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(ppc_inst_val(op1) & 0xffff0000) != 0xe8410000)
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if (!ppc_inst_equal(op0, ppc_inst(PPC_RAW_BRANCH(8))) ||
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!ppc_inst_equal(op1, ppc_inst(PPC_INST_LD_TOC)))
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return 0;
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return 1;
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}
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@ -412,7 +403,6 @@ expected_nop_sequence(void *ip, ppc_inst_t op0, ppc_inst_t op1)
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static int
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expected_nop_sequence(void *ip, ppc_inst_t op0, ppc_inst_t op1)
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{
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/* look for patched "NOP" on ppc64 with -mprofile-kernel or ppc32 */
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if (!ppc_inst_equal(op0, ppc_inst(PPC_RAW_NOP())))
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return 0;
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return 1;
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@ -738,11 +728,11 @@ int __init ftrace_dyn_arch_init(void)
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int i;
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unsigned int *tramp[] = { ftrace_tramp_text, ftrace_tramp_init };
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u32 stub_insns[] = {
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0xe98d0000 | PACATOC, /* ld r12,PACATOC(r13) */
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0x3d8c0000, /* addis r12,r12,<high> */
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0x398c0000, /* addi r12,r12,<low> */
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0x7d8903a6, /* mtctr r12 */
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0x4e800420, /* bctr */
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PPC_RAW_LD(_R12, _R13, PACATOC),
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PPC_RAW_ADDIS(_R12, _R12, 0),
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PPC_RAW_ADDI(_R12, _R12, 0),
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PPC_RAW_MTCTR(_R12),
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PPC_RAW_BCTR()
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};
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#ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS
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unsigned long addr = ppc_global_function_entry((void *)ftrace_regs_caller);
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