drm/amdgpu/psp: use a function pointer structure
This way we can make all of the IP specific functions static, and we only need a single entry point into the PSP IP modules. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
97745f6852
commit
e7f9ccb437
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@ -51,29 +51,10 @@ static int psp_sw_init(void *handle)
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switch (adev->asic_type) {
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case CHIP_VEGA10:
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psp->init_microcode = psp_v3_1_init_microcode;
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psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv;
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psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos;
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psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
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psp->ring_init = psp_v3_1_ring_init;
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psp->ring_create = psp_v3_1_ring_create;
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psp->ring_stop = psp_v3_1_ring_stop;
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psp->ring_destroy = psp_v3_1_ring_destroy;
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psp->cmd_submit = psp_v3_1_cmd_submit;
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psp->compare_sram_data = psp_v3_1_compare_sram_data;
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psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
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psp->mode1_reset = psp_v3_1_mode1_reset;
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psp_v3_1_set_psp_funcs(psp);
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break;
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case CHIP_RAVEN:
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psp->init_microcode = psp_v10_0_init_microcode;
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psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
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psp->ring_init = psp_v10_0_ring_init;
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psp->ring_create = psp_v10_0_ring_create;
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psp->ring_stop = psp_v10_0_ring_stop;
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psp->ring_destroy = psp_v10_0_ring_destroy;
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psp->cmd_submit = psp_v10_0_cmd_submit;
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psp->compare_sram_data = psp_v10_0_compare_sram_data;
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psp->mode1_reset = psp_v10_0_mode1_reset;
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psp_v10_0_set_psp_funcs(psp);
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break;
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default:
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return -EINVAL;
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@ -33,6 +33,8 @@
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#define PSP_ASD_SHARED_MEM_SIZE 0x4000
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#define PSP_1_MEG 0x100000
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struct psp_context;
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enum psp_ring_type
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{
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PSP_RING_TYPE__INVALID = 0,
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@ -53,12 +55,8 @@ struct psp_ring
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uint32_t ring_size;
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};
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struct psp_context
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struct psp_funcs
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{
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struct amdgpu_device *adev;
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struct psp_ring km_ring;
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struct psp_gfx_cmd_resp *cmd;
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int (*init_microcode)(struct psp_context *psp);
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int (*bootloader_load_sysdrv)(struct psp_context *psp);
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int (*bootloader_load_sos)(struct psp_context *psp);
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@ -77,6 +75,15 @@ struct psp_context
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enum AMDGPU_UCODE_ID ucode_type);
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bool (*smu_reload_quirk)(struct psp_context *psp);
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int (*mode1_reset)(struct psp_context *psp);
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};
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struct psp_context
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{
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struct amdgpu_device *adev;
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struct psp_ring km_ring;
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struct psp_gfx_cmd_resp *cmd;
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const struct psp_funcs *funcs;
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/* fence buffer */
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struct amdgpu_bo *fw_pri_bo;
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@ -123,25 +130,25 @@ struct amdgpu_psp_funcs {
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enum AMDGPU_UCODE_ID);
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};
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#define psp_prep_cmd_buf(ucode, type) (psp)->prep_cmd_buf((ucode), (type))
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#define psp_ring_init(psp, type) (psp)->ring_init((psp), (type))
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#define psp_ring_create(psp, type) (psp)->ring_create((psp), (type))
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#define psp_ring_stop(psp, type) (psp)->ring_stop((psp), (type))
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#define psp_ring_destroy(psp, type) ((psp)->ring_destroy((psp), (type)))
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#define psp_prep_cmd_buf(ucode, type) (psp)->funcs->prep_cmd_buf((ucode), (type))
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#define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
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#define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
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#define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
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#define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
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#define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \
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(psp)->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index))
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(psp)->funcs->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index))
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#define psp_compare_sram_data(psp, ucode, type) \
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(psp)->compare_sram_data((psp), (ucode), (type))
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(psp)->funcs->compare_sram_data((psp), (ucode), (type))
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#define psp_init_microcode(psp) \
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((psp)->init_microcode ? (psp)->init_microcode((psp)) : 0)
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((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
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#define psp_bootloader_load_sysdrv(psp) \
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((psp)->bootloader_load_sysdrv ? (psp)->bootloader_load_sysdrv((psp)) : 0)
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((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
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#define psp_bootloader_load_sos(psp) \
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((psp)->bootloader_load_sos ? (psp)->bootloader_load_sos((psp)) : 0)
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((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
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#define psp_smu_reload_quirk(psp) \
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((psp)->smu_reload_quirk ? (psp)->smu_reload_quirk((psp)) : false)
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((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
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#define psp_mode1_reset(psp) \
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((psp)->mode1_reset ? (psp)->mode1_reset((psp)) : false)
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((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
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extern const struct amd_ip_funcs psp_ip_funcs;
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@ -87,7 +87,7 @@ psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *
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return 0;
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}
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int psp_v10_0_init_microcode(struct psp_context *psp)
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static int psp_v10_0_init_microcode(struct psp_context *psp)
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{
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struct amdgpu_device *adev = psp->adev;
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const char *chip_name;
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@ -133,7 +133,8 @@ out:
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return err;
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}
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int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd)
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static int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
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struct psp_gfx_cmd_resp *cmd)
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{
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int ret;
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uint64_t fw_mem_mc_addr = ucode->mc_addr;
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@ -152,7 +153,8 @@ int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cm
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return ret;
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}
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int psp_v10_0_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
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static int psp_v10_0_ring_init(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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struct psp_ring *ring;
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@ -177,7 +179,8 @@ int psp_v10_0_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
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return 0;
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}
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int psp_v10_0_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
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static int psp_v10_0_ring_create(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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unsigned int psp_ring_reg = 0;
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@ -208,7 +211,8 @@ int psp_v10_0_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
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return ret;
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}
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int psp_v10_0_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type)
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static int psp_v10_0_ring_stop(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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struct psp_ring *ring;
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@ -231,7 +235,8 @@ int psp_v10_0_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type)
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return ret;
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}
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int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
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static int psp_v10_0_ring_destroy(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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struct psp_ring *ring = &psp->km_ring;
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@ -248,10 +253,10 @@ int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type
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return ret;
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}
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int psp_v10_0_cmd_submit(struct psp_context *psp,
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struct amdgpu_firmware_info *ucode,
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uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
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int index)
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static int psp_v10_0_cmd_submit(struct psp_context *psp,
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struct amdgpu_firmware_info *ucode,
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uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
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int index)
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{
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unsigned int psp_write_ptr_reg = 0;
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struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
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@ -298,9 +303,9 @@ int psp_v10_0_cmd_submit(struct psp_context *psp,
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static int
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psp_v10_0_sram_map(struct amdgpu_device *adev,
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unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
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unsigned int *sram_data_reg_offset,
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enum AMDGPU_UCODE_ID ucode_id)
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unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
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unsigned int *sram_data_reg_offset,
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enum AMDGPU_UCODE_ID ucode_id)
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{
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int ret = 0;
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@ -383,9 +388,9 @@ psp_v10_0_sram_map(struct amdgpu_device *adev,
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return ret;
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}
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bool psp_v10_0_compare_sram_data(struct psp_context *psp,
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struct amdgpu_firmware_info *ucode,
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enum AMDGPU_UCODE_ID ucode_type)
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static bool psp_v10_0_compare_sram_data(struct psp_context *psp,
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struct amdgpu_firmware_info *ucode,
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enum AMDGPU_UCODE_ID ucode_type)
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{
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int err = 0;
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unsigned int fw_sram_reg_val = 0;
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@ -419,8 +424,25 @@ bool psp_v10_0_compare_sram_data(struct psp_context *psp,
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}
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int psp_v10_0_mode1_reset(struct psp_context *psp)
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static int psp_v10_0_mode1_reset(struct psp_context *psp)
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{
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DRM_INFO("psp mode 1 reset not supported now! \n");
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return -EINVAL;
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}
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static const struct psp_funcs psp_v10_0_funcs = {
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.init_microcode = psp_v10_0_init_microcode,
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.prep_cmd_buf = psp_v10_0_prep_cmd_buf,
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.ring_init = psp_v10_0_ring_init,
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.ring_create = psp_v10_0_ring_create,
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.ring_stop = psp_v10_0_ring_stop,
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.ring_destroy = psp_v10_0_ring_destroy,
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.cmd_submit = psp_v10_0_cmd_submit,
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.compare_sram_data = psp_v10_0_compare_sram_data,
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.mode1_reset = psp_v10_0_mode1_reset,
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};
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void psp_v10_0_set_psp_funcs(struct psp_context *psp)
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{
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psp->funcs = &psp_v10_0_funcs;
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}
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@ -27,24 +27,6 @@
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#include "amdgpu_psp.h"
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extern int psp_v10_0_init_microcode(struct psp_context *psp);
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extern int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
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struct psp_gfx_cmd_resp *cmd);
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extern int psp_v10_0_ring_init(struct psp_context *psp,
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enum psp_ring_type ring_type);
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extern int psp_v10_0_ring_create(struct psp_context *psp,
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enum psp_ring_type ring_type);
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extern int psp_v10_0_ring_stop(struct psp_context *psp,
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enum psp_ring_type ring_type);
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extern int psp_v10_0_ring_destroy(struct psp_context *psp,
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enum psp_ring_type ring_type);
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extern int psp_v10_0_cmd_submit(struct psp_context *psp,
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struct amdgpu_firmware_info *ucode,
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uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
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int index);
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extern bool psp_v10_0_compare_sram_data(struct psp_context *psp,
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struct amdgpu_firmware_info *ucode,
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enum AMDGPU_UCODE_ID ucode_type);
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void psp_v10_0_set_psp_funcs(struct psp_context *psp);
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extern int psp_v10_0_mode1_reset(struct psp_context *psp);
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#endif
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@ -93,7 +93,7 @@ psp_v3_1_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *t
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return 0;
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}
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int psp_v3_1_init_microcode(struct psp_context *psp)
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static int psp_v3_1_init_microcode(struct psp_context *psp)
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{
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struct amdgpu_device *adev = psp->adev;
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const char *chip_name;
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@ -161,7 +161,7 @@ out:
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return err;
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}
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int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
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static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
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{
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int ret;
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uint32_t psp_gfxdrv_command_reg = 0;
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@ -202,7 +202,7 @@ int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
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return ret;
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}
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int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
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static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
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{
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int ret;
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unsigned int psp_gfxdrv_command_reg = 0;
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@ -243,7 +243,8 @@ int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
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return ret;
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}
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int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd)
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static int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
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struct psp_gfx_cmd_resp *cmd)
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{
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int ret;
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uint64_t fw_mem_mc_addr = ucode->mc_addr;
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@ -262,7 +263,8 @@ int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd
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return ret;
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}
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int psp_v3_1_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
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static int psp_v3_1_ring_init(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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struct psp_ring *ring;
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@ -287,7 +289,8 @@ int psp_v3_1_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
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return 0;
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}
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int psp_v3_1_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
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static int psp_v3_1_ring_create(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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unsigned int psp_ring_reg = 0;
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@ -318,7 +321,8 @@ int psp_v3_1_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
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return ret;
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}
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int psp_v3_1_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type)
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static int psp_v3_1_ring_stop(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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struct psp_ring *ring;
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@ -341,7 +345,8 @@ int psp_v3_1_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type)
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return ret;
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}
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int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
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static int psp_v3_1_ring_destroy(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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struct psp_ring *ring = &psp->km_ring;
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@ -358,10 +363,10 @@ int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
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return ret;
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}
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int psp_v3_1_cmd_submit(struct psp_context *psp,
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||||
struct amdgpu_firmware_info *ucode,
|
||||
uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
|
||||
int index)
|
||||
static int psp_v3_1_cmd_submit(struct psp_context *psp,
|
||||
struct amdgpu_firmware_info *ucode,
|
||||
uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
|
||||
int index)
|
||||
{
|
||||
unsigned int psp_write_ptr_reg = 0;
|
||||
struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
|
||||
|
|
@ -410,9 +415,9 @@ int psp_v3_1_cmd_submit(struct psp_context *psp,
|
|||
|
||||
static int
|
||||
psp_v3_1_sram_map(struct amdgpu_device *adev,
|
||||
unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
|
||||
unsigned int *sram_data_reg_offset,
|
||||
enum AMDGPU_UCODE_ID ucode_id)
|
||||
unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
|
||||
unsigned int *sram_data_reg_offset,
|
||||
enum AMDGPU_UCODE_ID ucode_id)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
|
|
@ -495,9 +500,9 @@ psp_v3_1_sram_map(struct amdgpu_device *adev,
|
|||
return ret;
|
||||
}
|
||||
|
||||
bool psp_v3_1_compare_sram_data(struct psp_context *psp,
|
||||
struct amdgpu_firmware_info *ucode,
|
||||
enum AMDGPU_UCODE_ID ucode_type)
|
||||
static bool psp_v3_1_compare_sram_data(struct psp_context *psp,
|
||||
struct amdgpu_firmware_info *ucode,
|
||||
enum AMDGPU_UCODE_ID ucode_type)
|
||||
{
|
||||
int err = 0;
|
||||
unsigned int fw_sram_reg_val = 0;
|
||||
|
|
@ -530,7 +535,7 @@ bool psp_v3_1_compare_sram_data(struct psp_context *psp,
|
|||
return true;
|
||||
}
|
||||
|
||||
bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
|
||||
static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
|
||||
{
|
||||
struct amdgpu_device *adev = psp->adev;
|
||||
uint32_t reg;
|
||||
|
|
@ -541,7 +546,7 @@ bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
|
|||
return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
|
||||
}
|
||||
|
||||
int psp_v3_1_mode1_reset(struct psp_context *psp)
|
||||
static int psp_v3_1_mode1_reset(struct psp_context *psp)
|
||||
{
|
||||
int ret;
|
||||
uint32_t offset;
|
||||
|
|
@ -574,3 +579,23 @@ int psp_v3_1_mode1_reset(struct psp_context *psp)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct psp_funcs psp_v3_1_funcs = {
|
||||
.init_microcode = psp_v3_1_init_microcode,
|
||||
.bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
|
||||
.bootloader_load_sos = psp_v3_1_bootloader_load_sos,
|
||||
.prep_cmd_buf = psp_v3_1_prep_cmd_buf,
|
||||
.ring_init = psp_v3_1_ring_init,
|
||||
.ring_create = psp_v3_1_ring_create,
|
||||
.ring_stop = psp_v3_1_ring_stop,
|
||||
.ring_destroy = psp_v3_1_ring_destroy,
|
||||
.cmd_submit = psp_v3_1_cmd_submit,
|
||||
.compare_sram_data = psp_v3_1_compare_sram_data,
|
||||
.smu_reload_quirk = psp_v3_1_smu_reload_quirk,
|
||||
.mode1_reset = psp_v3_1_mode1_reset,
|
||||
};
|
||||
|
||||
void psp_v3_1_set_psp_funcs(struct psp_context *psp)
|
||||
{
|
||||
psp->funcs = &psp_v3_1_funcs;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -32,26 +32,6 @@ enum { PSP_BINARY_ALIGNMENT = 64 };
|
|||
enum { PSP_BOOTLOADER_1_MEG_ALIGNMENT = 0x100000 };
|
||||
enum { PSP_BOOTLOADER_8_MEM_ALIGNMENT = 0x800000 };
|
||||
|
||||
extern int psp_v3_1_init_microcode(struct psp_context *psp);
|
||||
extern int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp);
|
||||
extern int psp_v3_1_bootloader_load_sos(struct psp_context *psp);
|
||||
extern int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
|
||||
struct psp_gfx_cmd_resp *cmd);
|
||||
extern int psp_v3_1_ring_init(struct psp_context *psp,
|
||||
enum psp_ring_type ring_type);
|
||||
extern int psp_v3_1_ring_create(struct psp_context *psp,
|
||||
enum psp_ring_type ring_type);
|
||||
extern int psp_v3_1_ring_stop(struct psp_context *psp,
|
||||
enum psp_ring_type ring_type);
|
||||
extern int psp_v3_1_ring_destroy(struct psp_context *psp,
|
||||
enum psp_ring_type ring_type);
|
||||
extern int psp_v3_1_cmd_submit(struct psp_context *psp,
|
||||
struct amdgpu_firmware_info *ucode,
|
||||
uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
|
||||
int index);
|
||||
extern bool psp_v3_1_compare_sram_data(struct psp_context *psp,
|
||||
struct amdgpu_firmware_info *ucode,
|
||||
enum AMDGPU_UCODE_ID ucode_type);
|
||||
extern bool psp_v3_1_smu_reload_quirk(struct psp_context *psp);
|
||||
extern int psp_v3_1_mode1_reset(struct psp_context *psp);
|
||||
void psp_v3_1_set_psp_funcs(struct psp_context *psp);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue