net: dsa: mv88e6xxx: refine SMI support
The Marvell SOHO switches have several ways to access the internal registers. One of them being the System Management Interface (SMI), using the MDC and MDIO pins, with direct and indirect variants. In preparation for adding support for other register accesses, move the SMI code into its own files. At the same time, refine the code to make it clear that the indirect variant is implemented using the direct variant accessing only two registers for command and data. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vivien Didelot
David S. Miller
parent
7e6a95d31b
commit
e7ba0fad9c
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@ -12,3 +12,4 @@ mv88e6xxx-objs += phy.o
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mv88e6xxx-objs += port.o
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mv88e6xxx-$(CONFIG_NET_DSA_MV88E6XXX_PTP) += ptp.o
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mv88e6xxx-objs += serdes.o
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mv88e6xxx-objs += smi.o
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@ -43,6 +43,7 @@
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#include "port.h"
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#include "ptp.h"
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#include "serdes.h"
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#include "smi.h"
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static void assert_reg_lock(struct mv88e6xxx_chip *chip)
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{
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@ -52,149 +53,6 @@ static void assert_reg_lock(struct mv88e6xxx_chip *chip)
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}
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}
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/* The switch ADDR[4:1] configuration pins define the chip SMI device address
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* (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
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*
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* When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
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* is the only device connected to the SMI master. In this mode it responds to
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* all 32 possible SMI addresses, and thus maps directly the internal devices.
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*
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* When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
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* multiple devices to share the SMI interface. In this mode it responds to only
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* 2 registers, used to indirectly access the internal SMI devices.
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*/
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static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
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int addr, int reg, u16 *val)
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{
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if (!chip->smi_ops)
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return -EOPNOTSUPP;
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return chip->smi_ops->read(chip, addr, reg, val);
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}
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static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
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int addr, int reg, u16 val)
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{
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if (!chip->smi_ops)
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return -EOPNOTSUPP;
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return chip->smi_ops->write(chip, addr, reg, val);
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}
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static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
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int addr, int reg, u16 *val)
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{
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int ret;
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ret = mdiobus_read_nested(chip->bus, addr, reg);
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if (ret < 0)
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return ret;
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*val = ret & 0xffff;
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return 0;
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}
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static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
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int addr, int reg, u16 val)
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{
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int ret;
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ret = mdiobus_write_nested(chip->bus, addr, reg, val);
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if (ret < 0)
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return ret;
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return 0;
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}
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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
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.read = mv88e6xxx_smi_single_chip_read,
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.write = mv88e6xxx_smi_single_chip_write,
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};
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static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
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{
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int ret;
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int i;
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for (i = 0; i < 16; i++) {
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ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
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if (ret < 0)
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return ret;
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if ((ret & SMI_CMD_BUSY) == 0)
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return 0;
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}
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return -ETIMEDOUT;
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}
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static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
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int addr, int reg, u16 *val)
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{
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int ret;
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/* Wait for the bus to become free. */
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ret = mv88e6xxx_smi_multi_chip_wait(chip);
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if (ret < 0)
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return ret;
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/* Transmit the read command. */
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ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
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SMI_CMD_OP_22_READ | (addr << 5) | reg);
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if (ret < 0)
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return ret;
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/* Wait for the read command to complete. */
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ret = mv88e6xxx_smi_multi_chip_wait(chip);
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if (ret < 0)
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return ret;
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/* Read the data. */
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ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
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if (ret < 0)
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return ret;
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*val = ret & 0xffff;
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return 0;
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}
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static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
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int addr, int reg, u16 val)
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{
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int ret;
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/* Wait for the bus to become free. */
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ret = mv88e6xxx_smi_multi_chip_wait(chip);
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if (ret < 0)
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return ret;
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/* Transmit the data to write. */
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ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
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if (ret < 0)
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return ret;
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/* Transmit the write command. */
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ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
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SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
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if (ret < 0)
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return ret;
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/* Wait for the write command to complete. */
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ret = mv88e6xxx_smi_multi_chip_wait(chip);
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if (ret < 0)
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return ret;
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return 0;
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}
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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
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.read = mv88e6xxx_smi_multi_chip_read,
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.write = mv88e6xxx_smi_multi_chip_write,
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};
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int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
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{
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int err;
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@ -4645,22 +4503,6 @@ static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
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return chip;
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}
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static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
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struct mii_bus *bus, int sw_addr)
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{
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if (sw_addr == 0)
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chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
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else if (chip->info->multi_chip)
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chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
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else
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return -EINVAL;
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chip->bus = bus;
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chip->sw_addr = sw_addr;
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return 0;
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}
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static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
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int port)
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{
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@ -21,17 +21,6 @@
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#include <linux/timecounter.h>
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#include <net/dsa.h>
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#define SMI_CMD 0x00
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#define SMI_CMD_BUSY BIT(15)
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#define SMI_CMD_CLAUSE_22 BIT(12)
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#define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
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#define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
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#define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY)
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#define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY)
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#define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY)
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#define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY)
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#define SMI_DATA 0x01
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#define MV88E6XXX_N_FID 4096
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/* PVT limits for 4-bit port and 5-bit switch */
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@ -0,0 +1,158 @@
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/*
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* Marvell 88E6xxx System Management Interface (SMI) support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2019 Vivien Didelot <vivien.didelot@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "chip.h"
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#include "smi.h"
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/* The switch ADDR[4:1] configuration pins define the chip SMI device address
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* (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
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*
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* When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
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* is the only device connected to the SMI master. In this mode it responds to
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* all 32 possible SMI addresses, and thus maps directly the internal devices.
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*
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* When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
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* multiple devices to share the SMI interface. In this mode it responds to only
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* 2 registers, used to indirectly access the internal SMI devices.
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*/
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static int mv88e6xxx_smi_direct_read(struct mv88e6xxx_chip *chip,
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int dev, int reg, u16 *data)
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{
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int ret;
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ret = mdiobus_read_nested(chip->bus, dev, reg);
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if (ret < 0)
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return ret;
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*data = ret & 0xffff;
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return 0;
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}
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static int mv88e6xxx_smi_direct_write(struct mv88e6xxx_chip *chip,
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int dev, int reg, u16 data)
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{
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int ret;
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ret = mdiobus_write_nested(chip->bus, dev, reg, data);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int mv88e6xxx_smi_direct_wait(struct mv88e6xxx_chip *chip,
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int dev, int reg, int bit, int val)
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{
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u16 data;
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int err;
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int i;
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for (i = 0; i < 16; i++) {
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err = mv88e6xxx_smi_direct_read(chip, dev, reg, &data);
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if (err)
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return err;
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if (!!(data >> bit) == !!val)
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return 0;
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}
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return -ETIMEDOUT;
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}
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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_direct_ops = {
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.read = mv88e6xxx_smi_direct_read,
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.write = mv88e6xxx_smi_direct_write,
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};
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/* Offset 0x00: SMI Command Register
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* Offset 0x01: SMI Data Register
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*/
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static int mv88e6xxx_smi_indirect_read(struct mv88e6xxx_chip *chip,
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int dev, int reg, u16 *data)
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{
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int err;
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err = mv88e6xxx_smi_direct_wait(chip, chip->sw_addr,
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MV88E6XXX_SMI_CMD, 15, 0);
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if (err)
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return err;
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err = mv88e6xxx_smi_direct_write(chip, chip->sw_addr,
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MV88E6XXX_SMI_CMD,
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MV88E6XXX_SMI_CMD_BUSY |
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MV88E6XXX_SMI_CMD_MODE_22 |
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MV88E6XXX_SMI_CMD_OP_22_READ |
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(dev << 5) | reg);
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if (err)
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return err;
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err = mv88e6xxx_smi_direct_wait(chip, chip->sw_addr,
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MV88E6XXX_SMI_CMD, 15, 0);
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if (err)
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return err;
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return mv88e6xxx_smi_direct_read(chip, chip->sw_addr,
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MV88E6XXX_SMI_DATA, data);
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}
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static int mv88e6xxx_smi_indirect_write(struct mv88e6xxx_chip *chip,
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int dev, int reg, u16 data)
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{
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int err;
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err = mv88e6xxx_smi_direct_wait(chip, chip->sw_addr,
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MV88E6XXX_SMI_CMD, 15, 0);
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if (err)
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return err;
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err = mv88e6xxx_smi_direct_write(chip, chip->sw_addr,
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MV88E6XXX_SMI_DATA, data);
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if (err)
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return err;
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err = mv88e6xxx_smi_direct_write(chip, chip->sw_addr,
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MV88E6XXX_SMI_CMD,
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MV88E6XXX_SMI_CMD_BUSY |
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MV88E6XXX_SMI_CMD_MODE_22 |
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MV88E6XXX_SMI_CMD_OP_22_WRITE |
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(dev << 5) | reg);
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if (err)
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return err;
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return mv88e6xxx_smi_direct_wait(chip, chip->sw_addr,
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MV88E6XXX_SMI_CMD, 15, 0);
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}
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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_indirect_ops = {
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.read = mv88e6xxx_smi_indirect_read,
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.write = mv88e6xxx_smi_indirect_write,
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};
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int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
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struct mii_bus *bus, int sw_addr)
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{
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if (sw_addr == 0)
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chip->smi_ops = &mv88e6xxx_smi_direct_ops;
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else if (chip->info->multi_chip)
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chip->smi_ops = &mv88e6xxx_smi_indirect_ops;
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else
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return -EINVAL;
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chip->bus = bus;
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chip->sw_addr = sw_addr;
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return 0;
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}
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@ -0,0 +1,59 @@
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/*
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* Marvell 88E6xxx System Management Interface (SMI) support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2019 Vivien Didelot <vivien.didelot@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _MV88E6XXX_SMI_H
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#define _MV88E6XXX_SMI_H
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#include "chip.h"
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/* Offset 0x00: SMI Command Register */
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#define MV88E6XXX_SMI_CMD 0x00
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#define MV88E6XXX_SMI_CMD_BUSY 0x8000
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#define MV88E6XXX_SMI_CMD_MODE_MASK 0x1000
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#define MV88E6XXX_SMI_CMD_MODE_45 0x0000
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#define MV88E6XXX_SMI_CMD_MODE_22 0x1000
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#define MV88E6XXX_SMI_CMD_OP_MASK 0x0c00
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#define MV88E6XXX_SMI_CMD_OP_22_WRITE 0x0400
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#define MV88E6XXX_SMI_CMD_OP_22_READ 0x0800
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#define MV88E6XXX_SMI_CMD_OP_45_WRITE_ADDR 0x0000
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#define MV88E6XXX_SMI_CMD_OP_45_WRITE_DATA 0x0400
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#define MV88E6XXX_SMI_CMD_OP_45_READ_DATA 0x0800
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#define MV88E6XXX_SMI_CMD_OP_45_READ_DATA_INC 0x0c00
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#define MV88E6XXX_SMI_CMD_DEV_ADDR_MASK 0x003e
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#define MV88E6XXX_SMI_CMD_REG_ADDR_MASK 0x001f
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/* Offset 0x01: SMI Data Register */
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#define MV88E6XXX_SMI_DATA 0x01
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int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
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struct mii_bus *bus, int sw_addr);
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static inline int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
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int dev, int reg, u16 *data)
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{
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if (chip->smi_ops && chip->smi_ops->read)
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return chip->smi_ops->read(chip, dev, reg, data);
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return -EOPNOTSUPP;
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}
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static inline int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
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int dev, int reg, u16 data)
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{
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if (chip->smi_ops && chip->smi_ops->write)
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return chip->smi_ops->write(chip, dev, reg, data);
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return -EOPNOTSUPP;
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}
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#endif /* _MV88E6XXX_SMI_H */
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