drm/amd/display: Disable hdmistream and hdmichar clocks
[Why & How] Disable hdmistream and hdmichar root clocks when not being used. Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com> Signed-off-by: Jake Wang <haonan.wang2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -186,8 +186,11 @@
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type SYMCLK32_ROOT_LE0_GATE_DISABLE;\
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type SYMCLK32_ROOT_LE1_GATE_DISABLE;\
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type DPSTREAMCLK_ROOT_GATE_DISABLE;\
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type DPSTREAMCLK_GATE_DISABLE;
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type DPSTREAMCLK_GATE_DISABLE;\
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type HDMISTREAMCLK0_DTO_PHASE;\
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type HDMISTREAMCLK0_DTO_MODULO;\
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type HDMICHARCLK0_GATE_DISABLE;\
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type HDMICHARCLK0_ROOT_GATE_DISABLE;
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struct dccg_shift {
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@ -231,6 +234,8 @@ struct dccg_registers {
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uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;
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uint32_t DPSTREAMCLK_GATE_DISABLE;
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uint32_t DCCG_GATE_DISABLE_CNTL3;
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uint32_t HDMISTREAMCLK0_DTO_PARAM;
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uint32_t DCCG_GATE_DISABLE_CNTL4;
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};
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@ -66,7 +66,8 @@
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SR(DSCCLK1_DTO_PARAM),\
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SR(DSCCLK2_DTO_PARAM),\
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SR(DSCCLK_DTO_CTRL),\
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SR(DCCG_GATE_DISABLE_CNTL3)
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SR(DCCG_GATE_DISABLE_CNTL3),\
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SR(HDMISTREAMCLK0_DTO_PARAM)
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#define DCCG_MASK_SH_LIST_DCN31(mask_sh) \
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@ -141,9 +142,9 @@
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DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\
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DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\
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DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\
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DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh)
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DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\
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DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_PHASE, mask_sh),\
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DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_MODULO, mask_sh)
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struct dccg *dccg31_create(
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@ -436,6 +436,8 @@
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#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2
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#define regDCCG_GATE_DISABLE_CNTL3 0x005a
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#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX 2
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#define regHDMISTREAMCLK0_DTO_PARAM 0x005b
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#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX 2
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#define regDCCG_AUDIO_DTBCLK_DTO_PHASE 0x0061
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#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX 2
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#define regDCCG_AUDIO_DTBCLK_DTO_MODULO 0x0062
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@ -1438,6 +1438,14 @@
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#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE_MASK 0x00200000L
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#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE_MASK 0x00400000L
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#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE_MASK 0x00800000L
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//HDMISTREAMCLK0_DTO_PARAM
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#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE__SHIFT 0x0
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#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO__SHIFT 0x8
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#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN__SHIFT 0x10
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#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE_MASK 0x000000FFL
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#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO_MASK 0x0000FF00L
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#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN_MASK 0x00010000L
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//DCCG_AUDIO_DTBCLK_DTO_PHASE
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#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE__SHIFT 0x0
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#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE_MASK 0xFFFFFFFFL
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