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drm/i915: Parameterize MI_PREDICATE registers 

The various MI_PREDICATE registers have per-engine instances.  Today we
only utilize the RCS0 instance of each, but that will likely change in
the future; switch to parameterized register definitions to make these
easier to work with going forward.

Of special note is MI_PREDICATE_RESULT_2; we only use it in one place in
the driver today in HSW-specific code.  It turns out that the bspec
(page 94) lists two different offsets for this register on HSW; one is
in the standard location shared by all other platforms (base + 0x3bc)
and the other is an unusual location (0x2214).  We're using the second,
non-standard offset in i915 today; that offset doesn't exist on any
other platforms (and it's not even 100% clear that it's correct for HSW)
so I've renamed the current non-standard definition to
HSW_MI_PREDICATE_RESULT_2; the new cross-platform parameterized macro
(which is still unused at the moment) uses the standard offset.

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220127234334.4016964-5-matthew.d.roper@intel.com
This commit is contained in:
Matt Roper 2022-01-27 15:43:32 -08:00
parent 7d296f369d
commit e71a741228
5 changed files with 19 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/drm/i915/gt/intel_engine_regs.h
View File

@ -142,6 +142,17 @@
(REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
#define MI_PREDICATE_RESULT_2(base) _MMIO((base) + 0x3bc)
#define LOWER_SLICE_ENABLED (1 << 0)
#define LOWER_SLICE_DISABLED (0 << 0)
#define MI_PREDICATE_SRC0(base) _MMIO((base) + 0x400)
#define MI_PREDICATE_SRC0_UDW(base) _MMIO((base) + 0x400 + 4)
#define MI_PREDICATE_SRC1(base) _MMIO((base) + 0x408)
#define MI_PREDICATE_SRC1_UDW(base) _MMIO((base) + 0x408 + 4)
#define MI_PREDICATE_DATA(base) _MMIO((base) + 0x410)
#define MI_PREDICATE_RESULT(base) _MMIO((base) + 0x418)
#define MI_PREDICATE_RESULT_1(base) _MMIO((base) + 0x41c)
#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
#define PP_DIR_DCLV_2G 0xffffffff
#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)

2
drivers/gpu/drm/i915/gt/intel_gt.c
View File

@ -208,7 +208,7 @@ int intel_gt_init_hw(struct intel_gt *gt)
if (IS_HASWELL(i915))
intel_uncore_write(uncore,
MI_PREDICATE_RESULT_2,
HSW_MI_PREDICATE_RESULT_2,
IS_HSW_GT3(i915) ?
LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);

4
drivers/gpu/drm/i915/i915_cmd_parser.c
View File

@ -611,8 +611,8 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
REG64(PS_INVOCATION_COUNT),
REG64(PS_DEPTH_COUNT),
REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
REG64(MI_PREDICATE_SRC0),
REG64(MI_PREDICATE_SRC1),
REG64_IDX(MI_PREDICATE_SRC0, RENDER_RING_BASE),
REG64_IDX(MI_PREDICATE_SRC1, RENDER_RING_BASE),
REG32(GEN7_3DPRIM_END_OFFSET),
REG32(GEN7_3DPRIM_START_VERTEX),
REG32(GEN7_3DPRIM_VERTEX_COUNT),

8
drivers/gpu/drm/i915/i915_perf.c
View File

@ -1684,7 +1684,7 @@ retry:
stream, cs, true /* save */, CS_GPR(i),
INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
cs = save_restore_register(
stream, cs, true /* save */, MI_PREDICATE_RESULT_1,
stream, cs, true /* save */, MI_PREDICATE_RESULT_1(RENDER_RING_BASE),
INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
/* First timestamp snapshot location. */
@ -1738,7 +1738,7 @@ retry:
*/
*cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
*cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
*cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
*cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1(RENDER_RING_BASE));
/* Restart from the beginning if we had timestamps roll over. */
*cs++ = (GRAPHICS_VER(i915) < 8 ?
@ -1775,7 +1775,7 @@ retry:
*/
*cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
*cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
*cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
*cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1(RENDER_RING_BASE));
/* Predicate the jump. */
*cs++ = (GRAPHICS_VER(i915) < 8 ?
@ -1791,7 +1791,7 @@ retry:
stream, cs, false /* restore */, CS_GPR(i),
INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
cs = save_restore_register(
stream, cs, false /* restore */, MI_PREDICATE_RESULT_1,
stream, cs, false /* restore */, MI_PREDICATE_RESULT_1(RENDER_RING_BASE),
INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
/* And return to the ring. */

11
drivers/gpu/drm/i915/i915_reg.h
View File

@ -353,16 +353,7 @@
#define _VGA_MSR_WRITE _MMIO(0x3c2)
#define MI_PREDICATE_SRC0 _MMIO(0x2400)
#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
#define MI_PREDICATE_SRC1 _MMIO(0x2408)
#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
#define MI_PREDICATE_DATA _MMIO(0x2410)
#define MI_PREDICATE_RESULT _MMIO(0x2418)
#define MI_PREDICATE_RESULT_1 _MMIO(0x241c)
#define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
#define LOWER_SLICE_ENABLED (1 << 0)
#define LOWER_SLICE_DISABLED (0 << 0)
#define HSW_MI_PREDICATE_RESULT_2 _MMIO(0x2214)
/*
* Registers used only by the command parser