Merge branch 'samsung/exynos5' into next/soc2
This commit is contained in:
Arnd Bergmann
commit
e7051e9dab
|
|
@ -3780,7 +3780,7 @@ F: Documentation/kdump/
|
|||
|
||||
KERNEL AUTOMOUNTER v4 (AUTOFS4)
|
||||
M: Ian Kent <raven@themaw.net>
|
||||
L: autofs@linux.kernel.org
|
||||
L: autofs@vger.kernel.org
|
||||
S: Maintained
|
||||
F: fs/autofs4/
|
||||
|
||||
|
|
@ -4685,7 +4685,7 @@ NTFS FILESYSTEM
|
|||
M: Anton Altaparmakov <anton@tuxera.com>
|
||||
L: linux-ntfs-dev@lists.sourceforge.net
|
||||
W: http://www.tuxera.com/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/aia21/ntfs-2.6.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/aia21/ntfs.git
|
||||
S: Supported
|
||||
F: Documentation/filesystems/ntfs.txt
|
||||
F: fs/ntfs/
|
||||
|
|
@ -7271,7 +7271,7 @@ WATCHDOG DEVICE DRIVERS
|
|||
M: Wim Van Sebroeck <wim@iguana.be>
|
||||
L: linux-watchdog@vger.kernel.org
|
||||
W: http://www.linux-watchdog.org/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/wim/linux-2.6-watchdog.git
|
||||
T: git git://www.linux-watchdog.org/linux-watchdog.git
|
||||
S: Maintained
|
||||
F: Documentation/watchdog/
|
||||
F: drivers/watchdog/
|
||||
|
|
|
|||
2
Makefile
2
Makefile
|
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 3
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc5
|
||||
EXTRAVERSION = -rc6
|
||||
NAME = Saber-toothed Squirrel
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
|||
|
|
@ -180,6 +180,7 @@ machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
|
|||
machine-$(CONFIG_ARCH_S5PC100) := s5pc100
|
||||
machine-$(CONFIG_ARCH_S5PV210) := s5pv210
|
||||
machine-$(CONFIG_ARCH_EXYNOS4) := exynos
|
||||
machine-$(CONFIG_ARCH_EXYNOS5) := exynos
|
||||
machine-$(CONFIG_ARCH_SA1100) := sa1100
|
||||
machine-$(CONFIG_ARCH_SHARK) := shark
|
||||
machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
|
||||
|
|
|
|||
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* SAMSUNG SMDK5250 board device tree source
|
||||
*
|
||||
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos5250.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
|
||||
compatible = "samsung,smdk5250", "samsung,exynos5250";
|
||||
|
||||
memory {
|
||||
reg = <0x40000000 0x80000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,413 @@
|
|||
/*
|
||||
* SAMSUNG EXYNOS5250 SoC device tree source
|
||||
*
|
||||
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
|
||||
* EXYNOS5250 based board files can include this file and provide
|
||||
* values for board specfic bindings.
|
||||
*
|
||||
* Note: This file does not include device nodes for all the controllers in
|
||||
* EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
|
||||
* additional nodes can be added to this file.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "samsung,exynos5250";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
gic:interrupt-controller@10490000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x10490000 0x1000>, <0x10480000 0x100>;
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "samsung,s3c2410-wdt";
|
||||
reg = <0x101D0000 0x100>;
|
||||
interrupts = <0 42 0>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
compatible = "samsung,s3c6410-rtc";
|
||||
reg = <0x101E0000 0x100>;
|
||||
interrupts = <0 43 0>, <0 44 0>;
|
||||
};
|
||||
|
||||
sdhci@12200000 {
|
||||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12200000 0x100>;
|
||||
interrupts = <0 75 0>;
|
||||
};
|
||||
|
||||
sdhci@12210000 {
|
||||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12210000 0x100>;
|
||||
interrupts = <0 76 0>;
|
||||
};
|
||||
|
||||
sdhci@12220000 {
|
||||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12220000 0x100>;
|
||||
interrupts = <0 77 0>;
|
||||
};
|
||||
|
||||
sdhci@12230000 {
|
||||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12230000 0x100>;
|
||||
interrupts = <0 78 0>;
|
||||
};
|
||||
|
||||
serial@12C00000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C00000 0x100>;
|
||||
interrupts = <0 51 0>;
|
||||
};
|
||||
|
||||
serial@12C10000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C10000 0x100>;
|
||||
interrupts = <0 52 0>;
|
||||
};
|
||||
|
||||
serial@12C20000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C20000 0x100>;
|
||||
interrupts = <0 53 0>;
|
||||
};
|
||||
|
||||
serial@12C30000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C30000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
};
|
||||
|
||||
i2c@12C60000 {
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x12C60000 0x100>;
|
||||
interrupts = <0 56 0>;
|
||||
};
|
||||
|
||||
i2c@12C70000 {
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x12C70000 0x100>;
|
||||
interrupts = <0 57 0>;
|
||||
};
|
||||
|
||||
i2c@12C80000 {
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x12C80000 0x100>;
|
||||
interrupts = <0 58 0>;
|
||||
};
|
||||
|
||||
i2c@12C90000 {
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x12C90000 0x100>;
|
||||
interrupts = <0 59 0>;
|
||||
};
|
||||
|
||||
i2c@12CA0000 {
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x12CA0000 0x100>;
|
||||
interrupts = <0 60 0>;
|
||||
};
|
||||
|
||||
i2c@12CB0000 {
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x12CB0000 0x100>;
|
||||
interrupts = <0 61 0>;
|
||||
};
|
||||
|
||||
i2c@12CC0000 {
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x12CC0000 0x100>;
|
||||
interrupts = <0 62 0>;
|
||||
};
|
||||
|
||||
i2c@12CD0000 {
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x12CD0000 0x100>;
|
||||
interrupts = <0 63 0>;
|
||||
};
|
||||
|
||||
amba {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "arm,amba-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
pdma0: pdma@121A0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121A0000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
};
|
||||
|
||||
pdma1: pdma@121B0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121B0000 0x1000>;
|
||||
interrupts = <0 35 0>;
|
||||
};
|
||||
|
||||
mdma0: pdma@10800000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x10800000 0x1000>;
|
||||
interrupts = <0 33 0>;
|
||||
};
|
||||
|
||||
mdma1: pdma@11C10000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x11C10000 0x1000>;
|
||||
interrupts = <0 124 0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-controllers {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
gpio-controller;
|
||||
ranges;
|
||||
|
||||
gpa0: gpio-controller@11400000 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400000 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpa1: gpio-controller@11400020 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400020 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpa2: gpio-controller@11400040 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400040 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpb0: gpio-controller@11400060 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400060 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpb1: gpio-controller@11400080 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400080 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpb2: gpio-controller@114000A0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114000A0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpb3: gpio-controller@114000C0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114000C0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpc0: gpio-controller@114000E0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114000E0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpc1: gpio-controller@11400100 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400100 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpc2: gpio-controller@11400120 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400120 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpc3: gpio-controller@11400140 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400140 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpd0: gpio-controller@11400160 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400160 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpd1: gpio-controller@11400180 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400180 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy0: gpio-controller@114001A0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114001A0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy1: gpio-controller@114001C0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114001C0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy2: gpio-controller@114001E0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114001E0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy3: gpio-controller@11400200 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400200 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy4: gpio-controller@11400220 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400220 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy5: gpio-controller@11400240 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400240 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy6: gpio-controller@11400260 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400260 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpx0: gpio-controller@11400C00 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400C00 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpx1: gpio-controller@11400C20 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400C20 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpx2: gpio-controller@11400C40 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400C40 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpx3: gpio-controller@11400C60 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400C60 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpe0: gpio-controller@13400000 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x13400000 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpe1: gpio-controller@13400020 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x13400020 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpf0: gpio-controller@13400040 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x13400040 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpf1: gpio-controller@13400060 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x13400060 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpg0: gpio-controller@13400080 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x13400080 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpg1: gpio-controller@134000A0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x134000A0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpg2: gpio-controller@134000C0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x134000C0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gph0: gpio-controller@134000E0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x134000E0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gph1: gpio-controller@13400100 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x13400100 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpv0: gpio-controller@10D10000 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x10D10000 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpv1: gpio-controller@10D10020 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x10D10020 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpv2: gpio-controller@10D10040 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x10D10040 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpv3: gpio-controller@10D10060 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x10D10060 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpv4: gpio-controller@10D10080 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x10D10080 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpz: gpio-controller@03860000 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x03860000 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -11,18 +11,19 @@ if ARCH_EXYNOS
|
|||
|
||||
menu "SAMSUNG EXYNOS SoCs Support"
|
||||
|
||||
choice
|
||||
prompt "EXYNOS System Type"
|
||||
default ARCH_EXYNOS4
|
||||
|
||||
config ARCH_EXYNOS4
|
||||
bool "SAMSUNG EXYNOS4"
|
||||
default y
|
||||
select HAVE_SMP
|
||||
select MIGHT_HAVE_CACHE_L2X0
|
||||
help
|
||||
Samsung EXYNOS4 SoCs based systems
|
||||
|
||||
endchoice
|
||||
config ARCH_EXYNOS5
|
||||
bool "SAMSUNG EXYNOS5"
|
||||
select HAVE_SMP
|
||||
help
|
||||
Samsung EXYNOS5 (Cortex-A15) SoC based systems
|
||||
|
||||
comment "EXYNOS SoCs"
|
||||
|
||||
|
|
@ -41,6 +42,7 @@ config SOC_EXYNOS4212
|
|||
bool "SAMSUNG EXYNOS4212"
|
||||
default y
|
||||
depends on ARCH_EXYNOS4
|
||||
select SAMSUNG_DMADEV
|
||||
select S5P_PM if PM
|
||||
select S5P_SLEEP if PM
|
||||
help
|
||||
|
|
@ -50,9 +52,17 @@ config SOC_EXYNOS4412
|
|||
bool "SAMSUNG EXYNOS4412"
|
||||
default y
|
||||
depends on ARCH_EXYNOS4
|
||||
select SAMSUNG_DMADEV
|
||||
help
|
||||
Enable EXYNOS4412 SoC support
|
||||
|
||||
config SOC_EXYNOS5250
|
||||
bool "SAMSUNG EXYNOS5250"
|
||||
default y
|
||||
depends on ARCH_EXYNOS5
|
||||
help
|
||||
Enable EXYNOS5250 SoC support
|
||||
|
||||
config EXYNOS4_MCT
|
||||
bool
|
||||
default y
|
||||
|
|
@ -333,6 +343,7 @@ config MACH_SMDK4212
|
|||
select SAMSUNG_DEV_BACKLIGHT
|
||||
select SAMSUNG_DEV_KEYPAD
|
||||
select SAMSUNG_DEV_PWM
|
||||
select EXYNOS4_DEV_DMA
|
||||
select EXYNOS4_SETUP_I2C1
|
||||
select EXYNOS4_SETUP_I2C3
|
||||
select EXYNOS4_SETUP_I2C7
|
||||
|
|
@ -351,7 +362,7 @@ config MACH_SMDK4412
|
|||
Machine support for Samsung SMDK4412
|
||||
endif
|
||||
|
||||
comment "Flattened Device Tree based board for Exynos4 based SoC"
|
||||
comment "Flattened Device Tree based board for EXYNOS SoCs"
|
||||
|
||||
config MACH_EXYNOS4_DT
|
||||
bool "Samsung Exynos4 Machine using device tree"
|
||||
|
|
@ -365,6 +376,15 @@ config MACH_EXYNOS4_DT
|
|||
Note: This is under development and not all peripherals can be supported
|
||||
with this machine file.
|
||||
|
||||
config MACH_EXYNOS5_DT
|
||||
bool "SAMSUNG EXYNOS5 Machine using device tree"
|
||||
select SOC_EXYNOS5250
|
||||
select USE_OF
|
||||
select ARM_AMBA
|
||||
help
|
||||
Machine support for Samsung Exynos4 machine with device tree enabled.
|
||||
Select this if a fdt blob is available for the EXYNOS4 SoC based board.
|
||||
|
||||
if ARCH_EXYNOS4
|
||||
|
||||
comment "Configuration for HSMMC 8-bit bus width"
|
||||
|
|
|
|||
|
|
@ -12,7 +12,9 @@ obj- :=
|
|||
|
||||
# Core
|
||||
|
||||
obj-$(CONFIG_ARCH_EXYNOS4) += common.o clock.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS) += common.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS5) += clock-exynos5.o
|
||||
obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
|
||||
obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
|
||||
|
||||
|
|
@ -40,9 +42,11 @@ obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o
|
|||
obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o
|
||||
|
||||
obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
|
||||
obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
|
||||
|
||||
# device support
|
||||
|
||||
obj-y += dev-uart.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
|
||||
obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
|
||||
obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
|
||||
|
|
@ -51,7 +55,7 @@ obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
|
|||
obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o
|
||||
obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
|
||||
|
||||
obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Header file for exynos4 clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H __FILE__
|
||||
|
||||
#include <linux/clk.h>
|
||||
|
||||
extern struct clksrc_clk exynos4_clk_aclk_133;
|
||||
extern struct clksrc_clk exynos4_clk_mout_mpll;
|
||||
|
||||
extern struct clksrc_sources exynos4_clkset_mout_corebus;
|
||||
extern struct clksrc_sources exynos4_clkset_group;
|
||||
|
||||
extern struct clk *exynos4_clkset_aclk_top_list[];
|
||||
extern struct clk *exynos4_clkset_group_list[];
|
||||
|
||||
extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
|
||||
|
||||
#endif /* __ASM_ARCH_CLOCK_H */
|
||||
|
|
@ -1,7 +1,5 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-exynos4/clock-exynos4210.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4210 - Clock support
|
||||
|
|
@ -28,20 +26,20 @@
|
|||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/exynos4-clock.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "clock-exynos4.h"
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save exynos4210_clock_save[] = {
|
||||
SAVE_ITEM(S5P_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKSRC_LCD1),
|
||||
SAVE_ITEM(S5P_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKDIV_LCD1),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
|
||||
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -51,7 +49,7 @@ static struct clksrc_clk *sysclks[] = {
|
|||
|
||||
static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
|
||||
return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
|
||||
}
|
||||
|
||||
static struct clksrc_clk clksrcs[] = {
|
||||
|
|
@ -62,9 +60,9 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
},
|
||||
.sources = &clkset_mout_corebus,
|
||||
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
|
||||
.reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
|
||||
.sources = &exynos4_clkset_mout_corebus,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
|
||||
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimd",
|
||||
|
|
@ -72,9 +70,9 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.enable = exynos4_clksrc_mask_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
.reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
|
||||
.reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
|
||||
.sources = &exynos4_clkset_group,
|
||||
.reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
|
||||
.reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -82,13 +80,13 @@ static struct clk init_clocks_off[] = {
|
|||
{
|
||||
.name = "sataphy",
|
||||
.id = -1,
|
||||
.parent = &clk_aclk_133.clk,
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "sata",
|
||||
.id = -1,
|
||||
.parent = &clk_aclk_133.clk,
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 10),
|
||||
}, {
|
||||
|
|
@ -117,7 +115,7 @@ static void exynos4210_clock_resume(void)
|
|||
#define exynos4210_clock_resume NULL
|
||||
#endif
|
||||
|
||||
struct syscore_ops exynos4210_clock_syscore_ops = {
|
||||
static struct syscore_ops exynos4210_clock_syscore_ops = {
|
||||
.suspend = exynos4210_clock_suspend,
|
||||
.resume = exynos4210_clock_resume,
|
||||
};
|
||||
|
|
@ -126,9 +124,9 @@ void __init exynos4210_register_clocks(void)
|
|||
{
|
||||
int ptr;
|
||||
|
||||
clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
|
||||
clk_mout_mpll.reg_src.shift = 8;
|
||||
clk_mout_mpll.reg_src.size = 1;
|
||||
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
|
||||
exynos4_clk_mout_mpll.reg_src.shift = 8;
|
||||
exynos4_clk_mout_mpll.reg_src.size = 1;
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
||||
s3c_register_clksrc(sysclks[ptr], 1);
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-exynos4/clock-exynos4212.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4212 - Clock support
|
||||
|
|
@ -28,22 +26,22 @@
|
|||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/exynos4-clock.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "clock-exynos4.h"
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save exynos4212_clock_save[] = {
|
||||
SAVE_ITEM(S5P_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
|
||||
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct clk *clk_src_mpll_user_list[] = {
|
||||
[0] = &clk_fin_mpll,
|
||||
[1] = &clk_mout_mpll.clk,
|
||||
[1] = &exynos4_clk_mout_mpll.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_sources clk_src_mpll_user = {
|
||||
|
|
@ -56,7 +54,7 @@ static struct clksrc_clk clk_mout_mpll_user = {
|
|||
.name = "mout_mpll_user",
|
||||
},
|
||||
.sources = &clk_src_mpll_user,
|
||||
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk *sysclks[] = {
|
||||
|
|
@ -89,7 +87,7 @@ static void exynos4212_clock_resume(void)
|
|||
#define exynos4212_clock_resume NULL
|
||||
#endif
|
||||
|
||||
struct syscore_ops exynos4212_clock_syscore_ops = {
|
||||
static struct syscore_ops exynos4212_clock_syscore_ops = {
|
||||
.suspend = exynos4212_clock_suspend,
|
||||
.resume = exynos4212_clock_resume,
|
||||
};
|
||||
|
|
@ -99,15 +97,15 @@ void __init exynos4212_register_clocks(void)
|
|||
int ptr;
|
||||
|
||||
/* usbphy1 is removed */
|
||||
clkset_group_list[4] = NULL;
|
||||
exynos4_clkset_group_list[4] = NULL;
|
||||
|
||||
/* mout_mpll_user is used */
|
||||
clkset_group_list[6] = &clk_mout_mpll_user.clk;
|
||||
clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
|
||||
exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
|
||||
exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
|
||||
|
||||
clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
|
||||
clk_mout_mpll.reg_src.shift = 12;
|
||||
clk_mout_mpll.reg_src.size = 1;
|
||||
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
|
||||
exynos4_clk_mout_mpll.reg_src.shift = 12;
|
||||
exynos4_clk_mout_mpll.reg_src.size = 1;
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
||||
s3c_register_clksrc(sysclks[ptr], 1);
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -49,6 +49,14 @@
|
|||
static const char name_exynos4210[] = "EXYNOS4210";
|
||||
static const char name_exynos4212[] = "EXYNOS4212";
|
||||
static const char name_exynos4412[] = "EXYNOS4412";
|
||||
static const char name_exynos5250[] = "EXYNOS5250";
|
||||
|
||||
static void exynos4_map_io(void);
|
||||
static void exynos5_map_io(void);
|
||||
static void exynos4_init_clocks(int xtal);
|
||||
static void exynos5_init_clocks(int xtal);
|
||||
static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
static int exynos_init(void);
|
||||
|
||||
static struct cpu_table cpu_ids[] __initdata = {
|
||||
{
|
||||
|
|
@ -56,7 +64,7 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init_uarts = exynos_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4210,
|
||||
}, {
|
||||
|
|
@ -64,7 +72,7 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init_uarts = exynos_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4212,
|
||||
}, {
|
||||
|
|
@ -72,9 +80,17 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init_uarts = exynos_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4412,
|
||||
}, {
|
||||
.idcode = EXYNOS5250_SOC_ID,
|
||||
.idmask = EXYNOS5_SOC_MASK,
|
||||
.map_io = exynos5_map_io,
|
||||
.init_clocks = exynos5_init_clocks,
|
||||
.init_uarts = exynos_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos5250,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -83,10 +99,14 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
static struct map_desc exynos_iodesc[] __initdata = {
|
||||
{
|
||||
.virtual = (unsigned long)S5P_VA_CHIPID,
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_CHIPID),
|
||||
.pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
},
|
||||
};
|
||||
|
||||
static struct map_desc exynos4_iodesc[] __initdata = {
|
||||
{
|
||||
.virtual = (unsigned long)S3C_VA_SYS,
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
|
||||
.length = SZ_64K,
|
||||
|
|
@ -136,11 +156,7 @@ static struct map_desc exynos_iodesc[] __initdata = {
|
|||
.pfn = __phys_to_pfn(EXYNOS4_PA_UART),
|
||||
.length = SZ_512K,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct map_desc exynos4_iodesc[] __initdata = {
|
||||
{
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_CMU,
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
|
||||
.length = SZ_128K,
|
||||
|
|
@ -201,11 +217,80 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct map_desc exynos5_iodesc[] __initdata = {
|
||||
{
|
||||
.virtual = (unsigned long)S3C_VA_SYS,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
|
||||
.length = SZ_64K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S3C_VA_TIMER,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
|
||||
.length = SZ_16K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S3C_VA_WATCHDOG,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_SROMC,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_SYSTIMER,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_SYSRAM,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_CMU,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
|
||||
.length = 144 * SZ_1K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_PMU,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
|
||||
.length = SZ_64K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_COMBINER),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S3C_VA_UART,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_UART),
|
||||
.length = SZ_512K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_GIC_CPU,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
|
||||
.length = SZ_64K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_GIC_DIST,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
|
||||
.length = SZ_64K,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
void exynos4_restart(char mode, const char *cmd)
|
||||
{
|
||||
__raw_writel(0x1, S5P_SWRESET);
|
||||
}
|
||||
|
||||
void exynos5_restart(char mode, const char *cmd)
|
||||
{
|
||||
__raw_writel(0x1, EXYNOS_SWRESET);
|
||||
}
|
||||
|
||||
/*
|
||||
* exynos_map_io
|
||||
*
|
||||
|
|
@ -225,7 +310,7 @@ void __init exynos_init_io(struct map_desc *mach_desc, int size)
|
|||
s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
|
||||
}
|
||||
|
||||
void __init exynos4_map_io(void)
|
||||
static void __init exynos4_map_io(void)
|
||||
{
|
||||
iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
|
||||
|
||||
|
|
@ -256,7 +341,22 @@ void __init exynos4_map_io(void)
|
|||
s5p_hdmi_setname("exynos4-hdmi");
|
||||
}
|
||||
|
||||
void __init exynos4_init_clocks(int xtal)
|
||||
static void __init exynos5_map_io(void)
|
||||
{
|
||||
iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
|
||||
|
||||
s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
|
||||
s3c_device_i2c0.resource[0].end = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
|
||||
s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
|
||||
s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
|
||||
|
||||
/* The I2C bus controllers are directly compatible with s3c2440 */
|
||||
s3c_i2c0_setname("s3c2440-i2c");
|
||||
s3c_i2c1_setname("s3c2440-i2c");
|
||||
s3c_i2c2_setname("s3c2440-i2c");
|
||||
}
|
||||
|
||||
static void __init exynos4_init_clocks(int xtal)
|
||||
{
|
||||
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
|
||||
|
||||
|
|
@ -272,6 +372,17 @@ void __init exynos4_init_clocks(int xtal)
|
|||
exynos4_setup_clocks();
|
||||
}
|
||||
|
||||
static void __init exynos5_init_clocks(int xtal)
|
||||
{
|
||||
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
|
||||
|
||||
s3c24xx_register_baseclocks(xtal);
|
||||
s5p_register_clocks(xtal);
|
||||
|
||||
exynos5_register_clocks();
|
||||
exynos5_setup_clocks();
|
||||
}
|
||||
|
||||
#define COMBINER_ENABLE_SET 0x0
|
||||
#define COMBINER_ENABLE_CLEAR 0x4
|
||||
#define COMBINER_INT_STATUS 0xC
|
||||
|
|
@ -345,7 +456,14 @@ static struct irq_chip combiner_chip = {
|
|||
|
||||
static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
|
||||
{
|
||||
if (combiner_nr >= MAX_COMBINER_NR)
|
||||
unsigned int max_nr;
|
||||
|
||||
if (soc_is_exynos5250())
|
||||
max_nr = EXYNOS5_MAX_COMBINER_NR;
|
||||
else
|
||||
max_nr = EXYNOS4_MAX_COMBINER_NR;
|
||||
|
||||
if (combiner_nr >= max_nr)
|
||||
BUG();
|
||||
if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
|
||||
BUG();
|
||||
|
|
@ -356,8 +474,14 @@ static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
|
|||
unsigned int irq_start)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned int max_nr;
|
||||
|
||||
if (combiner_nr >= MAX_COMBINER_NR)
|
||||
if (soc_is_exynos5250())
|
||||
max_nr = EXYNOS5_MAX_COMBINER_NR;
|
||||
else
|
||||
max_nr = EXYNOS4_MAX_COMBINER_NR;
|
||||
|
||||
if (combiner_nr >= max_nr)
|
||||
BUG();
|
||||
|
||||
combiner_data[combiner_nr].base = base;
|
||||
|
|
@ -400,7 +524,7 @@ void __init exynos4_init_irq(void)
|
|||
of_irq_init(exynos4_dt_irq_match);
|
||||
#endif
|
||||
|
||||
for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
|
||||
for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
|
||||
|
||||
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
|
||||
COMBINER_IRQ(irq, 0));
|
||||
|
|
@ -415,24 +539,59 @@ void __init exynos4_init_irq(void)
|
|||
s5p_init_irq(NULL, 0);
|
||||
}
|
||||
|
||||
void __init exynos5_init_irq(void)
|
||||
{
|
||||
int irq;
|
||||
|
||||
gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
|
||||
|
||||
for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
|
||||
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
|
||||
COMBINER_IRQ(irq, 0));
|
||||
combiner_cascade_irq(irq, IRQ_SPI(irq));
|
||||
}
|
||||
|
||||
/*
|
||||
* The parameters of s5p_init_irq() are for VIC init.
|
||||
* Theses parameters should be NULL and 0 because EXYNOS4
|
||||
* uses GIC instead of VIC.
|
||||
*/
|
||||
s5p_init_irq(NULL, 0);
|
||||
}
|
||||
|
||||
struct bus_type exynos4_subsys = {
|
||||
.name = "exynos4-core",
|
||||
.dev_name = "exynos4-core",
|
||||
};
|
||||
|
||||
struct bus_type exynos5_subsys = {
|
||||
.name = "exynos5-core",
|
||||
.dev_name = "exynos5-core",
|
||||
};
|
||||
|
||||
static struct device exynos4_dev = {
|
||||
.bus = &exynos4_subsys,
|
||||
};
|
||||
|
||||
static int __init exynos4_core_init(void)
|
||||
static struct device exynos5_dev = {
|
||||
.bus = &exynos5_subsys,
|
||||
};
|
||||
|
||||
static int __init exynos_core_init(void)
|
||||
{
|
||||
return subsys_system_register(&exynos4_subsys, NULL);
|
||||
if (soc_is_exynos5250())
|
||||
return subsys_system_register(&exynos5_subsys, NULL);
|
||||
else
|
||||
return subsys_system_register(&exynos4_subsys, NULL);
|
||||
}
|
||||
core_initcall(exynos4_core_init);
|
||||
core_initcall(exynos_core_init);
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
static int __init exynos4_l2x0_cache_init(void)
|
||||
{
|
||||
if (soc_is_exynos5250())
|
||||
return 0;
|
||||
|
||||
/* TAG, Data Latency Control: 2cycle */
|
||||
__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
|
||||
|
||||
|
|
@ -452,19 +611,47 @@ static int __init exynos4_l2x0_cache_init(void)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
early_initcall(exynos4_l2x0_cache_init);
|
||||
#endif
|
||||
|
||||
int __init exynos_init(void)
|
||||
static int __init exynos5_l2_cache_init(void)
|
||||
{
|
||||
unsigned int val;
|
||||
|
||||
if (!soc_is_exynos5250())
|
||||
return 0;
|
||||
|
||||
asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
|
||||
"bic %0, %0, #(1 << 2)\n" /* cache disable */
|
||||
"mcr p15, 0, %0, c1, c0, 0\n"
|
||||
"mrc p15, 1, %0, c9, c0, 2\n"
|
||||
: "=r"(val));
|
||||
|
||||
val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
|
||||
|
||||
asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
|
||||
asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
|
||||
"orr %0, %0, #(1 << 2)\n" /* cache enable */
|
||||
"mcr p15, 0, %0, c1, c0, 0\n"
|
||||
: : "r"(val));
|
||||
|
||||
return 0;
|
||||
}
|
||||
early_initcall(exynos5_l2_cache_init);
|
||||
|
||||
static int __init exynos_init(void)
|
||||
{
|
||||
printk(KERN_INFO "EXYNOS: Initializing architecture\n");
|
||||
return device_register(&exynos4_dev);
|
||||
|
||||
if (soc_is_exynos5250())
|
||||
return device_register(&exynos5_dev);
|
||||
else
|
||||
return device_register(&exynos4_dev);
|
||||
}
|
||||
|
||||
/* uart registration process */
|
||||
|
||||
void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
|
||||
static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
|
||||
{
|
||||
struct s3c2410_uartcfg *tcfg = cfg;
|
||||
u32 ucnt;
|
||||
|
|
@ -472,69 +659,138 @@ void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
|
|||
for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
|
||||
tcfg->has_fracval = 1;
|
||||
|
||||
s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
|
||||
if (soc_is_exynos5250())
|
||||
s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
|
||||
else
|
||||
s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
|
||||
}
|
||||
|
||||
static void __iomem *exynos_eint_base;
|
||||
|
||||
static DEFINE_SPINLOCK(eint_lock);
|
||||
|
||||
static unsigned int eint0_15_data[16];
|
||||
|
||||
static unsigned int exynos4_get_irq_nr(unsigned int number)
|
||||
static inline int exynos4_irq_to_gpio(unsigned int irq)
|
||||
{
|
||||
u32 ret = 0;
|
||||
if (irq < IRQ_EINT(0))
|
||||
return -EINVAL;
|
||||
|
||||
switch (number) {
|
||||
case 0 ... 3:
|
||||
ret = (number + IRQ_EINT0);
|
||||
break;
|
||||
case 4 ... 7:
|
||||
ret = (number + (IRQ_EINT4 - 4));
|
||||
break;
|
||||
case 8 ... 15:
|
||||
ret = (number + (IRQ_EINT8 - 8));
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "number available : %d\n", number);
|
||||
}
|
||||
irq -= IRQ_EINT(0);
|
||||
if (irq < 8)
|
||||
return EXYNOS4_GPX0(irq);
|
||||
|
||||
return ret;
|
||||
irq -= 8;
|
||||
if (irq < 8)
|
||||
return EXYNOS4_GPX1(irq);
|
||||
|
||||
irq -= 8;
|
||||
if (irq < 8)
|
||||
return EXYNOS4_GPX2(irq);
|
||||
|
||||
irq -= 8;
|
||||
if (irq < 8)
|
||||
return EXYNOS4_GPX3(irq);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline void exynos4_irq_eint_mask(struct irq_data *data)
|
||||
static inline int exynos5_irq_to_gpio(unsigned int irq)
|
||||
{
|
||||
if (irq < IRQ_EINT(0))
|
||||
return -EINVAL;
|
||||
|
||||
irq -= IRQ_EINT(0);
|
||||
if (irq < 8)
|
||||
return EXYNOS5_GPX0(irq);
|
||||
|
||||
irq -= 8;
|
||||
if (irq < 8)
|
||||
return EXYNOS5_GPX1(irq);
|
||||
|
||||
irq -= 8;
|
||||
if (irq < 8)
|
||||
return EXYNOS5_GPX2(irq);
|
||||
|
||||
irq -= 8;
|
||||
if (irq < 8)
|
||||
return EXYNOS5_GPX3(irq);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static unsigned int exynos4_eint0_15_src_int[16] = {
|
||||
EXYNOS4_IRQ_EINT0,
|
||||
EXYNOS4_IRQ_EINT1,
|
||||
EXYNOS4_IRQ_EINT2,
|
||||
EXYNOS4_IRQ_EINT3,
|
||||
EXYNOS4_IRQ_EINT4,
|
||||
EXYNOS4_IRQ_EINT5,
|
||||
EXYNOS4_IRQ_EINT6,
|
||||
EXYNOS4_IRQ_EINT7,
|
||||
EXYNOS4_IRQ_EINT8,
|
||||
EXYNOS4_IRQ_EINT9,
|
||||
EXYNOS4_IRQ_EINT10,
|
||||
EXYNOS4_IRQ_EINT11,
|
||||
EXYNOS4_IRQ_EINT12,
|
||||
EXYNOS4_IRQ_EINT13,
|
||||
EXYNOS4_IRQ_EINT14,
|
||||
EXYNOS4_IRQ_EINT15,
|
||||
};
|
||||
|
||||
static unsigned int exynos5_eint0_15_src_int[16] = {
|
||||
EXYNOS5_IRQ_EINT0,
|
||||
EXYNOS5_IRQ_EINT1,
|
||||
EXYNOS5_IRQ_EINT2,
|
||||
EXYNOS5_IRQ_EINT3,
|
||||
EXYNOS5_IRQ_EINT4,
|
||||
EXYNOS5_IRQ_EINT5,
|
||||
EXYNOS5_IRQ_EINT6,
|
||||
EXYNOS5_IRQ_EINT7,
|
||||
EXYNOS5_IRQ_EINT8,
|
||||
EXYNOS5_IRQ_EINT9,
|
||||
EXYNOS5_IRQ_EINT10,
|
||||
EXYNOS5_IRQ_EINT11,
|
||||
EXYNOS5_IRQ_EINT12,
|
||||
EXYNOS5_IRQ_EINT13,
|
||||
EXYNOS5_IRQ_EINT14,
|
||||
EXYNOS5_IRQ_EINT15,
|
||||
};
|
||||
static inline void exynos_irq_eint_mask(struct irq_data *data)
|
||||
{
|
||||
u32 mask;
|
||||
|
||||
spin_lock(&eint_lock);
|
||||
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
|
||||
mask |= eint_irq_to_bit(data->irq);
|
||||
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
|
||||
mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
|
||||
mask |= EINT_OFFSET_BIT(data->irq);
|
||||
__raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
|
||||
spin_unlock(&eint_lock);
|
||||
}
|
||||
|
||||
static void exynos4_irq_eint_unmask(struct irq_data *data)
|
||||
static void exynos_irq_eint_unmask(struct irq_data *data)
|
||||
{
|
||||
u32 mask;
|
||||
|
||||
spin_lock(&eint_lock);
|
||||
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
|
||||
mask &= ~(eint_irq_to_bit(data->irq));
|
||||
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
|
||||
mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
|
||||
mask &= ~(EINT_OFFSET_BIT(data->irq));
|
||||
__raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
|
||||
spin_unlock(&eint_lock);
|
||||
}
|
||||
|
||||
static inline void exynos4_irq_eint_ack(struct irq_data *data)
|
||||
static inline void exynos_irq_eint_ack(struct irq_data *data)
|
||||
{
|
||||
__raw_writel(eint_irq_to_bit(data->irq),
|
||||
S5P_EINT_PEND(EINT_REG_NR(data->irq)));
|
||||
__raw_writel(EINT_OFFSET_BIT(data->irq),
|
||||
EINT_PEND(exynos_eint_base, data->irq));
|
||||
}
|
||||
|
||||
static void exynos4_irq_eint_maskack(struct irq_data *data)
|
||||
static void exynos_irq_eint_maskack(struct irq_data *data)
|
||||
{
|
||||
exynos4_irq_eint_mask(data);
|
||||
exynos4_irq_eint_ack(data);
|
||||
exynos_irq_eint_mask(data);
|
||||
exynos_irq_eint_ack(data);
|
||||
}
|
||||
|
||||
static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
|
||||
static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
|
||||
{
|
||||
int offs = EINT_OFFSET(data->irq);
|
||||
int shift;
|
||||
|
|
@ -571,39 +827,27 @@ static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
|
|||
mask = 0x7 << shift;
|
||||
|
||||
spin_lock(&eint_lock);
|
||||
ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
|
||||
ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
|
||||
ctrl &= ~mask;
|
||||
ctrl |= newvalue << shift;
|
||||
__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
|
||||
__raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
|
||||
spin_unlock(&eint_lock);
|
||||
|
||||
switch (offs) {
|
||||
case 0 ... 7:
|
||||
s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
|
||||
break;
|
||||
case 8 ... 15:
|
||||
s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
|
||||
break;
|
||||
case 16 ... 23:
|
||||
s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
|
||||
break;
|
||||
case 24 ... 31:
|
||||
s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "No such irq number %d", offs);
|
||||
}
|
||||
if (soc_is_exynos5250())
|
||||
s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
|
||||
else
|
||||
s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_chip exynos4_irq_eint = {
|
||||
.name = "exynos4-eint",
|
||||
.irq_mask = exynos4_irq_eint_mask,
|
||||
.irq_unmask = exynos4_irq_eint_unmask,
|
||||
.irq_mask_ack = exynos4_irq_eint_maskack,
|
||||
.irq_ack = exynos4_irq_eint_ack,
|
||||
.irq_set_type = exynos4_irq_eint_set_type,
|
||||
static struct irq_chip exynos_irq_eint = {
|
||||
.name = "exynos-eint",
|
||||
.irq_mask = exynos_irq_eint_mask,
|
||||
.irq_unmask = exynos_irq_eint_unmask,
|
||||
.irq_mask_ack = exynos_irq_eint_maskack,
|
||||
.irq_ack = exynos_irq_eint_ack,
|
||||
.irq_set_type = exynos_irq_eint_set_type,
|
||||
#ifdef CONFIG_PM
|
||||
.irq_set_wake = s3c_irqext_wake,
|
||||
#endif
|
||||
|
|
@ -618,12 +862,12 @@ static struct irq_chip exynos4_irq_eint = {
|
|||
*
|
||||
* Each EINT pend/mask registers handle eight of them.
|
||||
*/
|
||||
static inline void exynos4_irq_demux_eint(unsigned int start)
|
||||
static inline void exynos_irq_demux_eint(unsigned int start)
|
||||
{
|
||||
unsigned int irq;
|
||||
|
||||
u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
|
||||
u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
|
||||
u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
|
||||
u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
|
||||
|
||||
status &= ~mask;
|
||||
status &= 0xff;
|
||||
|
|
@ -635,16 +879,16 @@ static inline void exynos4_irq_demux_eint(unsigned int start)
|
|||
}
|
||||
}
|
||||
|
||||
static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
|
||||
static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
struct irq_chip *chip = irq_get_chip(irq);
|
||||
chained_irq_enter(chip, desc);
|
||||
exynos4_irq_demux_eint(IRQ_EINT(16));
|
||||
exynos4_irq_demux_eint(IRQ_EINT(24));
|
||||
exynos_irq_demux_eint(IRQ_EINT(16));
|
||||
exynos_irq_demux_eint(IRQ_EINT(24));
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
|
||||
static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
u32 *irq_data = irq_get_handler_data(irq);
|
||||
struct irq_chip *chip = irq_get_chip(irq);
|
||||
|
|
@ -661,27 +905,44 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
|
|||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
int __init exynos4_init_irq_eint(void)
|
||||
static int __init exynos_init_irq_eint(void)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (soc_is_exynos5250())
|
||||
exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
|
||||
else
|
||||
exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
|
||||
|
||||
if (exynos_eint_base == NULL) {
|
||||
pr_err("unable to ioremap for EINT base address\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
for (irq = 0 ; irq <= 31 ; irq++) {
|
||||
irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
|
||||
irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
|
||||
handle_level_irq);
|
||||
set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
|
||||
}
|
||||
|
||||
irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
|
||||
irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
|
||||
|
||||
for (irq = 0 ; irq <= 15 ; irq++) {
|
||||
eint0_15_data[irq] = IRQ_EINT(irq);
|
||||
|
||||
irq_set_handler_data(exynos4_get_irq_nr(irq),
|
||||
&eint0_15_data[irq]);
|
||||
irq_set_chained_handler(exynos4_get_irq_nr(irq),
|
||||
exynos4_irq_eint0_15);
|
||||
if (soc_is_exynos5250()) {
|
||||
irq_set_handler_data(exynos5_eint0_15_src_int[irq],
|
||||
&eint0_15_data[irq]);
|
||||
irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
|
||||
exynos_irq_eint0_15);
|
||||
} else {
|
||||
irq_set_handler_data(exynos4_eint0_15_src_int[irq],
|
||||
&eint0_15_data[irq]);
|
||||
irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
|
||||
exynos_irq_eint0_15);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(exynos4_init_irq_eint);
|
||||
arch_initcall(exynos_init_irq_eint);
|
||||
|
|
|
|||
|
|
@ -12,30 +12,44 @@
|
|||
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
||||
#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
||||
|
||||
extern struct sys_timer exynos4_timer;
|
||||
|
||||
void exynos_init_io(struct map_desc *mach_desc, int size);
|
||||
void exynos4_init_irq(void);
|
||||
void exynos5_init_irq(void);
|
||||
void exynos4_restart(char mode, const char *cmd);
|
||||
void exynos5_restart(char mode, const char *cmd);
|
||||
|
||||
#ifdef CONFIG_ARCH_EXYNOS4
|
||||
void exynos4_register_clocks(void);
|
||||
void exynos4_setup_clocks(void);
|
||||
|
||||
void exynos4210_register_clocks(void);
|
||||
void exynos4212_register_clocks(void);
|
||||
#else
|
||||
#define exynos4_register_clocks()
|
||||
#define exynos4_setup_clocks()
|
||||
#endif
|
||||
|
||||
void exynos4_restart(char mode, const char *cmd);
|
||||
|
||||
extern struct sys_timer exynos4_timer;
|
||||
|
||||
#ifdef CONFIG_ARCH_EXYNOS
|
||||
extern int exynos_init(void);
|
||||
extern void exynos4_map_io(void);
|
||||
extern void exynos4_init_clocks(int xtal);
|
||||
extern void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
#ifdef CONFIG_ARCH_EXYNOS5
|
||||
void exynos5_register_clocks(void);
|
||||
void exynos5_setup_clocks(void);
|
||||
|
||||
#else
|
||||
#define exynos4_init_clocks NULL
|
||||
#define exynos4_init_uarts NULL
|
||||
#define exynos4_map_io NULL
|
||||
#define exynos_init NULL
|
||||
#define exynos5_register_clocks()
|
||||
#define exynos5_setup_clocks()
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_EXYNOS4210
|
||||
void exynos4210_register_clocks(void);
|
||||
|
||||
#else
|
||||
#define exynos4210_register_clocks()
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_EXYNOS4212
|
||||
void exynos4212_register_clocks(void);
|
||||
|
||||
#else
|
||||
#define exynos4212_register_clocks()
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
|
||||
|
|
|
|||
|
|
@ -242,8 +242,8 @@ static struct resource exynos4_ahci_resource[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_SATA,
|
||||
.end = IRQ_SATA,
|
||||
.start = EXYNOS4_IRQ_SATA,
|
||||
.end = EXYNOS4_IRQ_SATA,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -304,8 +304,8 @@ static struct resource exynos4_ac97_resource[] = {
|
|||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[4] = {
|
||||
.start = IRQ_AC97,
|
||||
.end = IRQ_AC97,
|
||||
.start = EXYNOS4_IRQ_AC97,
|
||||
.end = EXYNOS4_IRQ_AC97,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Base EXYNOS UART resource and device definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/devs.h>
|
||||
|
||||
#define EXYNOS_UART_RESOURCE(_series, _nr) \
|
||||
static struct resource exynos##_series##_uart##_nr##_resource[] = { \
|
||||
[0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART), \
|
||||
[1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr), \
|
||||
};
|
||||
|
||||
EXYNOS_UART_RESOURCE(4, 0)
|
||||
EXYNOS_UART_RESOURCE(4, 1)
|
||||
EXYNOS_UART_RESOURCE(4, 2)
|
||||
EXYNOS_UART_RESOURCE(4, 3)
|
||||
|
||||
struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
|
||||
[0] = {
|
||||
.resources = exynos4_uart0_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos4_uart0_resource),
|
||||
},
|
||||
[1] = {
|
||||
.resources = exynos4_uart1_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos4_uart1_resource),
|
||||
},
|
||||
[2] = {
|
||||
.resources = exynos4_uart2_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos4_uart2_resource),
|
||||
},
|
||||
[3] = {
|
||||
.resources = exynos4_uart3_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos4_uart3_resource),
|
||||
},
|
||||
};
|
||||
|
||||
EXYNOS_UART_RESOURCE(5, 0)
|
||||
EXYNOS_UART_RESOURCE(5, 1)
|
||||
EXYNOS_UART_RESOURCE(5, 2)
|
||||
EXYNOS_UART_RESOURCE(5, 3)
|
||||
|
||||
struct s3c24xx_uart_resources exynos5_uart_resources[] __initdata = {
|
||||
[0] = {
|
||||
.resources = exynos5_uart0_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
|
||||
},
|
||||
[1] = {
|
||||
.resources = exynos5_uart1_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
|
||||
},
|
||||
[2] = {
|
||||
.resources = exynos5_uart2_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos5_uart2_resource),
|
||||
},
|
||||
[3] = {
|
||||
.resources = exynos5_uart3_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos5_uart3_resource),
|
||||
},
|
||||
};
|
||||
|
|
@ -29,6 +29,7 @@
|
|||
#include <asm/irq.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/irqs.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/irqs.h>
|
||||
|
|
@ -36,7 +37,7 @@
|
|||
|
||||
static u64 dma_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
u8 pdma0_peri[] = {
|
||||
static u8 exynos4210_pdma0_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM2_RX,
|
||||
|
|
@ -69,15 +70,47 @@ u8 pdma0_peri[] = {
|
|||
DMACH_AC97_PCMOUT,
|
||||
};
|
||||
|
||||
struct dma_pl330_platdata exynos4_pdma0_pdata = {
|
||||
.nr_valid_peri = ARRAY_SIZE(pdma0_peri),
|
||||
.peri_id = pdma0_peri,
|
||||
static u8 exynos4212_pdma0_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM2_RX,
|
||||
DMACH_PCM2_TX,
|
||||
DMACH_MIPI_HSI0,
|
||||
DMACH_MIPI_HSI1,
|
||||
DMACH_SPI0_RX,
|
||||
DMACH_SPI0_TX,
|
||||
DMACH_SPI2_RX,
|
||||
DMACH_SPI2_TX,
|
||||
DMACH_I2S0S_TX,
|
||||
DMACH_I2S0_RX,
|
||||
DMACH_I2S0_TX,
|
||||
DMACH_I2S2_RX,
|
||||
DMACH_I2S2_TX,
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART2_RX,
|
||||
DMACH_UART2_TX,
|
||||
DMACH_UART4_RX,
|
||||
DMACH_UART4_TX,
|
||||
DMACH_SLIMBUS0_RX,
|
||||
DMACH_SLIMBUS0_TX,
|
||||
DMACH_SLIMBUS2_RX,
|
||||
DMACH_SLIMBUS2_TX,
|
||||
DMACH_SLIMBUS4_RX,
|
||||
DMACH_SLIMBUS4_TX,
|
||||
DMACH_AC97_MICIN,
|
||||
DMACH_AC97_PCMIN,
|
||||
DMACH_AC97_PCMOUT,
|
||||
DMACH_MIPI_HSI4,
|
||||
DMACH_MIPI_HSI5,
|
||||
};
|
||||
|
||||
AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, EXYNOS4_PA_PDMA0,
|
||||
{IRQ_PDMA0}, &exynos4_pdma0_pdata);
|
||||
struct dma_pl330_platdata exynos4_pdma0_pdata;
|
||||
|
||||
u8 pdma1_peri[] = {
|
||||
static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
|
||||
EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata);
|
||||
|
||||
static u8 exynos4210_pdma1_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM1_RX,
|
||||
|
|
@ -105,19 +138,84 @@ u8 pdma1_peri[] = {
|
|||
DMACH_SLIMBUS5_TX,
|
||||
};
|
||||
|
||||
struct dma_pl330_platdata exynos4_pdma1_pdata = {
|
||||
.nr_valid_peri = ARRAY_SIZE(pdma1_peri),
|
||||
.peri_id = pdma1_peri,
|
||||
static u8 exynos4212_pdma1_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM1_RX,
|
||||
DMACH_PCM1_TX,
|
||||
DMACH_MIPI_HSI2,
|
||||
DMACH_MIPI_HSI3,
|
||||
DMACH_SPI1_RX,
|
||||
DMACH_SPI1_TX,
|
||||
DMACH_I2S0S_TX,
|
||||
DMACH_I2S0_RX,
|
||||
DMACH_I2S0_TX,
|
||||
DMACH_I2S1_RX,
|
||||
DMACH_I2S1_TX,
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART1_RX,
|
||||
DMACH_UART1_TX,
|
||||
DMACH_UART3_RX,
|
||||
DMACH_UART3_TX,
|
||||
DMACH_SLIMBUS1_RX,
|
||||
DMACH_SLIMBUS1_TX,
|
||||
DMACH_SLIMBUS3_RX,
|
||||
DMACH_SLIMBUS3_TX,
|
||||
DMACH_SLIMBUS5_RX,
|
||||
DMACH_SLIMBUS5_TX,
|
||||
DMACH_SLIMBUS0AUX_RX,
|
||||
DMACH_SLIMBUS0AUX_TX,
|
||||
DMACH_SPDIF,
|
||||
DMACH_MIPI_HSI6,
|
||||
DMACH_MIPI_HSI7,
|
||||
};
|
||||
|
||||
AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, EXYNOS4_PA_PDMA1,
|
||||
{IRQ_PDMA1}, &exynos4_pdma1_pdata);
|
||||
static struct dma_pl330_platdata exynos4_pdma1_pdata;
|
||||
|
||||
static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330,
|
||||
EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata);
|
||||
|
||||
static u8 mdma_peri[] = {
|
||||
DMACH_MTOM_0,
|
||||
DMACH_MTOM_1,
|
||||
DMACH_MTOM_2,
|
||||
DMACH_MTOM_3,
|
||||
DMACH_MTOM_4,
|
||||
DMACH_MTOM_5,
|
||||
DMACH_MTOM_6,
|
||||
DMACH_MTOM_7,
|
||||
};
|
||||
|
||||
static struct dma_pl330_platdata exynos4_mdma1_pdata = {
|
||||
.nr_valid_peri = ARRAY_SIZE(mdma_peri),
|
||||
.peri_id = mdma_peri,
|
||||
};
|
||||
|
||||
static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330,
|
||||
EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata);
|
||||
|
||||
static int __init exynos4_dma_init(void)
|
||||
{
|
||||
if (of_have_populated_dt())
|
||||
return 0;
|
||||
|
||||
if (soc_is_exynos4210()) {
|
||||
exynos4_pdma0_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos4210_pdma0_peri);
|
||||
exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
|
||||
exynos4_pdma1_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos4210_pdma1_peri);
|
||||
exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
|
||||
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
|
||||
exynos4_pdma0_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos4212_pdma0_peri);
|
||||
exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
|
||||
exynos4_pdma1_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos4212_pdma1_peri);
|
||||
exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
|
||||
}
|
||||
|
||||
dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
|
||||
dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
|
||||
amba_device_register(&exynos4_pdma0_device, &iomem_resource);
|
||||
|
|
@ -126,6 +224,9 @@ static int __init exynos4_dma_init(void)
|
|||
dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
|
||||
amba_device_register(&exynos4_pdma1_device, &iomem_resource);
|
||||
|
||||
dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);
|
||||
amba_device_register(&exynos4_mdma1_device, &iomem_resource);
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(exynos4_dma_init);
|
||||
|
|
|
|||
|
|
@ -21,8 +21,13 @@
|
|||
*/
|
||||
|
||||
.macro addruart, rp, rv, tmp
|
||||
ldr \rp, = S3C_PA_UART
|
||||
ldr \rv, = S3C_VA_UART
|
||||
mov \rp, #0x10000000
|
||||
ldr \rp, [\rp, #0x0]
|
||||
and \rp, \rp, #0xf00000
|
||||
teq \rp, #0x500000 @@ EXYNOS5
|
||||
ldreq \rp, =EXYNOS5_PA_UART
|
||||
movne \rp, #EXYNOS4_PA_UART @@ EXYNOS4
|
||||
ldr \rv, =S3C_VA_UART
|
||||
#if CONFIG_DEBUG_S3C_UART != 0
|
||||
add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
|
||||
add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
|
||||
|
|
|
|||
|
|
@ -1,43 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Header file for exynos4 clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H __FILE__
|
||||
|
||||
#include <linux/clk.h>
|
||||
|
||||
extern struct clk clk_sclk_hdmi27m;
|
||||
extern struct clk clk_sclk_usbphy0;
|
||||
extern struct clk clk_sclk_usbphy1;
|
||||
extern struct clk clk_sclk_hdmiphy;
|
||||
|
||||
extern struct clksrc_clk clk_sclk_apll;
|
||||
extern struct clksrc_clk clk_mout_mpll;
|
||||
extern struct clksrc_clk clk_aclk_133;
|
||||
extern struct clksrc_clk clk_mout_epll;
|
||||
extern struct clksrc_clk clk_sclk_vpll;
|
||||
|
||||
extern struct clk *clkset_corebus_list[];
|
||||
extern struct clksrc_sources clkset_mout_corebus;
|
||||
|
||||
extern struct clk *clkset_aclk_top_list[];
|
||||
extern struct clksrc_sources clkset_aclk;
|
||||
|
||||
extern struct clk *clkset_group_list[];
|
||||
extern struct clksrc_sources clkset_group;
|
||||
|
||||
extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
|
||||
|
||||
#endif /* __ASM_ARCH_CLOCK_H */
|
||||
|
|
@ -1,9 +1,8 @@
|
|||
/* linux/arch/arm/mach-exynos4/include/mach/irqs.h
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
/*
|
||||
* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4 - IRQ definitions
|
||||
* EXYNOS - IRQ definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
|
@ -17,158 +16,450 @@
|
|||
|
||||
/* PPI: Private Peripheral Interrupt */
|
||||
|
||||
#define IRQ_PPI(x) (x+16)
|
||||
|
||||
#define IRQ_MCT_LOCALTIMER IRQ_PPI(12)
|
||||
#define IRQ_PPI(x) (x + 16)
|
||||
|
||||
/* SPI: Shared Peripheral Interrupt */
|
||||
|
||||
#define IRQ_SPI(x) (x+32)
|
||||
#define IRQ_SPI(x) (x + 32)
|
||||
|
||||
#define IRQ_EINT0 IRQ_SPI(16)
|
||||
#define IRQ_EINT1 IRQ_SPI(17)
|
||||
#define IRQ_EINT2 IRQ_SPI(18)
|
||||
#define IRQ_EINT3 IRQ_SPI(19)
|
||||
#define IRQ_EINT4 IRQ_SPI(20)
|
||||
#define IRQ_EINT5 IRQ_SPI(21)
|
||||
#define IRQ_EINT6 IRQ_SPI(22)
|
||||
#define IRQ_EINT7 IRQ_SPI(23)
|
||||
#define IRQ_EINT8 IRQ_SPI(24)
|
||||
#define IRQ_EINT9 IRQ_SPI(25)
|
||||
#define IRQ_EINT10 IRQ_SPI(26)
|
||||
#define IRQ_EINT11 IRQ_SPI(27)
|
||||
#define IRQ_EINT12 IRQ_SPI(28)
|
||||
#define IRQ_EINT13 IRQ_SPI(29)
|
||||
#define IRQ_EINT14 IRQ_SPI(30)
|
||||
#define IRQ_EINT15 IRQ_SPI(31)
|
||||
#define IRQ_EINT16_31 IRQ_SPI(32)
|
||||
/* COMBINER */
|
||||
|
||||
#define IRQ_PDMA0 IRQ_SPI(35)
|
||||
#define IRQ_PDMA1 IRQ_SPI(36)
|
||||
#define IRQ_TIMER0_VIC IRQ_SPI(37)
|
||||
#define IRQ_TIMER1_VIC IRQ_SPI(38)
|
||||
#define IRQ_TIMER2_VIC IRQ_SPI(39)
|
||||
#define IRQ_TIMER3_VIC IRQ_SPI(40)
|
||||
#define IRQ_TIMER4_VIC IRQ_SPI(41)
|
||||
#define IRQ_MCT_L0 IRQ_SPI(42)
|
||||
#define IRQ_WDT IRQ_SPI(43)
|
||||
#define IRQ_RTC_ALARM IRQ_SPI(44)
|
||||
#define IRQ_RTC_TIC IRQ_SPI(45)
|
||||
#define IRQ_GPIO_XB IRQ_SPI(46)
|
||||
#define IRQ_GPIO_XA IRQ_SPI(47)
|
||||
#define IRQ_MCT_L1 IRQ_SPI(48)
|
||||
#define MAX_IRQ_IN_COMBINER 8
|
||||
#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
|
||||
#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
|
||||
|
||||
#define IRQ_UART0 IRQ_SPI(52)
|
||||
#define IRQ_UART1 IRQ_SPI(53)
|
||||
#define IRQ_UART2 IRQ_SPI(54)
|
||||
#define IRQ_UART3 IRQ_SPI(55)
|
||||
#define IRQ_UART4 IRQ_SPI(56)
|
||||
#define IRQ_MCT_G0 IRQ_SPI(57)
|
||||
#define IRQ_IIC IRQ_SPI(58)
|
||||
#define IRQ_IIC1 IRQ_SPI(59)
|
||||
#define IRQ_IIC2 IRQ_SPI(60)
|
||||
#define IRQ_IIC3 IRQ_SPI(61)
|
||||
#define IRQ_IIC4 IRQ_SPI(62)
|
||||
#define IRQ_IIC5 IRQ_SPI(63)
|
||||
#define IRQ_IIC6 IRQ_SPI(64)
|
||||
#define IRQ_IIC7 IRQ_SPI(65)
|
||||
#define IRQ_SPI0 IRQ_SPI(66)
|
||||
#define IRQ_SPI1 IRQ_SPI(67)
|
||||
#define IRQ_SPI2 IRQ_SPI(68)
|
||||
/* For EXYNOS4 and EXYNOS5 */
|
||||
|
||||
#define IRQ_USB_HOST IRQ_SPI(70)
|
||||
#define IRQ_USB_HSOTG IRQ_SPI(71)
|
||||
#define IRQ_MODEM_IF IRQ_SPI(72)
|
||||
#define IRQ_HSMMC0 IRQ_SPI(73)
|
||||
#define IRQ_HSMMC1 IRQ_SPI(74)
|
||||
#define IRQ_HSMMC2 IRQ_SPI(75)
|
||||
#define IRQ_HSMMC3 IRQ_SPI(76)
|
||||
#define IRQ_DWMCI IRQ_SPI(77)
|
||||
#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12)
|
||||
|
||||
#define IRQ_MIPI_CSIS0 IRQ_SPI(78)
|
||||
#define IRQ_MIPI_CSIS1 IRQ_SPI(80)
|
||||
#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
|
||||
|
||||
#define IRQ_ONENAND_AUDI IRQ_SPI(82)
|
||||
#define IRQ_ROTATOR IRQ_SPI(83)
|
||||
#define IRQ_FIMC0 IRQ_SPI(84)
|
||||
#define IRQ_FIMC1 IRQ_SPI(85)
|
||||
#define IRQ_FIMC2 IRQ_SPI(86)
|
||||
#define IRQ_FIMC3 IRQ_SPI(87)
|
||||
#define IRQ_JPEG IRQ_SPI(88)
|
||||
#define IRQ_2D IRQ_SPI(89)
|
||||
#define IRQ_PCIE IRQ_SPI(90)
|
||||
/* For EXYNOS4 SoCs */
|
||||
|
||||
#define IRQ_MIXER IRQ_SPI(91)
|
||||
#define IRQ_HDMI IRQ_SPI(92)
|
||||
#define IRQ_IIC_HDMIPHY IRQ_SPI(93)
|
||||
#define IRQ_MFC IRQ_SPI(94)
|
||||
#define IRQ_SDO IRQ_SPI(95)
|
||||
#define EXYNOS4_IRQ_EINT0 IRQ_SPI(16)
|
||||
#define EXYNOS4_IRQ_EINT1 IRQ_SPI(17)
|
||||
#define EXYNOS4_IRQ_EINT2 IRQ_SPI(18)
|
||||
#define EXYNOS4_IRQ_EINT3 IRQ_SPI(19)
|
||||
#define EXYNOS4_IRQ_EINT4 IRQ_SPI(20)
|
||||
#define EXYNOS4_IRQ_EINT5 IRQ_SPI(21)
|
||||
#define EXYNOS4_IRQ_EINT6 IRQ_SPI(22)
|
||||
#define EXYNOS4_IRQ_EINT7 IRQ_SPI(23)
|
||||
#define EXYNOS4_IRQ_EINT8 IRQ_SPI(24)
|
||||
#define EXYNOS4_IRQ_EINT9 IRQ_SPI(25)
|
||||
#define EXYNOS4_IRQ_EINT10 IRQ_SPI(26)
|
||||
#define EXYNOS4_IRQ_EINT11 IRQ_SPI(27)
|
||||
#define EXYNOS4_IRQ_EINT12 IRQ_SPI(28)
|
||||
#define EXYNOS4_IRQ_EINT13 IRQ_SPI(29)
|
||||
#define EXYNOS4_IRQ_EINT14 IRQ_SPI(30)
|
||||
#define EXYNOS4_IRQ_EINT15 IRQ_SPI(31)
|
||||
|
||||
#define IRQ_AUDIO_SS IRQ_SPI(96)
|
||||
#define IRQ_I2S0 IRQ_SPI(97)
|
||||
#define IRQ_I2S1 IRQ_SPI(98)
|
||||
#define IRQ_I2S2 IRQ_SPI(99)
|
||||
#define IRQ_AC97 IRQ_SPI(100)
|
||||
#define EXYNOS4_IRQ_MDMA0 IRQ_SPI(33)
|
||||
#define EXYNOS4_IRQ_MDMA1 IRQ_SPI(34)
|
||||
#define EXYNOS4_IRQ_PDMA0 IRQ_SPI(35)
|
||||
#define EXYNOS4_IRQ_PDMA1 IRQ_SPI(36)
|
||||
#define EXYNOS4_IRQ_TIMER0_VIC IRQ_SPI(37)
|
||||
#define EXYNOS4_IRQ_TIMER1_VIC IRQ_SPI(38)
|
||||
#define EXYNOS4_IRQ_TIMER2_VIC IRQ_SPI(39)
|
||||
#define EXYNOS4_IRQ_TIMER3_VIC IRQ_SPI(40)
|
||||
#define EXYNOS4_IRQ_TIMER4_VIC IRQ_SPI(41)
|
||||
#define EXYNOS4_IRQ_MCT_L0 IRQ_SPI(42)
|
||||
#define EXYNOS4_IRQ_WDT IRQ_SPI(43)
|
||||
#define EXYNOS4_IRQ_RTC_ALARM IRQ_SPI(44)
|
||||
#define EXYNOS4_IRQ_RTC_TIC IRQ_SPI(45)
|
||||
#define EXYNOS4_IRQ_GPIO_XB IRQ_SPI(46)
|
||||
#define EXYNOS4_IRQ_GPIO_XA IRQ_SPI(47)
|
||||
#define EXYNOS4_IRQ_MCT_L1 IRQ_SPI(48)
|
||||
|
||||
#define IRQ_SPDIF IRQ_SPI(104)
|
||||
#define IRQ_ADC0 IRQ_SPI(105)
|
||||
#define IRQ_PEN0 IRQ_SPI(106)
|
||||
#define IRQ_ADC1 IRQ_SPI(107)
|
||||
#define IRQ_PEN1 IRQ_SPI(108)
|
||||
#define IRQ_KEYPAD IRQ_SPI(109)
|
||||
#define IRQ_PMU IRQ_SPI(110)
|
||||
#define IRQ_GPS IRQ_SPI(111)
|
||||
#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
|
||||
#define IRQ_SLIMBUS IRQ_SPI(113)
|
||||
#define EXYNOS4_IRQ_UART0 IRQ_SPI(52)
|
||||
#define EXYNOS4_IRQ_UART1 IRQ_SPI(53)
|
||||
#define EXYNOS4_IRQ_UART2 IRQ_SPI(54)
|
||||
#define EXYNOS4_IRQ_UART3 IRQ_SPI(55)
|
||||
#define EXYNOS4_IRQ_UART4 IRQ_SPI(56)
|
||||
#define EXYNOS4_IRQ_MCT_G0 IRQ_SPI(57)
|
||||
#define EXYNOS4_IRQ_IIC IRQ_SPI(58)
|
||||
#define EXYNOS4_IRQ_IIC1 IRQ_SPI(59)
|
||||
#define EXYNOS4_IRQ_IIC2 IRQ_SPI(60)
|
||||
#define EXYNOS4_IRQ_IIC3 IRQ_SPI(61)
|
||||
#define EXYNOS4_IRQ_IIC4 IRQ_SPI(62)
|
||||
#define EXYNOS4_IRQ_IIC5 IRQ_SPI(63)
|
||||
#define EXYNOS4_IRQ_IIC6 IRQ_SPI(64)
|
||||
#define EXYNOS4_IRQ_IIC7 IRQ_SPI(65)
|
||||
#define EXYNOS4_IRQ_SPI0 IRQ_SPI(66)
|
||||
#define EXYNOS4_IRQ_SPI1 IRQ_SPI(67)
|
||||
#define EXYNOS4_IRQ_SPI2 IRQ_SPI(68)
|
||||
|
||||
#define IRQ_TSI IRQ_SPI(115)
|
||||
#define IRQ_SATA IRQ_SPI(116)
|
||||
#define EXYNOS4_IRQ_USB_HOST IRQ_SPI(70)
|
||||
#define EXYNOS4_IRQ_USB_HSOTG IRQ_SPI(71)
|
||||
#define EXYNOS4_IRQ_MODEM_IF IRQ_SPI(72)
|
||||
#define EXYNOS4_IRQ_HSMMC0 IRQ_SPI(73)
|
||||
#define EXYNOS4_IRQ_HSMMC1 IRQ_SPI(74)
|
||||
#define EXYNOS4_IRQ_HSMMC2 IRQ_SPI(75)
|
||||
#define EXYNOS4_IRQ_HSMMC3 IRQ_SPI(76)
|
||||
#define EXYNOS4_IRQ_DWMCI IRQ_SPI(77)
|
||||
|
||||
#define MAX_IRQ_IN_COMBINER 8
|
||||
#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
|
||||
#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
|
||||
#define EXYNOS4_IRQ_MIPI_CSIS0 IRQ_SPI(78)
|
||||
#define EXYNOS4_IRQ_MIPI_CSIS1 IRQ_SPI(80)
|
||||
|
||||
#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
|
||||
#define IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
|
||||
#define IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
|
||||
#define IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3)
|
||||
#define IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4)
|
||||
#define IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5)
|
||||
#define IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6)
|
||||
#define IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7)
|
||||
#define EXYNOS4_IRQ_ONENAND_AUDI IRQ_SPI(82)
|
||||
#define EXYNOS4_IRQ_ROTATOR IRQ_SPI(83)
|
||||
#define EXYNOS4_IRQ_FIMC0 IRQ_SPI(84)
|
||||
#define EXYNOS4_IRQ_FIMC1 IRQ_SPI(85)
|
||||
#define EXYNOS4_IRQ_FIMC2 IRQ_SPI(86)
|
||||
#define EXYNOS4_IRQ_FIMC3 IRQ_SPI(87)
|
||||
#define EXYNOS4_IRQ_JPEG IRQ_SPI(88)
|
||||
#define EXYNOS4_IRQ_2D IRQ_SPI(89)
|
||||
#define EXYNOS4_IRQ_PCIE IRQ_SPI(90)
|
||||
|
||||
#define IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0)
|
||||
#define IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1)
|
||||
#define IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2)
|
||||
#define IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3)
|
||||
#define IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4)
|
||||
#define IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5)
|
||||
#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
|
||||
#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
|
||||
#define EXYNOS4_IRQ_MIXER IRQ_SPI(91)
|
||||
#define EXYNOS4_IRQ_HDMI IRQ_SPI(92)
|
||||
#define EXYNOS4_IRQ_IIC_HDMIPHY IRQ_SPI(93)
|
||||
#define EXYNOS4_IRQ_MFC IRQ_SPI(94)
|
||||
#define EXYNOS4_IRQ_SDO IRQ_SPI(95)
|
||||
|
||||
#define IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
|
||||
#define IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
|
||||
#define IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
|
||||
#define EXYNOS4_IRQ_AUDIO_SS IRQ_SPI(96)
|
||||
#define EXYNOS4_IRQ_I2S0 IRQ_SPI(97)
|
||||
#define EXYNOS4_IRQ_I2S1 IRQ_SPI(98)
|
||||
#define EXYNOS4_IRQ_I2S2 IRQ_SPI(99)
|
||||
#define EXYNOS4_IRQ_AC97 IRQ_SPI(100)
|
||||
|
||||
#define MAX_COMBINER_NR 16
|
||||
#define EXYNOS4_IRQ_SPDIF IRQ_SPI(104)
|
||||
#define EXYNOS4_IRQ_ADC0 IRQ_SPI(105)
|
||||
#define EXYNOS4_IRQ_PEN0 IRQ_SPI(106)
|
||||
#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
|
||||
#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
|
||||
#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
|
||||
#define EXYNOS4_IRQ_PMU IRQ_SPI(110)
|
||||
#define EXYNOS4_IRQ_GPS IRQ_SPI(111)
|
||||
#define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
|
||||
#define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113)
|
||||
|
||||
#define IRQ_ADC IRQ_ADC0
|
||||
#define IRQ_TC IRQ_PEN0
|
||||
#define EXYNOS4_IRQ_TSI IRQ_SPI(115)
|
||||
#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
|
||||
|
||||
#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0)
|
||||
#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
|
||||
#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
|
||||
#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
|
||||
#define EXYNOS4_IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3)
|
||||
#define EXYNOS4_IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4)
|
||||
#define EXYNOS4_IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5)
|
||||
#define EXYNOS4_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6)
|
||||
#define EXYNOS4_IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7)
|
||||
|
||||
#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0)
|
||||
#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE + 16)
|
||||
#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0)
|
||||
#define EXYNOS4_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1)
|
||||
#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2)
|
||||
#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3)
|
||||
#define EXYNOS4_IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4)
|
||||
#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5)
|
||||
#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
|
||||
#define EXYNOS4_IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
|
||||
|
||||
/* optional GPIO interrupts */
|
||||
#define S5P_GPIOINT_BASE (S5P_IRQ_EINT_BASE + 32)
|
||||
#define IRQ_GPIO1_NR_GROUPS 16
|
||||
#define IRQ_GPIO2_NR_GROUPS 9
|
||||
#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
|
||||
#define EXYNOS4_IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
|
||||
#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
|
||||
#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
|
||||
|
||||
#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
|
||||
#define EXYNOS4_MAX_COMBINER_NR 16
|
||||
|
||||
#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16
|
||||
#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9
|
||||
|
||||
/*
|
||||
* For Compatibility:
|
||||
* the default is for EXYNOS4, and
|
||||
* for exynos5, should be re-mapped at function
|
||||
*/
|
||||
|
||||
#define IRQ_TIMER0_VIC EXYNOS4_IRQ_TIMER0_VIC
|
||||
#define IRQ_TIMER1_VIC EXYNOS4_IRQ_TIMER1_VIC
|
||||
#define IRQ_TIMER2_VIC EXYNOS4_IRQ_TIMER2_VIC
|
||||
#define IRQ_TIMER3_VIC EXYNOS4_IRQ_TIMER3_VIC
|
||||
#define IRQ_TIMER4_VIC EXYNOS4_IRQ_TIMER4_VIC
|
||||
|
||||
#define IRQ_WDT EXYNOS4_IRQ_WDT
|
||||
#define IRQ_RTC_ALARM EXYNOS4_IRQ_RTC_ALARM
|
||||
#define IRQ_RTC_TIC EXYNOS4_IRQ_RTC_TIC
|
||||
#define IRQ_GPIO_XB EXYNOS4_IRQ_GPIO_XB
|
||||
#define IRQ_GPIO_XA EXYNOS4_IRQ_GPIO_XA
|
||||
|
||||
#define IRQ_IIC EXYNOS4_IRQ_IIC
|
||||
#define IRQ_IIC1 EXYNOS4_IRQ_IIC1
|
||||
#define IRQ_IIC3 EXYNOS4_IRQ_IIC3
|
||||
#define IRQ_IIC5 EXYNOS4_IRQ_IIC5
|
||||
#define IRQ_IIC6 EXYNOS4_IRQ_IIC6
|
||||
#define IRQ_IIC7 EXYNOS4_IRQ_IIC7
|
||||
|
||||
#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST
|
||||
|
||||
#define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0
|
||||
#define IRQ_HSMMC1 EXYNOS4_IRQ_HSMMC1
|
||||
#define IRQ_HSMMC2 EXYNOS4_IRQ_HSMMC2
|
||||
#define IRQ_HSMMC3 EXYNOS4_IRQ_HSMMC3
|
||||
|
||||
#define IRQ_MIPI_CSIS0 EXYNOS4_IRQ_MIPI_CSIS0
|
||||
|
||||
#define IRQ_ONENAND_AUDI EXYNOS4_IRQ_ONENAND_AUDI
|
||||
|
||||
#define IRQ_FIMC0 EXYNOS4_IRQ_FIMC0
|
||||
#define IRQ_FIMC1 EXYNOS4_IRQ_FIMC1
|
||||
#define IRQ_FIMC2 EXYNOS4_IRQ_FIMC2
|
||||
#define IRQ_FIMC3 EXYNOS4_IRQ_FIMC3
|
||||
#define IRQ_JPEG EXYNOS4_IRQ_JPEG
|
||||
#define IRQ_2D EXYNOS4_IRQ_2D
|
||||
|
||||
#define IRQ_MIXER EXYNOS4_IRQ_MIXER
|
||||
#define IRQ_HDMI EXYNOS4_IRQ_HDMI
|
||||
#define IRQ_IIC_HDMIPHY EXYNOS4_IRQ_IIC_HDMIPHY
|
||||
#define IRQ_MFC EXYNOS4_IRQ_MFC
|
||||
#define IRQ_SDO EXYNOS4_IRQ_SDO
|
||||
|
||||
#define IRQ_ADC EXYNOS4_IRQ_ADC0
|
||||
#define IRQ_TC EXYNOS4_IRQ_PEN0
|
||||
|
||||
#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
|
||||
#define IRQ_PMU EXYNOS4_IRQ_PMU
|
||||
|
||||
#define IRQ_SYSMMU_MDMA0_0 EXYNOS4_IRQ_SYSMMU_MDMA0_0
|
||||
#define IRQ_SYSMMU_SSS_0 EXYNOS4_IRQ_SYSMMU_SSS_0
|
||||
#define IRQ_SYSMMU_FIMC0_0 EXYNOS4_IRQ_SYSMMU_FIMC0_0
|
||||
#define IRQ_SYSMMU_FIMC1_0 EXYNOS4_IRQ_SYSMMU_FIMC1_0
|
||||
#define IRQ_SYSMMU_FIMC2_0 EXYNOS4_IRQ_SYSMMU_FIMC2_0
|
||||
#define IRQ_SYSMMU_FIMC3_0 EXYNOS4_IRQ_SYSMMU_FIMC3_0
|
||||
#define IRQ_SYSMMU_JPEG_0 EXYNOS4_IRQ_SYSMMU_JPEG_0
|
||||
#define IRQ_SYSMMU_2D_0 EXYNOS4_IRQ_SYSMMU_2D_0
|
||||
|
||||
#define IRQ_SYSMMU_ROTATOR_0 EXYNOS4_IRQ_SYSMMU_ROTATOR_0
|
||||
#define IRQ_SYSMMU_MDMA1_0 EXYNOS4_IRQ_SYSMMU_MDMA1_0
|
||||
#define IRQ_SYSMMU_LCD0_M0_0 EXYNOS4_IRQ_SYSMMU_LCD0_M0_0
|
||||
#define IRQ_SYSMMU_LCD1_M1_0 EXYNOS4_IRQ_SYSMMU_LCD1_M1_0
|
||||
#define IRQ_SYSMMU_TV_M0_0 EXYNOS4_IRQ_SYSMMU_TV_M0_0
|
||||
#define IRQ_SYSMMU_MFC_M0_0 EXYNOS4_IRQ_SYSMMU_MFC_M0_0
|
||||
#define IRQ_SYSMMU_MFC_M1_0 EXYNOS4_IRQ_SYSMMU_MFC_M1_0
|
||||
#define IRQ_SYSMMU_PCIE_0 EXYNOS4_IRQ_SYSMMU_PCIE_0
|
||||
|
||||
#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
|
||||
#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
|
||||
#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM
|
||||
|
||||
#define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS
|
||||
#define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS
|
||||
|
||||
/* For EXYNOS5 SoCs */
|
||||
|
||||
#define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33)
|
||||
#define EXYNOS5_IRQ_PDMA0 IRQ_SPI(34)
|
||||
#define EXYNOS5_IRQ_PDMA1 IRQ_SPI(35)
|
||||
#define EXYNOS5_IRQ_TIMER0_VIC IRQ_SPI(36)
|
||||
#define EXYNOS5_IRQ_TIMER1_VIC IRQ_SPI(37)
|
||||
#define EXYNOS5_IRQ_TIMER2_VIC IRQ_SPI(38)
|
||||
#define EXYNOS5_IRQ_TIMER3_VIC IRQ_SPI(39)
|
||||
#define EXYNOS5_IRQ_TIMER4_VIC IRQ_SPI(40)
|
||||
#define EXYNOS5_IRQ_RTIC IRQ_SPI(41)
|
||||
#define EXYNOS5_IRQ_WDT IRQ_SPI(42)
|
||||
#define EXYNOS5_IRQ_RTC_ALARM IRQ_SPI(43)
|
||||
#define EXYNOS5_IRQ_RTC_TIC IRQ_SPI(44)
|
||||
#define EXYNOS5_IRQ_GPIO_XB IRQ_SPI(45)
|
||||
#define EXYNOS5_IRQ_GPIO_XA IRQ_SPI(46)
|
||||
#define EXYNOS5_IRQ_GPIO IRQ_SPI(47)
|
||||
#define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48)
|
||||
#define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49)
|
||||
#define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50)
|
||||
#define EXYNOS5_IRQ_UART0 IRQ_SPI(51)
|
||||
#define EXYNOS5_IRQ_UART1 IRQ_SPI(52)
|
||||
#define EXYNOS5_IRQ_UART2 IRQ_SPI(53)
|
||||
#define EXYNOS5_IRQ_UART3 IRQ_SPI(54)
|
||||
#define EXYNOS5_IRQ_UART4 IRQ_SPI(55)
|
||||
#define EXYNOS5_IRQ_IIC IRQ_SPI(56)
|
||||
#define EXYNOS5_IRQ_IIC1 IRQ_SPI(57)
|
||||
#define EXYNOS5_IRQ_IIC2 IRQ_SPI(58)
|
||||
#define EXYNOS5_IRQ_IIC3 IRQ_SPI(59)
|
||||
#define EXYNOS5_IRQ_IIC4 IRQ_SPI(60)
|
||||
#define EXYNOS5_IRQ_IIC5 IRQ_SPI(61)
|
||||
#define EXYNOS5_IRQ_IIC6 IRQ_SPI(62)
|
||||
#define EXYNOS5_IRQ_IIC7 IRQ_SPI(63)
|
||||
#define EXYNOS5_IRQ_IIC_HDMIPHY IRQ_SPI(64)
|
||||
#define EXYNOS5_IRQ_TMU IRQ_SPI(65)
|
||||
#define EXYNOS5_IRQ_FIQ_0 IRQ_SPI(66)
|
||||
#define EXYNOS5_IRQ_FIQ_1 IRQ_SPI(67)
|
||||
#define EXYNOS5_IRQ_SPI0 IRQ_SPI(68)
|
||||
#define EXYNOS5_IRQ_SPI1 IRQ_SPI(69)
|
||||
#define EXYNOS5_IRQ_SPI2 IRQ_SPI(70)
|
||||
#define EXYNOS5_IRQ_USB_HOST IRQ_SPI(71)
|
||||
#define EXYNOS5_IRQ_USB3_DRD IRQ_SPI(72)
|
||||
#define EXYNOS5_IRQ_MIPI_HSI IRQ_SPI(73)
|
||||
#define EXYNOS5_IRQ_USB_HSOTG IRQ_SPI(74)
|
||||
#define EXYNOS5_IRQ_HSMMC0 IRQ_SPI(75)
|
||||
#define EXYNOS5_IRQ_HSMMC1 IRQ_SPI(76)
|
||||
#define EXYNOS5_IRQ_HSMMC2 IRQ_SPI(77)
|
||||
#define EXYNOS5_IRQ_HSMMC3 IRQ_SPI(78)
|
||||
#define EXYNOS5_IRQ_MIPICSI0 IRQ_SPI(79)
|
||||
#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80)
|
||||
#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81)
|
||||
#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82)
|
||||
#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84)
|
||||
#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85)
|
||||
#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86)
|
||||
#define EXYNOS5_IRQ_GSC2 IRQ_SPI(87)
|
||||
#define EXYNOS5_IRQ_GSC3 IRQ_SPI(88)
|
||||
#define EXYNOS5_IRQ_JPEG IRQ_SPI(89)
|
||||
#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90)
|
||||
#define EXYNOS5_IRQ_2D IRQ_SPI(91)
|
||||
#define EXYNOS5_IRQ_SFMC0 IRQ_SPI(92)
|
||||
#define EXYNOS5_IRQ_SFMC1 IRQ_SPI(93)
|
||||
#define EXYNOS5_IRQ_MIXER IRQ_SPI(94)
|
||||
#define EXYNOS5_IRQ_HDMI IRQ_SPI(95)
|
||||
#define EXYNOS5_IRQ_MFC IRQ_SPI(96)
|
||||
#define EXYNOS5_IRQ_AUDIO_SS IRQ_SPI(97)
|
||||
#define EXYNOS5_IRQ_I2S0 IRQ_SPI(98)
|
||||
#define EXYNOS5_IRQ_I2S1 IRQ_SPI(99)
|
||||
#define EXYNOS5_IRQ_I2S2 IRQ_SPI(100)
|
||||
#define EXYNOS5_IRQ_AC97 IRQ_SPI(101)
|
||||
#define EXYNOS5_IRQ_PCM0 IRQ_SPI(102)
|
||||
#define EXYNOS5_IRQ_PCM1 IRQ_SPI(103)
|
||||
#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104)
|
||||
#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105)
|
||||
#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106)
|
||||
|
||||
#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108)
|
||||
#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109)
|
||||
#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110)
|
||||
#define EXYNOS5_IRQ_EAGLE_PMU IRQ_SPI(111)
|
||||
#define EXYNOS5_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
|
||||
#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113)
|
||||
#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
|
||||
#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
|
||||
#define EXYNOS5_IRQ_NFCON IRQ_SPI(116)
|
||||
|
||||
#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
|
||||
#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
|
||||
#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
|
||||
#define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126)
|
||||
#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127)
|
||||
|
||||
#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2)
|
||||
#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(1, 6)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC1_0 COMBINER_IRQ(2, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC1_1 COMBINER_IRQ(2, 3)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC2_0 COMBINER_IRQ(2, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC2_1 COMBINER_IRQ(2, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3)
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE0_1 COMBINER_IRQ(3, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6)
|
||||
#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(4, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1 COMBINER_IRQ(4, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_JPEG_1 COMBINER_IRQ(4, 3)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_FD_0 COMBINER_IRQ(5, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_FD_1 COMBINER_IRQ(5, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MCUISP_0 COMBINER_IRQ(5, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MCUISP_1 COMBINER_IRQ(5, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_3DNR_0 COMBINER_IRQ(5, 6)
|
||||
#define EXYNOS5_IRQ_SYSMMU_3DNR_1 COMBINER_IRQ(5, 7)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(6, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(6, 3)
|
||||
#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6)
|
||||
#define EXYNOS5_IRQ_SYSMMU_SSS_1 COMBINER_IRQ(6, 7)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(7, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MDMA0_1 COMBINER_IRQ(7, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(7, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3)
|
||||
#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GPSX_0 COMBINER_IRQ(7, 6)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GPSX_1 COMBINER_IRQ(7, 7)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(8, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(8, 6)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5)
|
||||
|
||||
#define EXYNOS5_IRQ_DP COMBINER_IRQ(10, 3)
|
||||
#define EXYNOS5_IRQ_SYSMMU_DIS0_0 COMBINER_IRQ(10, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_DIS0_1 COMBINER_IRQ(10, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_ISP_0 COMBINER_IRQ(10, 6)
|
||||
#define EXYNOS5_IRQ_SYSMMU_ISP_1 COMBINER_IRQ(10, 7)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_ODC_0 COMBINER_IRQ(11, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_ODC_1 COMBINER_IRQ(11, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6)
|
||||
#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7)
|
||||
|
||||
#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4)
|
||||
#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5)
|
||||
#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
|
||||
#define EXYNOS5_IRQ_MCT_L0 COMBINER_IRQ(23, 1)
|
||||
#define EXYNOS5_IRQ_MCT_L1 COMBINER_IRQ(23, 2)
|
||||
#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
|
||||
#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
|
||||
#define EXYNOS5_IRQ_MCT_G2 COMBINER_IRQ(23, 5)
|
||||
#define EXYNOS5_IRQ_MCT_G3 COMBINER_IRQ(23, 6)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE1_1 COMBINER_IRQ(24, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_2D_0 COMBINER_IRQ(24, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_2D_1 COMBINER_IRQ(24, 6)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT2 COMBINER_IRQ(25, 0)
|
||||
#define EXYNOS5_IRQ_EINT3 COMBINER_IRQ(25, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT4 COMBINER_IRQ(26, 0)
|
||||
#define EXYNOS5_IRQ_EINT5 COMBINER_IRQ(26, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT6 COMBINER_IRQ(27, 0)
|
||||
#define EXYNOS5_IRQ_EINT7 COMBINER_IRQ(27, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT8 COMBINER_IRQ(28, 0)
|
||||
#define EXYNOS5_IRQ_EINT9 COMBINER_IRQ(28, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT10 COMBINER_IRQ(29, 0)
|
||||
#define EXYNOS5_IRQ_EINT11 COMBINER_IRQ(29, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT12 COMBINER_IRQ(30, 0)
|
||||
#define EXYNOS5_IRQ_EINT13 COMBINER_IRQ(30, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT14 COMBINER_IRQ(31, 0)
|
||||
#define EXYNOS5_IRQ_EINT15 COMBINER_IRQ(31, 1)
|
||||
|
||||
#define EXYNOS5_MAX_COMBINER_NR 32
|
||||
|
||||
#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 13
|
||||
#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9
|
||||
#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5
|
||||
#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1
|
||||
|
||||
#define MAX_COMBINER_NR (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \
|
||||
EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR)
|
||||
|
||||
#define S5P_EINT_BASE1 COMBINER_IRQ(MAX_COMBINER_NR, 0)
|
||||
#define S5P_EINT_BASE2 (S5P_EINT_BASE1 + 16)
|
||||
#define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32)
|
||||
#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
|
||||
#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
|
||||
|
||||
/* Set the default NR_IRQS */
|
||||
#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
|
||||
|
||||
#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
|
||||
|
||||
#endif /* __ASM_ARCH_IRQS_H */
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
|
||||
#define EXYNOS4_PA_SYSRAM0 0x02025000
|
||||
#define EXYNOS4_PA_SYSRAM1 0x02020000
|
||||
#define EXYNOS5_PA_SYSRAM 0x02020000
|
||||
|
||||
#define EXYNOS4_PA_FIMC0 0x11800000
|
||||
#define EXYNOS4_PA_FIMC1 0x11810000
|
||||
|
|
@ -44,14 +45,23 @@
|
|||
#define EXYNOS4_PA_ONENAND 0x0C000000
|
||||
#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
|
||||
|
||||
#define EXYNOS4_PA_CHIPID 0x10000000
|
||||
#define EXYNOS_PA_CHIPID 0x10000000
|
||||
|
||||
#define EXYNOS4_PA_SYSCON 0x10010000
|
||||
#define EXYNOS5_PA_SYSCON 0x10050100
|
||||
|
||||
#define EXYNOS4_PA_PMU 0x10020000
|
||||
#define EXYNOS5_PA_PMU 0x10040000
|
||||
|
||||
#define EXYNOS4_PA_CMU 0x10030000
|
||||
#define EXYNOS5_PA_CMU 0x10010000
|
||||
|
||||
#define EXYNOS4_PA_SYSTIMER 0x10050000
|
||||
#define EXYNOS5_PA_SYSTIMER 0x101C0000
|
||||
|
||||
#define EXYNOS4_PA_WATCHDOG 0x10060000
|
||||
#define EXYNOS5_PA_WATCHDOG 0x101D0000
|
||||
|
||||
#define EXYNOS4_PA_RTC 0x10070000
|
||||
|
||||
#define EXYNOS4_PA_KEYPAD 0x100A0000
|
||||
|
|
@ -59,15 +69,19 @@
|
|||
#define EXYNOS4_PA_DMC0 0x10400000
|
||||
|
||||
#define EXYNOS4_PA_COMBINER 0x10440000
|
||||
#define EXYNOS5_PA_COMBINER 0x10440000
|
||||
|
||||
#define EXYNOS4_PA_GIC_CPU 0x10480000
|
||||
#define EXYNOS4_PA_GIC_DIST 0x10490000
|
||||
#define EXYNOS5_PA_GIC_CPU 0x10480000
|
||||
#define EXYNOS5_PA_GIC_DIST 0x10490000
|
||||
|
||||
#define EXYNOS4_PA_COREPERI 0x10500000
|
||||
#define EXYNOS4_PA_TWD 0x10500600
|
||||
#define EXYNOS4_PA_L2CC 0x10502000
|
||||
|
||||
#define EXYNOS4_PA_MDMA 0x10810000
|
||||
#define EXYNOS4_PA_MDMA0 0x10810000
|
||||
#define EXYNOS4_PA_MDMA1 0x12840000
|
||||
#define EXYNOS4_PA_PDMA0 0x12680000
|
||||
#define EXYNOS4_PA_PDMA1 0x12690000
|
||||
|
||||
|
|
@ -91,7 +105,6 @@
|
|||
#define EXYNOS4_PA_SPI1 0x13930000
|
||||
#define EXYNOS4_PA_SPI2 0x13940000
|
||||
|
||||
|
||||
#define EXYNOS4_PA_GPIO1 0x11400000
|
||||
#define EXYNOS4_PA_GPIO2 0x11000000
|
||||
#define EXYNOS4_PA_GPIO3 0x03860000
|
||||
|
|
@ -109,6 +122,7 @@
|
|||
#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
|
||||
|
||||
#define EXYNOS4_PA_SROMC 0x12570000
|
||||
#define EXYNOS5_PA_SROMC 0x12250000
|
||||
|
||||
#define EXYNOS4_PA_EHCI 0x12580000
|
||||
#define EXYNOS4_PA_OHCI 0x12590000
|
||||
|
|
@ -116,6 +130,7 @@
|
|||
#define EXYNOS4_PA_MFC 0x13400000
|
||||
|
||||
#define EXYNOS4_PA_UART 0x13800000
|
||||
#define EXYNOS5_PA_UART 0x12C00000
|
||||
|
||||
#define EXYNOS4_PA_VP 0x12C00000
|
||||
#define EXYNOS4_PA_MIXER 0x12C10000
|
||||
|
|
@ -124,6 +139,7 @@
|
|||
#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
|
||||
|
||||
#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
|
||||
#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000))
|
||||
|
||||
#define EXYNOS4_PA_ADC 0x13910000
|
||||
#define EXYNOS4_PA_ADC1 0x13911000
|
||||
|
|
@ -133,8 +149,10 @@
|
|||
#define EXYNOS4_PA_SPDIF 0x139B0000
|
||||
|
||||
#define EXYNOS4_PA_TIMER 0x139D0000
|
||||
#define EXYNOS5_PA_TIMER 0x12DD0000
|
||||
|
||||
#define EXYNOS4_PA_SDRAM 0x40000000
|
||||
#define EXYNOS5_PA_SDRAM 0x40000000
|
||||
|
||||
/* Compatibiltiy Defines */
|
||||
|
||||
|
|
@ -152,7 +170,6 @@
|
|||
#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
|
||||
#define S3C_PA_RTC EXYNOS4_PA_RTC
|
||||
#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
|
||||
#define S3C_PA_UART EXYNOS4_PA_UART
|
||||
#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
|
||||
#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
|
||||
#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
|
||||
|
|
@ -181,15 +198,18 @@
|
|||
|
||||
/* Compatibility UART */
|
||||
|
||||
#define EXYNOS4_PA_UART0 0x13800000
|
||||
#define EXYNOS4_PA_UART1 0x13810000
|
||||
#define EXYNOS4_PA_UART2 0x13820000
|
||||
#define EXYNOS4_PA_UART3 0x13830000
|
||||
#define EXYNOS4_SZ_UART SZ_256
|
||||
|
||||
#define EXYNOS5_PA_UART0 0x12C00000
|
||||
#define EXYNOS5_PA_UART1 0x12C10000
|
||||
#define EXYNOS5_PA_UART2 0x12C20000
|
||||
#define EXYNOS5_PA_UART3 0x12C30000
|
||||
#define EXYNOS5_SZ_UART SZ_256
|
||||
|
||||
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
|
||||
|
||||
#define S5P_PA_UART(x) (EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET))
|
||||
#define S5P_PA_UART0 S5P_PA_UART(0)
|
||||
#define S5P_PA_UART1 S5P_PA_UART(1)
|
||||
#define S5P_PA_UART2 S5P_PA_UART(2)
|
||||
#define S5P_PA_UART3 S5P_PA_UART(3)
|
||||
#define S5P_PA_UART4 S5P_PA_UART(4)
|
||||
|
||||
#define S5P_SZ_UART SZ_256
|
||||
|
||||
#endif /* __ASM_ARCH_MAP_H */
|
||||
|
|
|
|||
|
|
@ -16,195 +16,309 @@
|
|||
#include <plat/cpu.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
|
||||
#define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x))
|
||||
|
||||
#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500)
|
||||
#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600)
|
||||
#define S5P_CLKGATE_IP_LEFTBUS S5P_CLKREG(0x04800)
|
||||
#define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500)
|
||||
#define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600)
|
||||
#define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800)
|
||||
|
||||
#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500)
|
||||
#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
|
||||
#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800)
|
||||
#define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500)
|
||||
#define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600)
|
||||
#define EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800)
|
||||
|
||||
#define S5P_EPLL_LOCK S5P_CLKREG(0x0C010)
|
||||
#define S5P_VPLL_LOCK S5P_CLKREG(0x0C020)
|
||||
#define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010)
|
||||
#define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020)
|
||||
|
||||
#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
|
||||
#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
|
||||
#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
|
||||
#define S5P_VPLL_CON1 S5P_CLKREG(0x0C124)
|
||||
#define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110)
|
||||
#define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114)
|
||||
#define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120)
|
||||
#define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124)
|
||||
|
||||
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
|
||||
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
|
||||
#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
|
||||
#define S5P_CLKSRC_TV S5P_CLKREG(0x0C224)
|
||||
#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228)
|
||||
#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C)
|
||||
#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
|
||||
#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
|
||||
#define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C)
|
||||
#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
|
||||
#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
|
||||
#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
|
||||
#define EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210)
|
||||
#define EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214)
|
||||
#define EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220)
|
||||
#define EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224)
|
||||
#define EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228)
|
||||
#define EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C)
|
||||
#define EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230)
|
||||
#define EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234)
|
||||
#define EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C)
|
||||
#define EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240)
|
||||
#define EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250)
|
||||
#define EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254)
|
||||
|
||||
#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
|
||||
#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
|
||||
#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324)
|
||||
#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
|
||||
#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C)
|
||||
#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
|
||||
#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
|
||||
#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
|
||||
#define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310)
|
||||
#define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320)
|
||||
#define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324)
|
||||
#define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334)
|
||||
#define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C)
|
||||
#define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340)
|
||||
#define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350)
|
||||
#define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354)
|
||||
|
||||
#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
|
||||
#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
|
||||
#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524)
|
||||
#define S5P_CLKDIV_MFC S5P_CLKREG(0x0C528)
|
||||
#define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C)
|
||||
#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
|
||||
#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
|
||||
#define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C)
|
||||
#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
|
||||
#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
|
||||
#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548)
|
||||
#define S5P_CLKDIV_FSYS3 S5P_CLKREG(0x0C54C)
|
||||
#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550)
|
||||
#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554)
|
||||
#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558)
|
||||
#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
|
||||
#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
|
||||
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
|
||||
#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580)
|
||||
#define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510)
|
||||
#define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520)
|
||||
#define EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524)
|
||||
#define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528)
|
||||
#define EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C)
|
||||
#define EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530)
|
||||
#define EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534)
|
||||
#define EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C)
|
||||
#define EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540)
|
||||
#define EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544)
|
||||
#define EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548)
|
||||
#define EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C)
|
||||
#define EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550)
|
||||
#define EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554)
|
||||
#define EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558)
|
||||
#define EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C)
|
||||
#define EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560)
|
||||
#define EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564)
|
||||
#define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580)
|
||||
|
||||
#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610)
|
||||
#define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610)
|
||||
#define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628)
|
||||
|
||||
#define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820)
|
||||
#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920)
|
||||
#define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924)
|
||||
#define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928)
|
||||
#define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C)
|
||||
#define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
|
||||
S5P_CLKREG(0x0C930) : \
|
||||
S5P_CLKREG(0x04930))
|
||||
#define S5P_CLKGATE_IP_IMAGE_4210 S5P_CLKREG(0x0C930)
|
||||
#define S5P_CLKGATE_IP_IMAGE_4212 S5P_CLKREG(0x04930)
|
||||
#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
|
||||
#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
|
||||
#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C)
|
||||
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
|
||||
#define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
|
||||
S5P_CLKREG(0x0C960) : \
|
||||
S5P_CLKREG(0x08960))
|
||||
#define S5P_CLKGATE_IP_PERIR_4210 S5P_CLKREG(0x0C960)
|
||||
#define S5P_CLKGATE_IP_PERIR_4212 S5P_CLKREG(0x08960)
|
||||
#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970)
|
||||
#define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820)
|
||||
#define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920)
|
||||
#define EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924)
|
||||
#define EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928)
|
||||
#define EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C)
|
||||
#define EXYNOS4_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
|
||||
EXYNOS_CLKREG(0x0C930) : \
|
||||
EXYNOS_CLKREG(0x04930))
|
||||
#define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930)
|
||||
#define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930)
|
||||
#define EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934)
|
||||
#define EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940)
|
||||
#define EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C)
|
||||
#define EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950)
|
||||
#define EXYNOS4_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
|
||||
EXYNOS_CLKREG(0x0C960) : \
|
||||
EXYNOS_CLKREG(0x08960))
|
||||
#define EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960)
|
||||
#define EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960)
|
||||
#define EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970)
|
||||
|
||||
#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300)
|
||||
#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200)
|
||||
#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500)
|
||||
#define S5P_CLKDIV_DMC1 S5P_CLKREG(0x10504)
|
||||
#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600)
|
||||
#define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900)
|
||||
#define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300)
|
||||
#define EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200)
|
||||
#define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500)
|
||||
#define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504)
|
||||
#define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600)
|
||||
#define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604)
|
||||
#define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900)
|
||||
|
||||
#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
|
||||
#define S5P_MPLL_LOCK (soc_is_exynos4210() ? \
|
||||
S5P_CLKREG(0x14004) : \
|
||||
S5P_CLKREG(0x10008))
|
||||
#define S5P_APLL_CON0 S5P_CLKREG(0x14100)
|
||||
#define S5P_APLL_CON1 S5P_CLKREG(0x14104)
|
||||
#define S5P_MPLL_CON0 (soc_is_exynos4210() ? \
|
||||
S5P_CLKREG(0x14108) : \
|
||||
S5P_CLKREG(0x10108))
|
||||
#define S5P_MPLL_CON1 (soc_is_exynos4210() ? \
|
||||
S5P_CLKREG(0x1410C) : \
|
||||
S5P_CLKREG(0x1010C))
|
||||
#define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094)
|
||||
#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0)
|
||||
|
||||
#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200)
|
||||
#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
|
||||
#define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000)
|
||||
#define EXYNOS4_MPLL_LOCK (soc_is_exynos4210() ? \
|
||||
EXYNOS_CLKREG(0x14004) : \
|
||||
EXYNOS_CLKREG(0x10008))
|
||||
#define EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100)
|
||||
#define EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104)
|
||||
#define EXYNOS4_MPLL_CON0 (soc_is_exynos4210() ? \
|
||||
EXYNOS_CLKREG(0x14108) : \
|
||||
EXYNOS_CLKREG(0x10108))
|
||||
#define EXYNOS4_MPLL_CON1 (soc_is_exynos4210() ? \
|
||||
EXYNOS_CLKREG(0x1410C) : \
|
||||
EXYNOS_CLKREG(0x1010C))
|
||||
|
||||
#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500)
|
||||
#define S5P_CLKDIV_CPU1 S5P_CLKREG(0x14504)
|
||||
#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600)
|
||||
#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604)
|
||||
#define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200)
|
||||
#define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400)
|
||||
|
||||
#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
|
||||
#define S5P_CLKGATE_IP_CPU S5P_CLKREG(0x14900)
|
||||
#define EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500)
|
||||
#define EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504)
|
||||
#define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600)
|
||||
#define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604)
|
||||
|
||||
#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */
|
||||
#define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800)
|
||||
#define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900)
|
||||
|
||||
#define S5P_APLLCON0_ENABLE_SHIFT (31)
|
||||
#define S5P_APLLCON0_LOCKED_SHIFT (29)
|
||||
#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
|
||||
#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
|
||||
#define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */
|
||||
|
||||
#define S5P_EPLLCON0_ENABLE_SHIFT (31)
|
||||
#define S5P_EPLLCON0_LOCKED_SHIFT (29)
|
||||
#define EXYNOS4_APLLCON0_ENABLE_SHIFT (31)
|
||||
#define EXYNOS4_APLLCON0_LOCKED_SHIFT (29)
|
||||
#define EXYNOS4_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
|
||||
#define EXYNOS4_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
|
||||
|
||||
#define S5P_VPLLCON0_ENABLE_SHIFT (31)
|
||||
#define S5P_VPLLCON0_LOCKED_SHIFT (29)
|
||||
#define EXYNOS4_EPLLCON0_ENABLE_SHIFT (31)
|
||||
#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29)
|
||||
|
||||
#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
|
||||
#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
|
||||
#define EXYNOS4_VPLLCON0_ENABLE_SHIFT (31)
|
||||
#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29)
|
||||
|
||||
#define S5P_CLKDIV_CPU0_CORE_SHIFT (0)
|
||||
#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
|
||||
#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4)
|
||||
#define S5P_CLKDIV_CPU0_COREM0_MASK (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)
|
||||
#define S5P_CLKDIV_CPU0_COREM1_SHIFT (8)
|
||||
#define S5P_CLKDIV_CPU0_COREM1_MASK (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)
|
||||
#define S5P_CLKDIV_CPU0_PERIPH_SHIFT (12)
|
||||
#define S5P_CLKDIV_CPU0_PERIPH_MASK (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)
|
||||
#define S5P_CLKDIV_CPU0_ATB_SHIFT (16)
|
||||
#define S5P_CLKDIV_CPU0_ATB_MASK (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)
|
||||
#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
|
||||
#define S5P_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
|
||||
#define S5P_CLKDIV_CPU0_APLL_SHIFT (24)
|
||||
#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
|
||||
#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
|
||||
#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
|
||||
|
||||
#define S5P_CLKDIV_DMC0_ACP_SHIFT (0)
|
||||
#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
|
||||
#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
|
||||
#define S5P_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
|
||||
#define S5P_CLKDIV_DMC0_DPHY_SHIFT (8)
|
||||
#define S5P_CLKDIV_DMC0_DPHY_MASK (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)
|
||||
#define S5P_CLKDIV_DMC0_DMC_SHIFT (12)
|
||||
#define S5P_CLKDIV_DMC0_DMC_MASK (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)
|
||||
#define S5P_CLKDIV_DMC0_DMCD_SHIFT (16)
|
||||
#define S5P_CLKDIV_DMC0_DMCD_MASK (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)
|
||||
#define S5P_CLKDIV_DMC0_DMCP_SHIFT (20)
|
||||
#define S5P_CLKDIV_DMC0_DMCP_MASK (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)
|
||||
#define S5P_CLKDIV_DMC0_COPY2_SHIFT (24)
|
||||
#define S5P_CLKDIV_DMC0_COPY2_MASK (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)
|
||||
#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28)
|
||||
#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4)
|
||||
#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8)
|
||||
#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12)
|
||||
#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16)
|
||||
#define EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
|
||||
#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24)
|
||||
#define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28
|
||||
#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)
|
||||
|
||||
#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0)
|
||||
#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
|
||||
#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4)
|
||||
#define S5P_CLKDIV_TOP_ACLK100_MASK (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)
|
||||
#define S5P_CLKDIV_TOP_ACLK160_SHIFT (8)
|
||||
#define S5P_CLKDIV_TOP_ACLK160_MASK (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)
|
||||
#define S5P_CLKDIV_TOP_ACLK133_SHIFT (12)
|
||||
#define S5P_CLKDIV_TOP_ACLK133_MASK (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)
|
||||
#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16)
|
||||
#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0
|
||||
#define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4
|
||||
#define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8
|
||||
#define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)
|
||||
|
||||
#define S5P_CLKDIV_BUS_GDLR_SHIFT (0)
|
||||
#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
|
||||
#define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
|
||||
#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
|
||||
#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24)
|
||||
#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)
|
||||
#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
|
||||
|
||||
#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4)
|
||||
#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8)
|
||||
#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12)
|
||||
#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16)
|
||||
#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24)
|
||||
#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
|
||||
|
||||
#define EXYNOS4_CLKDIV_MFC_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
|
||||
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)
|
||||
#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
|
||||
|
||||
#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)
|
||||
#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
|
||||
|
||||
#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4)
|
||||
#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8)
|
||||
#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12)
|
||||
#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
|
||||
|
||||
/* Only for EXYNOS4210 */
|
||||
|
||||
#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
|
||||
#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
|
||||
#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
|
||||
#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
|
||||
#define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238)
|
||||
#define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338)
|
||||
#define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538)
|
||||
#define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938)
|
||||
|
||||
/* Only for EXYNOS4212 */
|
||||
|
||||
#define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568)
|
||||
|
||||
#define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668)
|
||||
|
||||
#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
|
||||
|
||||
/* For EXYNOS5250 */
|
||||
|
||||
#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
|
||||
#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
|
||||
#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
|
||||
#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
|
||||
#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)
|
||||
|
||||
#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)
|
||||
|
||||
#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
|
||||
|
||||
#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
|
||||
#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
|
||||
#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
|
||||
#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
|
||||
#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
|
||||
#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
|
||||
|
||||
#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
|
||||
#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
|
||||
#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
|
||||
#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
|
||||
#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
|
||||
#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
|
||||
|
||||
#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
|
||||
#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
|
||||
#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
|
||||
#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
|
||||
#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
|
||||
|
||||
#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
|
||||
#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
|
||||
#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
|
||||
#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
|
||||
#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
|
||||
#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
|
||||
#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
|
||||
#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
|
||||
#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
|
||||
#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
|
||||
|
||||
#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
|
||||
#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
|
||||
#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
|
||||
#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
|
||||
#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
|
||||
#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
|
||||
#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
|
||||
#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)
|
||||
#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
|
||||
#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
|
||||
|
||||
#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)
|
||||
#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
|
||||
#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
|
||||
|
||||
#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
|
||||
|
||||
#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
|
||||
|
||||
/* Compatibility defines and inclusion */
|
||||
|
||||
#include <mach/regs-pmu.h>
|
||||
|
||||
#define S5P_EPLL_CON S5P_EPLL_CON0
|
||||
#define S5P_EPLL_CON EXYNOS4_EPLL_CON0
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_CLOCK_H */
|
||||
|
|
|
|||
|
|
@ -16,6 +16,15 @@
|
|||
#include <mach/map.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
|
||||
#define EINT_CON(b, x) (b + 0xE00 + (EINT_REG_NR(x) * 4))
|
||||
#define EINT_FLTCON(b, x) (b + 0xE80 + (EINT_REG_NR(x) * 4))
|
||||
#define EINT_MASK(b, x) (b + 0xF00 + (EINT_REG_NR(x) * 4))
|
||||
#define EINT_PEND(b, x) (b + 0xF40 + (EINT_REG_NR(x) * 4))
|
||||
|
||||
#define EINT_OFFSET_BIT(x) (1 << (EINT_OFFSET(x) & 0x7))
|
||||
|
||||
/* compatibility for plat-s5p/irq-pm.c */
|
||||
#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00)
|
||||
#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4))
|
||||
|
||||
|
|
@ -28,15 +37,4 @@
|
|||
#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
|
||||
#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4))
|
||||
|
||||
#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
|
||||
|
||||
#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
|
||||
|
||||
#define EINT_MODE S3C_GPIO_SFN(0xf)
|
||||
|
||||
#define EINT_GPIO_0(x) EXYNOS4_GPX0(x)
|
||||
#define EINT_GPIO_1(x) EXYNOS4_GPX1(x)
|
||||
#define EINT_GPIO_2(x) EXYNOS4_GPX2(x)
|
||||
#define EINT_GPIO_3(x) EXYNOS4_GPX3(x)
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_GPIO_H */
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@
|
|||
#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26)
|
||||
|
||||
#define S5P_SWRESET S5P_PMUREG(0x0400)
|
||||
#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
|
||||
|
||||
#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
|
||||
#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
|
||||
|
|
|
|||
|
|
@ -1,9 +1,8 @@
|
|||
/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
/*
|
||||
* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4 - uncompress code
|
||||
* EXYNOS - uncompress code
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
|
@ -13,12 +12,20 @@
|
|||
#ifndef __ASM_ARCH_UNCOMPRESS_H
|
||||
#define __ASM_ARCH_UNCOMPRESS_H __FILE__
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
volatile u8 *uart_base;
|
||||
|
||||
#include <plat/uncompress.h>
|
||||
|
||||
static void arch_detect_cpu(void)
|
||||
{
|
||||
/* we do not need to do any cpu detection here at the moment. */
|
||||
if (machine_is_smdk5250())
|
||||
uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
|
||||
else
|
||||
uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
|
||||
|
||||
/*
|
||||
* For preventing FIFO overrun or infinite loop of UART console,
|
||||
|
|
|
|||
|
|
@ -37,13 +37,13 @@
|
|||
* data from the device tree.
|
||||
*/
|
||||
static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART0,
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
|
||||
"exynos4210-uart.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART1,
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
|
||||
"exynos4210-uart.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART2,
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
|
||||
"exynos4210-uart.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART3,
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
|
||||
"exynos4210-uart.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
|
||||
"exynos4-sdhci.0", NULL),
|
||||
|
|
|
|||
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
|
||||
*
|
||||
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/serial_core.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/regs-serial.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
/*
|
||||
* The following lookup table is used to override device names when devices
|
||||
* are registered from device tree. This is temporarily added to enable
|
||||
* device tree support addition for the EXYNOS5 architecture.
|
||||
*
|
||||
* For drivers that require platform data to be provided from the machine
|
||||
* file, a platform data pointer can also be supplied along with the
|
||||
* devices names. Usually, the platform data elements that cannot be parsed
|
||||
* from the device tree by the drivers (example: function pointers) are
|
||||
* supplied. But it should be noted that this is a temporary mechanism and
|
||||
* at some point, the drivers should be capable of parsing all the platform
|
||||
* data from the device tree.
|
||||
*/
|
||||
static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
|
||||
"exynos4210-uart.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
|
||||
"exynos4210-uart.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
|
||||
"exynos4210-uart.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
|
||||
"exynos4210-uart.3", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.2", NULL),
|
||||
{},
|
||||
};
|
||||
|
||||
static void __init exynos5250_dt_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
}
|
||||
|
||||
static void __init exynos5250_dt_machine_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
exynos5250_auxdata_lookup, NULL);
|
||||
}
|
||||
|
||||
static char const *exynos5250_dt_compat[] __initdata = {
|
||||
"samsung,exynos5250",
|
||||
NULL
|
||||
};
|
||||
|
||||
DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
|
||||
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
|
||||
.init_irq = exynos5_init_irq,
|
||||
.map_io = exynos5250_dt_map_io,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = exynos5250_dt_machine_init,
|
||||
.timer = &exynos4_timer,
|
||||
.dt_compat = exynos5250_dt_compat,
|
||||
.restart = exynos5_restart,
|
||||
MACHINE_END
|
||||
|
|
@ -412,7 +412,7 @@ static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
|
|||
{ MAX8997_BUCK7, &max8997_buck7_data },
|
||||
};
|
||||
|
||||
struct max8997_platform_data __initdata origen_max8997_pdata = {
|
||||
static struct max8997_platform_data __initdata origen_max8997_pdata = {
|
||||
.num_regulators = ARRAY_SIZE(origen_max8997_regulators),
|
||||
.regulators = origen_max8997_regulators,
|
||||
|
||||
|
|
|
|||
|
|
@ -997,7 +997,7 @@ static void __init universal_map_io(void)
|
|||
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
|
||||
}
|
||||
|
||||
void s5p_tv_setup(void)
|
||||
static void s5p_tv_setup(void)
|
||||
{
|
||||
/* direct HPD to HDMI chip */
|
||||
gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
|
||||
|
|
|
|||
|
|
@ -258,7 +258,10 @@ static void exynos4_clockevent_init(void)
|
|||
mct_comp_device.cpumask = cpumask_of(0);
|
||||
clockevents_register_device(&mct_comp_device);
|
||||
|
||||
setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
|
||||
if (soc_is_exynos5250())
|
||||
setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
|
||||
else
|
||||
setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_LOCAL_TIMERS
|
||||
|
|
@ -406,16 +409,16 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
|
|||
if (mct_int_type == MCT_INT_SPI) {
|
||||
if (cpu == 0) {
|
||||
mct_tick0_event_irq.dev_id = mevt;
|
||||
evt->irq = IRQ_MCT_L0;
|
||||
setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
|
||||
evt->irq = EXYNOS4_IRQ_MCT_L0;
|
||||
setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
|
||||
} else {
|
||||
mct_tick1_event_irq.dev_id = mevt;
|
||||
evt->irq = IRQ_MCT_L1;
|
||||
setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
|
||||
irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
|
||||
evt->irq = EXYNOS4_IRQ_MCT_L1;
|
||||
setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
|
||||
irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
|
||||
}
|
||||
} else {
|
||||
enable_percpu_irq(IRQ_MCT_LOCALTIMER, 0);
|
||||
enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -437,7 +440,7 @@ void local_timer_stop(struct clock_event_device *evt)
|
|||
else
|
||||
remove_irq(evt->irq, &mct_tick1_event_irq);
|
||||
else
|
||||
disable_percpu_irq(IRQ_MCT_LOCALTIMER);
|
||||
disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
|
||||
}
|
||||
#endif /* CONFIG_LOCAL_TIMERS */
|
||||
|
||||
|
|
@ -452,11 +455,11 @@ static void __init exynos4_timer_resources(void)
|
|||
if (mct_int_type == MCT_INT_PPI) {
|
||||
int err;
|
||||
|
||||
err = request_percpu_irq(IRQ_MCT_LOCALTIMER,
|
||||
err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
|
||||
exynos4_mct_tick_isr, "MCT",
|
||||
&percpu_mct_tick);
|
||||
WARN(err, "MCT: can't request IRQ %d (%d)\n",
|
||||
IRQ_MCT_LOCALTIMER, err);
|
||||
EXYNOS_IRQ_MCT_LOCALTIMER, err);
|
||||
}
|
||||
#endif /* CONFIG_LOCAL_TIMERS */
|
||||
}
|
||||
|
|
|
|||
|
|
@ -166,7 +166,10 @@ void __init smp_init_cpus(void)
|
|||
void __iomem *scu_base = scu_base_addr();
|
||||
unsigned int i, ncores;
|
||||
|
||||
ncores = scu_base ? scu_get_core_count(scu_base) : 1;
|
||||
if (soc_is_exynos5250())
|
||||
ncores = 2;
|
||||
else
|
||||
ncores = scu_base ? scu_get_core_count(scu_base) : 1;
|
||||
|
||||
/* sanity check */
|
||||
if (ncores > nr_cpu_ids) {
|
||||
|
|
@ -183,8 +186,8 @@ void __init smp_init_cpus(void)
|
|||
|
||||
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
|
||||
scu_enable(scu_base_addr());
|
||||
if (!soc_is_exynos5250())
|
||||
scu_enable(scu_base_addr());
|
||||
|
||||
/*
|
||||
* Write the address of secondary startup into the
|
||||
|
|
|
|||
|
|
@ -38,29 +38,29 @@
|
|||
#include <mach/pmu.h>
|
||||
|
||||
static struct sleep_save exynos4_set_clksrc[] = {
|
||||
{ .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, },
|
||||
{ .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, },
|
||||
{ .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, },
|
||||
{ .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
|
||||
{ .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
|
||||
{ .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, },
|
||||
{ .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
|
||||
{ .reg = S5P_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
|
||||
{ .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
|
||||
{ .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },
|
||||
{ .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, },
|
||||
{ .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, },
|
||||
{ .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
|
||||
{ .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
|
||||
{ .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, },
|
||||
{ .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
|
||||
{ .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
|
||||
{ .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, },
|
||||
};
|
||||
|
||||
static struct sleep_save exynos4210_set_clksrc[] = {
|
||||
{ .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
|
||||
{ .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
|
||||
};
|
||||
|
||||
static struct sleep_save exynos4_epll_save[] = {
|
||||
SAVE_ITEM(S5P_EPLL_CON0),
|
||||
SAVE_ITEM(S5P_EPLL_CON1),
|
||||
SAVE_ITEM(EXYNOS4_EPLL_CON0),
|
||||
SAVE_ITEM(EXYNOS4_EPLL_CON1),
|
||||
};
|
||||
|
||||
static struct sleep_save exynos4_vpll_save[] = {
|
||||
SAVE_ITEM(S5P_VPLL_CON0),
|
||||
SAVE_ITEM(S5P_VPLL_CON1),
|
||||
SAVE_ITEM(EXYNOS4_VPLL_CON0),
|
||||
SAVE_ITEM(EXYNOS4_VPLL_CON1),
|
||||
};
|
||||
|
||||
static struct sleep_save exynos4_core_save[] = {
|
||||
|
|
@ -239,7 +239,7 @@ static void exynos4_restore_pll(void)
|
|||
locktime = (3000 / pll_in_rate) * p_div;
|
||||
lockcnt = locktime * 10000 / (10000 / pll_in_rate);
|
||||
|
||||
__raw_writel(lockcnt, S5P_EPLL_LOCK);
|
||||
__raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
|
||||
|
||||
s3c_pm_do_restore_core(exynos4_epll_save,
|
||||
ARRAY_SIZE(exynos4_epll_save));
|
||||
|
|
@ -257,7 +257,7 @@ static void exynos4_restore_pll(void)
|
|||
locktime = 750;
|
||||
lockcnt = locktime * 10000 / (10000 / pll_in_rate);
|
||||
|
||||
__raw_writel(lockcnt, S5P_VPLL_LOCK);
|
||||
__raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
|
||||
|
||||
s3c_pm_do_restore_core(exynos4_vpll_save,
|
||||
ARRAY_SIZE(exynos4_vpll_save));
|
||||
|
|
@ -268,14 +268,14 @@ static void exynos4_restore_pll(void)
|
|||
|
||||
do {
|
||||
if (epll_wait) {
|
||||
pll_con = __raw_readl(S5P_EPLL_CON0);
|
||||
if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
|
||||
pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
|
||||
if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
|
||||
epll_wait = 0;
|
||||
}
|
||||
|
||||
if (vpll_wait) {
|
||||
pll_con = __raw_readl(S5P_VPLL_CON0);
|
||||
if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
|
||||
pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
|
||||
if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
|
||||
vpll_wait = 0;
|
||||
}
|
||||
} while (epll_wait || vpll_wait);
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-exynos4/setup-i2c0.c
|
||||
*
|
||||
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
|
||||
* Copyright (c) 2009-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* I2C0 GPIO configuration.
|
||||
|
|
@ -18,9 +16,14 @@ struct platform_device; /* don't need the contents */
|
|||
#include <linux/gpio.h>
|
||||
#include <plat/iic.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
if (soc_is_exynos5250())
|
||||
/* will be implemented with gpio function */
|
||||
return;
|
||||
|
||||
s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
|
||||
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@
|
|||
*/
|
||||
#define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1)
|
||||
#define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2)
|
||||
#define IRQ_LPC32XX_GPI_11 LPC32XX_SIC1_IRQ(4)
|
||||
#define IRQ_LPC32XX_GPI_28 LPC32XX_SIC1_IRQ(4)
|
||||
#define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6)
|
||||
#define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7)
|
||||
#define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8)
|
||||
|
|
|
|||
|
|
@ -118,6 +118,10 @@ static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = {
|
|||
.event_group = &lpc32xx_event_pin_regs,
|
||||
.mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT,
|
||||
},
|
||||
[IRQ_LPC32XX_GPI_28] = {
|
||||
.event_group = &lpc32xx_event_pin_regs,
|
||||
.mask = LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT,
|
||||
},
|
||||
[IRQ_LPC32XX_GPIO_00] = {
|
||||
.event_group = &lpc32xx_event_int_regs,
|
||||
.mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
|
||||
|
|
@ -305,9 +309,18 @@ static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state)
|
|||
|
||||
if (state)
|
||||
eventreg |= lpc32xx_events[d->irq].mask;
|
||||
else
|
||||
else {
|
||||
eventreg &= ~lpc32xx_events[d->irq].mask;
|
||||
|
||||
/*
|
||||
* When disabling the wakeup, clear the latched
|
||||
* event
|
||||
*/
|
||||
__raw_writel(lpc32xx_events[d->irq].mask,
|
||||
lpc32xx_events[d->irq].
|
||||
event_group->rawstat_reg);
|
||||
}
|
||||
|
||||
__raw_writel(eventreg,
|
||||
lpc32xx_events[d->irq].event_group->enab_reg);
|
||||
|
||||
|
|
@ -380,13 +393,15 @@ void __init lpc32xx_init_irq(void)
|
|||
|
||||
/* Setup SIC1 */
|
||||
__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
|
||||
__raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
|
||||
__raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
|
||||
__raw_writel(SIC1_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
|
||||
__raw_writel(SIC1_ATR_DEFAULT,
|
||||
LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
|
||||
|
||||
/* Setup SIC2 */
|
||||
__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
|
||||
__raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
|
||||
__raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
|
||||
__raw_writel(SIC2_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
|
||||
__raw_writel(SIC2_ATR_DEFAULT,
|
||||
LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
|
||||
|
||||
/* Configure supported IRQ's */
|
||||
for (i = 0; i < NR_IRQS; i++) {
|
||||
|
|
|
|||
|
|
@ -88,6 +88,7 @@ struct uartinit {
|
|||
char *uart_ck_name;
|
||||
u32 ck_mode_mask;
|
||||
void __iomem *pdiv_clk_reg;
|
||||
resource_size_t mapbase;
|
||||
};
|
||||
|
||||
static struct uartinit uartinit_data[] __initdata = {
|
||||
|
|
@ -97,6 +98,7 @@ static struct uartinit uartinit_data[] __initdata = {
|
|||
.ck_mode_mask =
|
||||
LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
|
||||
.pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
|
||||
.mapbase = LPC32XX_UART5_BASE,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
|
||||
|
|
@ -105,6 +107,7 @@ static struct uartinit uartinit_data[] __initdata = {
|
|||
.ck_mode_mask =
|
||||
LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
|
||||
.pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
|
||||
.mapbase = LPC32XX_UART3_BASE,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
|
||||
|
|
@ -113,6 +116,7 @@ static struct uartinit uartinit_data[] __initdata = {
|
|||
.ck_mode_mask =
|
||||
LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
|
||||
.pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
|
||||
.mapbase = LPC32XX_UART4_BASE,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
|
||||
|
|
@ -121,6 +125,7 @@ static struct uartinit uartinit_data[] __initdata = {
|
|||
.ck_mode_mask =
|
||||
LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
|
||||
.pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
|
||||
.mapbase = LPC32XX_UART6_BASE,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
|
@ -165,11 +170,24 @@ void __init lpc32xx_serial_init(void)
|
|||
|
||||
/* pre-UART clock divider set to 1 */
|
||||
__raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
|
||||
|
||||
/*
|
||||
* Force a flush of the RX FIFOs to work around a
|
||||
* HW bug
|
||||
*/
|
||||
puart = uartinit_data[i].mapbase;
|
||||
__raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
|
||||
__raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
|
||||
j = LPC32XX_SUART_FIFO_SIZE;
|
||||
while (j--)
|
||||
tmp = __raw_readl(
|
||||
LPC32XX_UART_DLL_FIFO(puart));
|
||||
__raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
|
||||
}
|
||||
|
||||
/* This needs to be done after all UART clocks are setup */
|
||||
__raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
|
||||
for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) {
|
||||
for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
|
||||
/* Force a flush of the RX FIFOs to work around a HW bug */
|
||||
puart = serial_std_platform_data[i].mapbase;
|
||||
__raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
|
||||
|
|
|
|||
|
|
@ -17,7 +17,6 @@
|
|||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
|
|
|||
|
|
@ -24,7 +24,6 @@
|
|||
#include <mach/dma.h>
|
||||
#include <mach/devices.h>
|
||||
#include <mach/mfp.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <mach/pxa168.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/smc91x.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
|
|
|||
|
|
@ -416,13 +416,13 @@ static void __init innovator_init(void)
|
|||
#ifdef CONFIG_ARCH_OMAP15XX
|
||||
if (cpu_is_omap1510()) {
|
||||
omap1_usb_init(&innovator1510_usb_config);
|
||||
innovator_config[1].data = &innovator1510_lcd_config;
|
||||
innovator_config[0].data = &innovator1510_lcd_config;
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_OMAP16XX
|
||||
if (cpu_is_omap1610()) {
|
||||
omap1_usb_init(&h2_usb_config);
|
||||
innovator_config[1].data = &innovator1610_lcd_config;
|
||||
innovator_config[0].data = &innovator1610_lcd_config;
|
||||
}
|
||||
#endif
|
||||
omap_board_config = innovator_config;
|
||||
|
|
|
|||
|
|
@ -364,8 +364,8 @@ config OMAP3_SDRC_AC_TIMING
|
|||
going on could result in system crashes;
|
||||
|
||||
config OMAP4_ERRATA_I688
|
||||
bool "OMAP4 errata: Async Bridge Corruption (BROKEN)"
|
||||
depends on ARCH_OMAP4 && BROKEN
|
||||
bool "OMAP4 errata: Async Bridge Corruption"
|
||||
depends on ARCH_OMAP4
|
||||
select ARCH_HAS_BARRIERS
|
||||
help
|
||||
If a data is stalled inside asynchronous bridge because of back
|
||||
|
|
|
|||
|
|
@ -371,7 +371,11 @@ static void n8x0_mmc_callback(void *data, u8 card_mask)
|
|||
else
|
||||
*openp = 0;
|
||||
|
||||
#ifdef CONFIG_MMC_OMAP
|
||||
omap_mmc_notify_cover_event(mmc_device, index, *openp);
|
||||
#else
|
||||
pr_warn("MMC: notify cover event not available\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
static int n8x0_mmc_late_init(struct device *dev)
|
||||
|
|
|
|||
|
|
@ -381,7 +381,7 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
|
|||
gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "EN_DVI");
|
||||
|
||||
/* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
|
||||
gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
|
||||
gpio_leds[0].gpio = gpio + TWL4030_GPIO_MAX + 1;
|
||||
|
||||
platform_device_register(&leds_gpio);
|
||||
|
||||
|
|
|
|||
|
|
@ -132,6 +132,7 @@ void omap3_map_io(void);
|
|||
void am33xx_map_io(void);
|
||||
void omap4_map_io(void);
|
||||
void ti81xx_map_io(void);
|
||||
void omap_barriers_init(void);
|
||||
|
||||
/**
|
||||
* omap_test_timeout - busy-loop, testing a condition
|
||||
|
|
|
|||
|
|
@ -65,7 +65,6 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
|
|||
struct timespec ts_preidle, ts_postidle, ts_idle;
|
||||
u32 cpu1_state;
|
||||
int idle_time;
|
||||
int new_state_idx;
|
||||
int cpu_id = smp_processor_id();
|
||||
|
||||
/* Used to keep track of the total time in idle */
|
||||
|
|
@ -84,8 +83,8 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
|
|||
*/
|
||||
cpu1_state = pwrdm_read_pwrst(cpu1_pd);
|
||||
if (cpu1_state != PWRDM_POWER_OFF) {
|
||||
new_state_idx = drv->safe_state_index;
|
||||
cx = cpuidle_get_statedata(&dev->states_usage[new_state_idx]);
|
||||
index = drv->safe_state_index;
|
||||
cx = cpuidle_get_statedata(&dev->states_usage[index]);
|
||||
}
|
||||
|
||||
if (index > 0)
|
||||
|
|
|
|||
|
|
@ -19,6 +19,8 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/smsc911x.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
|
||||
#include <plat/board.h>
|
||||
#include <plat/gpmc.h>
|
||||
|
|
@ -42,6 +44,50 @@ static struct smsc911x_platform_config gpmc_smsc911x_config = {
|
|||
.flags = SMSC911X_USE_16BIT,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply gpmc_smsc911x_supply[] = {
|
||||
REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
|
||||
REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
|
||||
};
|
||||
|
||||
/* Generic regulator definition to satisfy smsc911x */
|
||||
static struct regulator_init_data gpmc_smsc911x_reg_init_data = {
|
||||
.constraints = {
|
||||
.min_uV = 3300000,
|
||||
.max_uV = 3300000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(gpmc_smsc911x_supply),
|
||||
.consumer_supplies = gpmc_smsc911x_supply,
|
||||
};
|
||||
|
||||
static struct fixed_voltage_config gpmc_smsc911x_fixed_reg_data = {
|
||||
.supply_name = "gpmc_smsc911x",
|
||||
.microvolts = 3300000,
|
||||
.gpio = -EINVAL,
|
||||
.startup_delay = 0,
|
||||
.enable_high = 0,
|
||||
.enabled_at_boot = 1,
|
||||
.init_data = &gpmc_smsc911x_reg_init_data,
|
||||
};
|
||||
|
||||
/*
|
||||
* Platform device id of 42 is a temporary fix to avoid conflicts
|
||||
* with other reg-fixed-voltage devices. The real fix should
|
||||
* involve the driver core providing a way of dynamically
|
||||
* assigning a unique id on registration for platform devices
|
||||
* in the same name space.
|
||||
*/
|
||||
static struct platform_device gpmc_smsc911x_regulator = {
|
||||
.name = "reg-fixed-voltage",
|
||||
.id = 42,
|
||||
.dev = {
|
||||
.platform_data = &gpmc_smsc911x_fixed_reg_data,
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* Initialize smsc911x device connected to the GPMC. Note that we
|
||||
* assume that pin multiplexing is done in the board-*.c file,
|
||||
|
|
@ -55,6 +101,12 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
|
|||
|
||||
gpmc_cfg = board_data;
|
||||
|
||||
ret = platform_device_register(&gpmc_smsc911x_regulator);
|
||||
if (ret < 0) {
|
||||
pr_err("Unable to register smsc911x regulators: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
|
||||
pr_err("Failed to request GPMC mem region\n");
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -428,6 +428,7 @@ static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int omap_hsmmc_done;
|
||||
#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
|
||||
|
||||
void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
|
||||
|
|
@ -491,6 +492,11 @@ void omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
|
|||
{
|
||||
u32 reg;
|
||||
|
||||
if (omap_hsmmc_done)
|
||||
return;
|
||||
|
||||
omap_hsmmc_done = 1;
|
||||
|
||||
if (!cpu_is_omap44xx()) {
|
||||
if (cpu_is_omap2430()) {
|
||||
control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
|
||||
|
|
|
|||
|
|
@ -307,6 +307,7 @@ void __init omapam33xx_map_common_io(void)
|
|||
void __init omap44xx_map_common_io(void)
|
||||
{
|
||||
iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
|
||||
omap_barriers_init();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -281,8 +281,16 @@ static struct omap_mbox mbox_iva_info = {
|
|||
.ops = &omap2_mbox_ops,
|
||||
.priv = &omap2_mbox_iva_priv,
|
||||
};
|
||||
#endif
|
||||
|
||||
struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
|
||||
#ifdef CONFIG_ARCH_OMAP2
|
||||
struct omap_mbox *omap2_mboxes[] = {
|
||||
&mbox_dsp_info,
|
||||
#ifdef CONFIG_SOC_OMAP2420
|
||||
&mbox_iva_info,
|
||||
#endif
|
||||
NULL
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP4)
|
||||
|
|
@ -412,7 +420,8 @@ static void __exit omap2_mbox_exit(void)
|
|||
platform_driver_unregister(&omap2_mbox_driver);
|
||||
}
|
||||
|
||||
module_init(omap2_mbox_init);
|
||||
/* must be ready before omap3isp is probed */
|
||||
subsys_initcall(omap2_mbox_init);
|
||||
module_exit(omap2_mbox_exit);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
|
|||
|
|
@ -218,7 +218,7 @@ static int _omap_mux_get_by_name(struct omap_mux_partition *partition,
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
static int __init
|
||||
static int
|
||||
omap_mux_get_by_name(const char *muxname,
|
||||
struct omap_mux_partition **found_partition,
|
||||
struct omap_mux **found_mux)
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
|
||||
#include <plat/irqs.h>
|
||||
#include <plat/sram.h>
|
||||
#include <plat/omap-secure.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/omap-wakeupgen.h>
|
||||
|
|
@ -43,6 +44,9 @@ static void __iomem *sar_ram_base;
|
|||
|
||||
void __iomem *dram_sync, *sram_sync;
|
||||
|
||||
static phys_addr_t paddr;
|
||||
static u32 size;
|
||||
|
||||
void omap_bus_sync(void)
|
||||
{
|
||||
if (dram_sync && sram_sync) {
|
||||
|
|
@ -52,18 +56,20 @@ void omap_bus_sync(void)
|
|||
}
|
||||
}
|
||||
|
||||
static int __init omap_barriers_init(void)
|
||||
/* Steal one page physical memory for barrier implementation */
|
||||
int __init omap_barrier_reserve_memblock(void)
|
||||
{
|
||||
struct map_desc dram_io_desc[1];
|
||||
phys_addr_t paddr;
|
||||
u32 size;
|
||||
|
||||
if (!cpu_is_omap44xx())
|
||||
return -ENODEV;
|
||||
|
||||
size = ALIGN(PAGE_SIZE, SZ_1M);
|
||||
paddr = arm_memblock_steal(size, SZ_1M);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __init omap_barriers_init(void)
|
||||
{
|
||||
struct map_desc dram_io_desc[1];
|
||||
|
||||
dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
|
||||
dram_io_desc[0].pfn = __phys_to_pfn(paddr);
|
||||
dram_io_desc[0].length = size;
|
||||
|
|
@ -75,9 +81,10 @@ static int __init omap_barriers_init(void)
|
|||
pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
|
||||
(long long) paddr, dram_io_desc[0].virtual);
|
||||
|
||||
return 0;
|
||||
}
|
||||
core_initcall(omap_barriers_init);
|
||||
#else
|
||||
void __init omap_barriers_init(void)
|
||||
{}
|
||||
#endif
|
||||
|
||||
void __init gic_init_irq(void)
|
||||
|
|
|
|||
|
|
@ -174,14 +174,17 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
|
|||
freq = clk->rate;
|
||||
clk_put(clk);
|
||||
|
||||
rcu_read_lock();
|
||||
opp = opp_find_freq_ceil(dev, &freq);
|
||||
if (IS_ERR(opp)) {
|
||||
rcu_read_unlock();
|
||||
pr_err("%s: unable to find boot up OPP for vdd_%s\n",
|
||||
__func__, vdd_name);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
bootup_volt = opp_get_voltage(opp);
|
||||
rcu_read_unlock();
|
||||
if (!bootup_volt) {
|
||||
pr_err("%s: unable to find voltage corresponding "
|
||||
"to the bootup OPP for vdd_%s\n", __func__, vdd_name);
|
||||
|
|
|
|||
|
|
@ -486,7 +486,7 @@ static void setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
|
|||
void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
|
||||
{
|
||||
struct omap_hwmod *oh[2];
|
||||
struct omap_device *od;
|
||||
struct platform_device *pdev;
|
||||
int bus_id = -1;
|
||||
int i;
|
||||
|
||||
|
|
@ -522,11 +522,11 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
|
|||
return;
|
||||
}
|
||||
|
||||
od = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 2,
|
||||
pdev = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 2,
|
||||
(void *)&usbhs_data, sizeof(usbhs_data),
|
||||
omap_uhhtll_latency,
|
||||
ARRAY_SIZE(omap_uhhtll_latency), false);
|
||||
if (IS_ERR(od)) {
|
||||
if (IS_ERR(pdev)) {
|
||||
pr_err("Could not build hwmod devices %s,%s\n",
|
||||
USBHS_UHH_HWMODNAME, USBHS_TLL_HWMODNAME);
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -45,6 +45,7 @@
|
|||
#include <mach/hx4700.h>
|
||||
#include <mach/irda.h>
|
||||
|
||||
#include <sound/ak4641.h>
|
||||
#include <video/platform_lcd.h>
|
||||
#include <video/w100fb.h>
|
||||
|
||||
|
|
@ -764,6 +765,28 @@ static struct i2c_board_info __initdata pi2c_board_info[] = {
|
|||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* Asahi Kasei AK4641 on I2C
|
||||
*/
|
||||
|
||||
static struct ak4641_platform_data ak4641_info = {
|
||||
.gpio_power = GPIO27_HX4700_CODEC_ON,
|
||||
.gpio_npdn = GPIO109_HX4700_CODEC_nPDN,
|
||||
};
|
||||
|
||||
static struct i2c_board_info i2c_board_info[] __initdata = {
|
||||
{
|
||||
I2C_BOARD_INFO("ak4641", 0x12),
|
||||
.platform_data = &ak4641_info,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device audio = {
|
||||
.name = "hx4700-audio",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* PCMCIA
|
||||
*/
|
||||
|
|
@ -790,6 +813,7 @@ static struct platform_device *devices[] __initdata = {
|
|||
&gpio_vbus,
|
||||
&power_supply,
|
||||
&strataflash,
|
||||
&audio,
|
||||
&pcmcia,
|
||||
};
|
||||
|
||||
|
|
@ -827,6 +851,7 @@ static void __init hx4700_init(void)
|
|||
pxa_set_ficp_info(&ficp_info);
|
||||
pxa27x_set_i2c_power_info(NULL);
|
||||
pxa_set_i2c_info(NULL);
|
||||
i2c_register_board_info(0, ARRAY_AND_SIZE(i2c_board_info));
|
||||
i2c_register_board_info(1, ARRAY_AND_SIZE(pi2c_board_info));
|
||||
pxa2xx_set_spi_info(2, &pxa_ssp2_master_info);
|
||||
spi_register_board_info(ARRAY_AND_SIZE(tsc2046_board_info));
|
||||
|
|
|
|||
|
|
@ -25,7 +25,6 @@
|
|||
#include <linux/suspend.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/suspend.h>
|
||||
|
|
|
|||
|
|
@ -22,7 +22,6 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/i2c/pxa-i2c.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
#include <mach/hardware.h>
|
||||
|
|
|
|||
|
|
@ -15,7 +15,6 @@
|
|||
#include <linux/i2c.h>
|
||||
#include <linux/i2c/pxa-i2c.h>
|
||||
#include <linux/mfd/88pm860x.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
|
|
|||
|
|
@ -168,6 +168,7 @@ struct battery_thresh sharpsl_battery_levels_noac[] = {
|
|||
#define MAXCTRL_SEL_SH 4
|
||||
#define MAXCTRL_STR (1u << 7)
|
||||
|
||||
extern int max1111_read_channel(int);
|
||||
/*
|
||||
* Read MAX1111 ADC
|
||||
*/
|
||||
|
|
@ -177,8 +178,6 @@ int sharpsl_pm_pxa_read_max1111(int channel)
|
|||
if (machine_is_tosa())
|
||||
return 0;
|
||||
|
||||
extern int max1111_read_channel(int);
|
||||
|
||||
/* max1111 accepts channels from 0-3, however,
|
||||
* it is encoded from 0-7 here in the code.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -172,10 +172,9 @@ static int spitz_should_wakeup(unsigned int resume_on_alarm)
|
|||
static unsigned long spitz_charger_wakeup(void)
|
||||
{
|
||||
unsigned long ret;
|
||||
ret = (!gpio_get_value(SPITZ_GPIO_KEY_INT)
|
||||
ret = ((!gpio_get_value(SPITZ_GPIO_KEY_INT)
|
||||
<< GPIO_bit(SPITZ_GPIO_KEY_INT))
|
||||
| (!gpio_get_value(SPITZ_GPIO_SYNC)
|
||||
<< GPIO_bit(SPITZ_GPIO_SYNC));
|
||||
| gpio_get_value(SPITZ_GPIO_SYNC));
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -162,7 +162,7 @@ static int h1940_gpiolib_latch_get(struct gpio_chip *chip,
|
|||
return (latch_state >> (offset + 16)) & 1;
|
||||
}
|
||||
|
||||
struct gpio_chip h1940_latch_gpiochip = {
|
||||
static struct gpio_chip h1940_latch_gpiochip = {
|
||||
.base = H1940_LATCH_GPIO(0),
|
||||
.owner = THIS_MODULE,
|
||||
.label = "H1940_LATCH",
|
||||
|
|
@ -304,7 +304,7 @@ static const struct s3c_adc_bat_thresh bat_lut_acin[] = {
|
|||
{ .volt = 3841, .cur = 0, .level = 0},
|
||||
};
|
||||
|
||||
int h1940_bat_init(void)
|
||||
static int h1940_bat_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
|
|
@ -317,17 +317,17 @@ int h1940_bat_init(void)
|
|||
|
||||
}
|
||||
|
||||
void h1940_bat_exit(void)
|
||||
static void h1940_bat_exit(void)
|
||||
{
|
||||
gpio_free(H1940_LATCH_SM803_ENABLE);
|
||||
}
|
||||
|
||||
void h1940_enable_charger(void)
|
||||
static void h1940_enable_charger(void)
|
||||
{
|
||||
gpio_set_value(H1940_LATCH_SM803_ENABLE, 1);
|
||||
}
|
||||
|
||||
void h1940_disable_charger(void)
|
||||
static void h1940_disable_charger(void)
|
||||
{
|
||||
gpio_set_value(H1940_LATCH_SM803_ENABLE, 0);
|
||||
}
|
||||
|
|
@ -364,7 +364,7 @@ static struct platform_device h1940_battery = {
|
|||
},
|
||||
};
|
||||
|
||||
DEFINE_SPINLOCK(h1940_blink_spin);
|
||||
static DEFINE_SPINLOCK(h1940_blink_spin);
|
||||
|
||||
int h1940_led_blink_set(unsigned gpio, int state,
|
||||
unsigned long *delay_on, unsigned long *delay_off)
|
||||
|
|
|
|||
|
|
@ -132,12 +132,6 @@ static struct clk hsmmc0_clk = {
|
|||
.ctrlbit = S3C2416_HCLKCON_HSMMC0,
|
||||
};
|
||||
|
||||
void __init_or_cpufreq s3c2416_setup_clocks(void)
|
||||
{
|
||||
s3c2443_common_setup_clocks(s3c2416_get_pll);
|
||||
}
|
||||
|
||||
|
||||
static struct clksrc_clk *clksrcs[] __initdata = {
|
||||
&hsspi_eplldiv,
|
||||
&hsspi_mux,
|
||||
|
|
|
|||
|
|
@ -125,7 +125,7 @@ static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = {
|
|||
}
|
||||
};
|
||||
|
||||
void smdk2416_hsudc_gpio_init(void)
|
||||
static void smdk2416_hsudc_gpio_init(void)
|
||||
{
|
||||
s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_setpull(S3C2410_GPF(2), S3C_GPIO_PULL_NONE);
|
||||
|
|
@ -133,20 +133,20 @@ void smdk2416_hsudc_gpio_init(void)
|
|||
s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 0);
|
||||
}
|
||||
|
||||
void smdk2416_hsudc_gpio_uninit(void)
|
||||
static void smdk2416_hsudc_gpio_uninit(void)
|
||||
{
|
||||
s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 1);
|
||||
s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_NONE);
|
||||
s3c_gpio_cfgpin(S3C2410_GPH(14), S3C_GPIO_SFN(0));
|
||||
}
|
||||
|
||||
struct s3c24xx_hsudc_platdata smdk2416_hsudc_platdata = {
|
||||
static struct s3c24xx_hsudc_platdata smdk2416_hsudc_platdata = {
|
||||
.epnum = 9,
|
||||
.gpio_init = smdk2416_hsudc_gpio_init,
|
||||
.gpio_uninit = smdk2416_hsudc_gpio_uninit,
|
||||
};
|
||||
|
||||
struct s3c_fb_pd_win smdk2416_fb_win[] = {
|
||||
static struct s3c_fb_pd_win smdk2416_fb_win[] = {
|
||||
[0] = {
|
||||
/* think this is the same as the smdk6410 */
|
||||
.win_mode = {
|
||||
|
|
|
|||
|
|
@ -258,7 +258,7 @@ static struct pcf50633_bl_platform_data gta02_backlight_data = {
|
|||
.ramp_time = 5,
|
||||
};
|
||||
|
||||
struct pcf50633_platform_data gta02_pcf_pdata = {
|
||||
static struct pcf50633_platform_data gta02_pcf_pdata = {
|
||||
.resumers = {
|
||||
[0] = PCF50633_INT1_USBINS |
|
||||
PCF50633_INT1_USBREM |
|
||||
|
|
@ -404,7 +404,7 @@ static struct platform_device gta02_nor_flash = {
|
|||
};
|
||||
|
||||
|
||||
struct platform_device s3c24xx_pwm_device = {
|
||||
static struct platform_device s3c24xx_pwm_device = {
|
||||
.name = "s3c24xx_pwm",
|
||||
.num_resources = 0,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -217,7 +217,7 @@ static const struct s3c_adc_bat_thresh bat_lut_acin[] = {
|
|||
{ .volt = 3820, .cur = 0, .level = 0},
|
||||
};
|
||||
|
||||
int rx1950_bat_init(void)
|
||||
static int rx1950_bat_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
|
|
@ -236,25 +236,25 @@ err_gpio1:
|
|||
return ret;
|
||||
}
|
||||
|
||||
void rx1950_bat_exit(void)
|
||||
static void rx1950_bat_exit(void)
|
||||
{
|
||||
gpio_free(S3C2410_GPJ(2));
|
||||
gpio_free(S3C2410_GPJ(3));
|
||||
}
|
||||
|
||||
void rx1950_enable_charger(void)
|
||||
static void rx1950_enable_charger(void)
|
||||
{
|
||||
gpio_direction_output(S3C2410_GPJ(2), 1);
|
||||
gpio_direction_output(S3C2410_GPJ(3), 1);
|
||||
}
|
||||
|
||||
void rx1950_disable_charger(void)
|
||||
static void rx1950_disable_charger(void)
|
||||
{
|
||||
gpio_direction_output(S3C2410_GPJ(2), 0);
|
||||
gpio_direction_output(S3C2410_GPJ(3), 0);
|
||||
}
|
||||
|
||||
DEFINE_SPINLOCK(rx1950_blink_spin);
|
||||
static DEFINE_SPINLOCK(rx1950_blink_spin);
|
||||
|
||||
static int rx1950_led_blink_set(unsigned gpio, int state,
|
||||
unsigned long *delay_on, unsigned long *delay_off)
|
||||
|
|
@ -382,7 +382,7 @@ static struct s3c2410fb_mach_info rx1950_lcd_cfg = {
|
|||
|
||||
static struct pwm_device *lcd_pwm;
|
||||
|
||||
void rx1950_lcd_power(int enable)
|
||||
static void rx1950_lcd_power(int enable)
|
||||
{
|
||||
int i;
|
||||
static int enabled;
|
||||
|
|
|
|||
|
|
@ -25,8 +25,6 @@ void s3c64xx_setup_clocks(void);
|
|||
|
||||
void s3c64xx_restart(char mode, const char *cmd);
|
||||
|
||||
extern struct syscore_ops s3c64xx_irq_syscore_ops;
|
||||
|
||||
#ifdef CONFIG_CPU_S3C6400
|
||||
|
||||
extern int s3c6400_init(void);
|
||||
|
|
|
|||
|
|
@ -96,7 +96,7 @@ static void s3c64xx_irq_pm_resume(void)
|
|||
S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
|
||||
}
|
||||
|
||||
struct syscore_ops s3c64xx_irq_syscore_ops = {
|
||||
static struct syscore_ops s3c64xx_irq_syscore_ops = {
|
||||
.suspend = s3c64xx_irq_pm_suspend,
|
||||
.resume = s3c64xx_irq_pm_resume,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@ static const u32 clock_table[][3] = {
|
|||
{L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
|
||||
};
|
||||
|
||||
unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
|
||||
static unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
|
||||
{
|
||||
unsigned long rate = clk_get_rate(clk->parent);
|
||||
u32 clkdiv;
|
||||
|
|
@ -84,7 +84,8 @@ unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
|
|||
return rate / (clkdiv + 1);
|
||||
}
|
||||
|
||||
unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate)
|
||||
static unsigned long s5p64x0_armclk_round_rate(struct clk *clk,
|
||||
unsigned long rate)
|
||||
{
|
||||
u32 iter;
|
||||
|
||||
|
|
@ -96,7 +97,7 @@ unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate)
|
|||
return clock_table[ARRAY_SIZE(clock_table) - 1][0];
|
||||
}
|
||||
|
||||
int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
|
||||
static int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
u32 round_tmp;
|
||||
u32 iter;
|
||||
|
|
@ -148,7 +149,7 @@ int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
|
|||
return 0;
|
||||
}
|
||||
|
||||
struct clk_ops s5p64x0_clkarm_ops = {
|
||||
static struct clk_ops s5p64x0_clkarm_ops = {
|
||||
.get_rate = s5p64x0_armclk_get_rate,
|
||||
.set_rate = s5p64x0_armclk_set_rate,
|
||||
.round_rate = s5p64x0_armclk_round_rate,
|
||||
|
|
@ -173,7 +174,7 @@ struct clksrc_clk clk_dout_mpll = {
|
|||
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 },
|
||||
};
|
||||
|
||||
struct clk *clkset_hclk_low_list[] = {
|
||||
static struct clk *clkset_hclk_low_list[] = {
|
||||
&clk_mout_apll.clk,
|
||||
&clk_mout_mpll.clk,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@
|
|||
|
||||
static u64 dma_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
u8 s5p6440_pdma_peri[] = {
|
||||
static u8 s5p6440_pdma_peri[] = {
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART1_RX,
|
||||
|
|
@ -63,12 +63,12 @@ u8 s5p6440_pdma_peri[] = {
|
|||
DMACH_SPI1_RX,
|
||||
};
|
||||
|
||||
struct dma_pl330_platdata s5p6440_pdma_pdata = {
|
||||
static struct dma_pl330_platdata s5p6440_pdma_pdata = {
|
||||
.nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
|
||||
.peri_id = s5p6440_pdma_peri,
|
||||
};
|
||||
|
||||
u8 s5p6450_pdma_peri[] = {
|
||||
static u8 s5p6450_pdma_peri[] = {
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART1_RX,
|
||||
|
|
@ -103,13 +103,13 @@ u8 s5p6450_pdma_peri[] = {
|
|||
DMACH_UART5_TX,
|
||||
};
|
||||
|
||||
struct dma_pl330_platdata s5p6450_pdma_pdata = {
|
||||
static struct dma_pl330_platdata s5p6450_pdma_pdata = {
|
||||
.nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
|
||||
.peri_id = s5p6450_pdma_peri,
|
||||
};
|
||||
|
||||
AMBA_AHB_DEVICE(s5p64x0_pdma, "dma-pl330", 0x00041330, S5P64X0_PA_PDMA,
|
||||
{IRQ_DMA0}, NULL);
|
||||
static AMBA_AHB_DEVICE(s5p64x0_pdma, "dma-pl330", 0x00041330,
|
||||
S5P64X0_PA_PDMA, {IRQ_DMA0}, NULL);
|
||||
|
||||
static int __init s5p64x0_dma_init(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -22,16 +22,9 @@ extern struct clksrc_clk clk_mout_epll;
|
|||
extern int s5p64x0_epll_enable(struct clk *clk, int enable);
|
||||
extern unsigned long s5p64x0_epll_get_rate(struct clk *clk);
|
||||
|
||||
extern unsigned long s5p64x0_armclk_get_rate(struct clk *clk);
|
||||
extern unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate);
|
||||
extern int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate);
|
||||
|
||||
extern struct clk_ops s5p64x0_clkarm_ops;
|
||||
|
||||
extern struct clksrc_clk clk_armclk;
|
||||
extern struct clksrc_clk clk_dout_mpll;
|
||||
|
||||
extern struct clk *clkset_hclk_low_list[];
|
||||
extern struct clksrc_sources clkset_hclk_low;
|
||||
|
||||
extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable);
|
||||
|
|
|
|||
|
|
@ -170,7 +170,7 @@ static struct clk *clk_src_mout_am_list[] = {
|
|||
[1] = &clk_div_apll2.clk,
|
||||
};
|
||||
|
||||
struct clksrc_sources clk_src_mout_am = {
|
||||
static struct clksrc_sources clk_src_mout_am = {
|
||||
.sources = clk_src_mout_am_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_mout_am_list),
|
||||
};
|
||||
|
|
@ -212,7 +212,7 @@ static struct clk *clk_src_mout_onenand_list[] = {
|
|||
[1] = &clk_div_d1_bus.clk,
|
||||
};
|
||||
|
||||
struct clksrc_sources clk_src_mout_onenand = {
|
||||
static struct clksrc_sources clk_src_mout_onenand = {
|
||||
.sources = clk_src_mout_onenand_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list),
|
||||
};
|
||||
|
|
@ -756,7 +756,7 @@ static struct clk *clk_src_group1_list[] = {
|
|||
[3] = &clk_mout_hpll.clk,
|
||||
};
|
||||
|
||||
struct clksrc_sources clk_src_group1 = {
|
||||
static struct clksrc_sources clk_src_group1 = {
|
||||
.sources = clk_src_group1_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_group1_list),
|
||||
};
|
||||
|
|
@ -766,7 +766,7 @@ static struct clk *clk_src_group2_list[] = {
|
|||
[1] = &clk_div_mpll.clk,
|
||||
};
|
||||
|
||||
struct clksrc_sources clk_src_group2 = {
|
||||
static struct clksrc_sources clk_src_group2 = {
|
||||
.sources = clk_src_group2_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_group2_list),
|
||||
};
|
||||
|
|
@ -780,7 +780,7 @@ static struct clk *clk_src_group3_list[] = {
|
|||
[5] = &clk_mout_hpll.clk,
|
||||
};
|
||||
|
||||
struct clksrc_sources clk_src_group3 = {
|
||||
static struct clksrc_sources clk_src_group3 = {
|
||||
.sources = clk_src_group3_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_group3_list),
|
||||
};
|
||||
|
|
@ -806,7 +806,7 @@ static struct clk *clk_src_group4_list[] = {
|
|||
[5] = &clk_mout_hpll.clk,
|
||||
};
|
||||
|
||||
struct clksrc_sources clk_src_group4 = {
|
||||
static struct clksrc_sources clk_src_group4 = {
|
||||
.sources = clk_src_group4_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_group4_list),
|
||||
};
|
||||
|
|
@ -831,7 +831,7 @@ static struct clk *clk_src_group5_list[] = {
|
|||
[4] = &clk_mout_hpll.clk,
|
||||
};
|
||||
|
||||
struct clksrc_sources clk_src_group5 = {
|
||||
static struct clksrc_sources clk_src_group5 = {
|
||||
.sources = clk_src_group5_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_group5_list),
|
||||
};
|
||||
|
|
@ -854,7 +854,7 @@ static struct clk *clk_src_group6_list[] = {
|
|||
[2] = &clk_div_hdmi.clk,
|
||||
};
|
||||
|
||||
struct clksrc_sources clk_src_group6 = {
|
||||
static struct clksrc_sources clk_src_group6 = {
|
||||
.sources = clk_src_group6_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_group6_list),
|
||||
};
|
||||
|
|
@ -866,7 +866,7 @@ static struct clk *clk_src_group7_list[] = {
|
|||
[3] = &clk_vclk54m,
|
||||
};
|
||||
|
||||
struct clksrc_sources clk_src_group7 = {
|
||||
static struct clksrc_sources clk_src_group7 = {
|
||||
.sources = clk_src_group7_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_group7_list),
|
||||
};
|
||||
|
|
@ -877,7 +877,7 @@ static struct clk *clk_src_mmc0_list[] = {
|
|||
[2] = &clk_fin_epll,
|
||||
};
|
||||
|
||||
struct clksrc_sources clk_src_mmc0 = {
|
||||
static struct clksrc_sources clk_src_mmc0 = {
|
||||
.sources = clk_src_mmc0_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_mmc0_list),
|
||||
};
|
||||
|
|
@ -889,7 +889,7 @@ static struct clk *clk_src_mmc12_list[] = {
|
|||
[3] = &clk_mout_hpll.clk,
|
||||
};
|
||||
|
||||
struct clksrc_sources clk_src_mmc12 = {
|
||||
static struct clksrc_sources clk_src_mmc12 = {
|
||||
.sources = clk_src_mmc12_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_mmc12_list),
|
||||
};
|
||||
|
|
@ -901,7 +901,7 @@ static struct clk *clk_src_irda_usb_list[] = {
|
|||
[3] = &clk_mout_hpll.clk,
|
||||
};
|
||||
|
||||
struct clksrc_sources clk_src_irda_usb = {
|
||||
static struct clksrc_sources clk_src_irda_usb = {
|
||||
.sources = clk_src_irda_usb_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_irda_usb_list),
|
||||
};
|
||||
|
|
@ -912,7 +912,7 @@ static struct clk *clk_src_pwi_list[] = {
|
|||
[2] = &clk_div_mpll.clk,
|
||||
};
|
||||
|
||||
struct clksrc_sources clk_src_pwi = {
|
||||
static struct clksrc_sources clk_src_pwi = {
|
||||
.sources = clk_src_pwi_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_pwi_list),
|
||||
};
|
||||
|
|
@ -923,7 +923,7 @@ static struct clk *clk_sclk_spdif_list[] = {
|
|||
[2] = &clk_sclk_audio2.clk,
|
||||
};
|
||||
|
||||
struct clksrc_sources clk_src_sclk_spdif = {
|
||||
static struct clksrc_sources clk_src_sclk_spdif = {
|
||||
.sources = clk_sclk_spdif_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_sclk_spdif_list),
|
||||
};
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@
|
|||
|
||||
static u64 dma_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
u8 pdma0_peri[] = {
|
||||
static u8 pdma0_peri[] = {
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART1_RX,
|
||||
|
|
@ -68,15 +68,15 @@ u8 pdma0_peri[] = {
|
|||
DMACH_HSI_TX,
|
||||
};
|
||||
|
||||
struct dma_pl330_platdata s5pc100_pdma0_pdata = {
|
||||
static struct dma_pl330_platdata s5pc100_pdma0_pdata = {
|
||||
.nr_valid_peri = ARRAY_SIZE(pdma0_peri),
|
||||
.peri_id = pdma0_peri,
|
||||
};
|
||||
|
||||
AMBA_AHB_DEVICE(s5pc100_pdma0, "dma-pl330.0", 0x00041330, S5PC100_PA_PDMA0,
|
||||
{IRQ_PDMA0}, &s5pc100_pdma0_pdata);
|
||||
static AMBA_AHB_DEVICE(s5pc100_pdma0, "dma-pl330.0", 0x00041330,
|
||||
S5PC100_PA_PDMA0, {IRQ_PDMA0}, &s5pc100_pdma0_pdata);
|
||||
|
||||
u8 pdma1_peri[] = {
|
||||
static u8 pdma1_peri[] = {
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART1_RX,
|
||||
|
|
@ -109,13 +109,13 @@ u8 pdma1_peri[] = {
|
|||
DMACH_MSM_REQ3,
|
||||
};
|
||||
|
||||
struct dma_pl330_platdata s5pc100_pdma1_pdata = {
|
||||
static struct dma_pl330_platdata s5pc100_pdma1_pdata = {
|
||||
.nr_valid_peri = ARRAY_SIZE(pdma1_peri),
|
||||
.peri_id = pdma1_peri,
|
||||
};
|
||||
|
||||
AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330, S5PC100_PA_PDMA1,
|
||||
{IRQ_PDMA1}, &s5pc100_pdma1_pdata);
|
||||
static AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330,
|
||||
S5PC100_PA_PDMA1, {IRQ_PDMA1}, &s5pc100_pdma1_pdata);
|
||||
|
||||
static int __init s5pc100_dma_init(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@
|
|||
|
||||
static u64 dma_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
u8 pdma0_peri[] = {
|
||||
static u8 pdma0_peri[] = {
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART1_RX,
|
||||
|
|
@ -66,15 +66,15 @@ u8 pdma0_peri[] = {
|
|||
DMACH_SPDIF,
|
||||
};
|
||||
|
||||
struct dma_pl330_platdata s5pv210_pdma0_pdata = {
|
||||
static struct dma_pl330_platdata s5pv210_pdma0_pdata = {
|
||||
.nr_valid_peri = ARRAY_SIZE(pdma0_peri),
|
||||
.peri_id = pdma0_peri,
|
||||
};
|
||||
|
||||
AMBA_AHB_DEVICE(s5pv210_pdma0, "dma-pl330.0", 0x00041330, S5PV210_PA_PDMA0,
|
||||
{IRQ_PDMA0}, &s5pv210_pdma0_pdata);
|
||||
static AMBA_AHB_DEVICE(s5pv210_pdma0, "dma-pl330.0", 0x00041330,
|
||||
S5PV210_PA_PDMA0, {IRQ_PDMA0}, &s5pv210_pdma0_pdata);
|
||||
|
||||
u8 pdma1_peri[] = {
|
||||
static u8 pdma1_peri[] = {
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART1_RX,
|
||||
|
|
@ -109,13 +109,13 @@ u8 pdma1_peri[] = {
|
|||
DMACH_PCM2_TX,
|
||||
};
|
||||
|
||||
struct dma_pl330_platdata s5pv210_pdma1_pdata = {
|
||||
static struct dma_pl330_platdata s5pv210_pdma1_pdata = {
|
||||
.nr_valid_peri = ARRAY_SIZE(pdma1_peri),
|
||||
.peri_id = pdma1_peri,
|
||||
};
|
||||
|
||||
AMBA_AHB_DEVICE(s5pv210_pdma1, "dma-pl330.1", 0x00041330, S5PV210_PA_PDMA1,
|
||||
{IRQ_PDMA1}, &s5pv210_pdma1_pdata);
|
||||
static AMBA_AHB_DEVICE(s5pv210_pdma1, "dma-pl330.1", 0x00041330,
|
||||
S5PV210_PA_PDMA1, {IRQ_PDMA1}, &s5pv210_pdma1_pdata);
|
||||
|
||||
static int __init s5pv210_dma_init(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -844,7 +844,7 @@ static struct s5p_fimc_isp_info goni_camera_sensors[] = {
|
|||
},
|
||||
};
|
||||
|
||||
struct s5p_platform_fimc goni_fimc_md_platdata __initdata = {
|
||||
static struct s5p_platform_fimc goni_fimc_md_platdata __initdata = {
|
||||
.isp_info = goni_camera_sensors,
|
||||
.num_clients = ARRAY_SIZE(goni_camera_sensors),
|
||||
};
|
||||
|
|
|
|||
|
|
@ -140,7 +140,7 @@ static struct dm9000_plat_data smdkv210_dm9000_platdata = {
|
|||
.dev_addr = { 0x00, 0x09, 0xc0, 0xff, 0xec, 0x48 },
|
||||
};
|
||||
|
||||
struct platform_device smdkv210_dm9000 = {
|
||||
static struct platform_device smdkv210_dm9000 = {
|
||||
.name = "dm9000",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(smdkv210_dm9000_resources),
|
||||
|
|
|
|||
|
|
@ -69,6 +69,7 @@ void __init omap_reserve(void)
|
|||
omap_vram_reserve_sdram_memblock();
|
||||
omap_dsp_reserve_sdram_memblock();
|
||||
omap_secure_ram_reserve_memblock();
|
||||
omap_barrier_reserve_memblock();
|
||||
}
|
||||
|
||||
void __init omap_init_consistent_dma_size(void)
|
||||
|
|
|
|||
|
|
@ -10,4 +10,10 @@ static inline void omap_secure_ram_reserve_memblock(void)
|
|||
{ }
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OMAP4_ERRATA_I688
|
||||
extern int omap_barrier_reserve_memblock(void);
|
||||
#else
|
||||
static inline void omap_barrier_reserve_memblock(void)
|
||||
{ }
|
||||
#endif
|
||||
#endif /* __OMAP_SECURE_H__ */
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
|
|||
* elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
|
||||
* such directly equating the two source clocks is impossible.
|
||||
*/
|
||||
struct clk clk_mpllref = {
|
||||
static struct clk clk_mpllref = {
|
||||
.name = "mpllref",
|
||||
.parent = &clk_xtal,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,8 +9,8 @@ config PLAT_S5P
|
|||
bool
|
||||
depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
|
||||
default y
|
||||
select ARM_VIC if !ARCH_EXYNOS4
|
||||
select ARM_GIC if ARCH_EXYNOS4
|
||||
select ARM_VIC if !ARCH_EXYNOS
|
||||
select ARM_GIC if ARCH_EXYNOS
|
||||
select GIC_NON_BANKED if ARCH_EXYNOS4
|
||||
select NO_IOPORT
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
|
|
@ -40,6 +40,10 @@ config S5P_HRT
|
|||
help
|
||||
Use the High Resolution timer support
|
||||
|
||||
config S5P_DEV_UART
|
||||
def_bool y
|
||||
depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
|
||||
|
||||
config S5P_PM
|
||||
bool
|
||||
help
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@ obj- :=
|
|||
|
||||
# Core files
|
||||
|
||||
obj-y += dev-uart.o
|
||||
obj-y += clock.o
|
||||
obj-y += irq.o
|
||||
obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o
|
||||
|
|
@ -23,5 +22,7 @@ obj-$(CONFIG_S5P_SLEEP) += sleep.o
|
|||
obj-$(CONFIG_S5P_HRT) += s5p-time.o
|
||||
|
||||
# devices
|
||||
|
||||
obj-$(CONFIG_S5P_DEV_UART) += dev-uart.o
|
||||
obj-$(CONFIG_S5P_DEV_MFC) += dev-mfc.o
|
||||
obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o
|
||||
|
|
|
|||
|
|
@ -61,6 +61,20 @@ struct clk clk_fout_apll = {
|
|||
.id = -1,
|
||||
};
|
||||
|
||||
/* BPLL clock output */
|
||||
|
||||
struct clk clk_fout_bpll = {
|
||||
.name = "fout_bpll",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
/* CPLL clock output */
|
||||
|
||||
struct clk clk_fout_cpll = {
|
||||
.name = "fout_cpll",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
/* MPLL clock output
|
||||
* No need .ctrlbit, this is always on
|
||||
*/
|
||||
|
|
@ -101,6 +115,28 @@ struct clksrc_sources clk_src_apll = {
|
|||
.nr_sources = ARRAY_SIZE(clk_src_apll_list),
|
||||
};
|
||||
|
||||
/* Possible clock sources for BPLL Mux */
|
||||
static struct clk *clk_src_bpll_list[] = {
|
||||
[0] = &clk_fin_bpll,
|
||||
[1] = &clk_fout_bpll,
|
||||
};
|
||||
|
||||
struct clksrc_sources clk_src_bpll = {
|
||||
.sources = clk_src_bpll_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_bpll_list),
|
||||
};
|
||||
|
||||
/* Possible clock sources for CPLL Mux */
|
||||
static struct clk *clk_src_cpll_list[] = {
|
||||
[0] = &clk_fin_cpll,
|
||||
[1] = &clk_fout_cpll,
|
||||
};
|
||||
|
||||
struct clksrc_sources clk_src_cpll = {
|
||||
.sources = clk_src_cpll_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_cpll_list),
|
||||
};
|
||||
|
||||
/* Possible clock sources for MPLL Mux */
|
||||
static struct clk *clk_src_mpll_list[] = {
|
||||
[0] = &clk_fin_mpll,
|
||||
|
|
|
|||
|
|
@ -200,7 +200,7 @@ static struct irq_chip s5p_irq_vic_eint = {
|
|||
#endif
|
||||
};
|
||||
|
||||
int __init s5p_init_irq_eint(void)
|
||||
static int __init s5p_init_irq_eint(void)
|
||||
{
|
||||
int irq;
|
||||
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ struct s5p_gpioint_bank {
|
|||
void (*handler)(unsigned int, struct irq_desc *);
|
||||
};
|
||||
|
||||
LIST_HEAD(banks);
|
||||
static LIST_HEAD(banks);
|
||||
|
||||
static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -39,19 +39,32 @@ unsigned long s3c_irqwake_eintallow = 0xffffffffL;
|
|||
int s3c_irq_wake(struct irq_data *data, unsigned int state)
|
||||
{
|
||||
unsigned long irqbit;
|
||||
unsigned int irq_rtc_tic, irq_rtc_alarm;
|
||||
|
||||
#ifdef CONFIG_ARCH_EXYNOS
|
||||
if (soc_is_exynos5250()) {
|
||||
irq_rtc_tic = EXYNOS5_IRQ_RTC_TIC;
|
||||
irq_rtc_alarm = EXYNOS5_IRQ_RTC_ALARM;
|
||||
} else {
|
||||
irq_rtc_tic = EXYNOS4_IRQ_RTC_TIC;
|
||||
irq_rtc_alarm = EXYNOS4_IRQ_RTC_ALARM;
|
||||
}
|
||||
#else
|
||||
irq_rtc_tic = IRQ_RTC_TIC;
|
||||
irq_rtc_alarm = IRQ_RTC_ALARM;
|
||||
#endif
|
||||
|
||||
if (data->irq == irq_rtc_tic || data->irq == irq_rtc_alarm) {
|
||||
irqbit = 1 << (data->irq + 1 - irq_rtc_alarm);
|
||||
|
||||
switch (data->irq) {
|
||||
case IRQ_RTC_TIC:
|
||||
case IRQ_RTC_ALARM:
|
||||
irqbit = 1 << (data->irq + 1 - IRQ_RTC_ALARM);
|
||||
if (!state)
|
||||
s3c_irqwake_intmask |= irqbit;
|
||||
else
|
||||
s3c_irqwake_intmask &= ~irqbit;
|
||||
break;
|
||||
default:
|
||||
} else {
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -744,17 +744,6 @@ struct platform_device s3c_device_iis = {
|
|||
};
|
||||
#endif /* CONFIG_PLAT_S3C24XX */
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2440
|
||||
struct platform_device s3c2412_device_iis = {
|
||||
.name = "s3c2412-iis",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.dma_mask = &samsung_device_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
}
|
||||
};
|
||||
#endif /* CONFIG_CPU_S3C2440 */
|
||||
|
||||
/* IDE CFCON */
|
||||
|
||||
#ifdef CONFIG_SAMSUNG_DEV_IDE
|
||||
|
|
@ -1078,7 +1067,7 @@ static struct resource s5p_pmu_resource[] = {
|
|||
DEFINE_RES_IRQ(IRQ_PMU)
|
||||
};
|
||||
|
||||
struct platform_device s5p_device_pmu = {
|
||||
static struct platform_device s5p_device_pmu = {
|
||||
.name = "arm-pmu",
|
||||
.id = ARM_PMU_DEVICE_CPU,
|
||||
.num_resources = ARRAY_SIZE(s5p_pmu_resource),
|
||||
|
|
|
|||
|
|
@ -116,7 +116,7 @@ static inline int samsung_dmadev_flush(unsigned ch)
|
|||
return dmaengine_terminate_all((struct dma_chan *)ch);
|
||||
}
|
||||
|
||||
struct samsung_dma_ops dmadev_ops = {
|
||||
static struct samsung_dma_ops dmadev_ops = {
|
||||
.request = samsung_dmadev_request,
|
||||
.release = samsung_dmadev_release,
|
||||
.prepare = samsung_dmadev_prepare,
|
||||
|
|
|
|||
|
|
@ -42,6 +42,9 @@ extern unsigned long samsung_cpu_id;
|
|||
#define EXYNOS4412_CPU_ID 0xE4412200
|
||||
#define EXYNOS4_CPU_MASK 0xFFFE0000
|
||||
|
||||
#define EXYNOS5250_SOC_ID 0x43520000
|
||||
#define EXYNOS5_SOC_MASK 0xFFFFF000
|
||||
|
||||
#define IS_SAMSUNG_CPU(name, id, mask) \
|
||||
static inline int is_samsung_##name(void) \
|
||||
{ \
|
||||
|
|
@ -58,6 +61,7 @@ IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
|
|||
IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
|
||||
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
|
||||
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
|
||||
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
|
||||
|
||||
#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
|
||||
defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
|
||||
|
|
@ -120,6 +124,12 @@ IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
|
|||
#define EXYNOS4210_REV_1_0 (0x10)
|
||||
#define EXYNOS4210_REV_1_1 (0x11)
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS5250)
|
||||
# define soc_is_exynos5250() is_samsung_exynos5250()
|
||||
#else
|
||||
# define soc_is_exynos5250() 0
|
||||
#endif
|
||||
|
||||
#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
|
||||
|
||||
#ifndef MHZ
|
||||
|
|
|
|||
|
|
@ -26,6 +26,8 @@ struct s3c24xx_uart_resources {
|
|||
extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
|
||||
extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
|
||||
extern struct s3c24xx_uart_resources s5p_uart_resources[];
|
||||
extern struct s3c24xx_uart_resources exynos4_uart_resources[];
|
||||
extern struct s3c24xx_uart_resources exynos5_uart_resources[];
|
||||
|
||||
extern struct platform_device *s3c24xx_uart_devs[];
|
||||
extern struct platform_device *s3c24xx_uart_src[];
|
||||
|
|
|
|||
|
|
@ -82,6 +82,22 @@ enum dma_ch {
|
|||
DMACH_SLIMBUS4_TX,
|
||||
DMACH_SLIMBUS5_RX,
|
||||
DMACH_SLIMBUS5_TX,
|
||||
DMACH_MIPI_HSI0,
|
||||
DMACH_MIPI_HSI1,
|
||||
DMACH_MIPI_HSI2,
|
||||
DMACH_MIPI_HSI3,
|
||||
DMACH_MIPI_HSI4,
|
||||
DMACH_MIPI_HSI5,
|
||||
DMACH_MIPI_HSI6,
|
||||
DMACH_MIPI_HSI7,
|
||||
DMACH_MTOM_0,
|
||||
DMACH_MTOM_1,
|
||||
DMACH_MTOM_2,
|
||||
DMACH_MTOM_3,
|
||||
DMACH_MTOM_4,
|
||||
DMACH_MTOM_5,
|
||||
DMACH_MTOM_6,
|
||||
DMACH_MTOM_7,
|
||||
/* END Marker, also used to denote a reserved channel */
|
||||
DMACH_MAX,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@
|
|||
#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
|
||||
|
||||
#define clk_fin_apll clk_ext_xtal_mux
|
||||
#define clk_fin_bpll clk_ext_xtal_mux
|
||||
#define clk_fin_cpll clk_ext_xtal_mux
|
||||
#define clk_fin_mpll clk_ext_xtal_mux
|
||||
#define clk_fin_epll clk_ext_xtal_mux
|
||||
#define clk_fin_dpll clk_ext_xtal_mux
|
||||
|
|
@ -29,6 +31,8 @@ extern struct clk clk_xusbxti;
|
|||
extern struct clk clk_48m;
|
||||
extern struct clk s5p_clk_27m;
|
||||
extern struct clk clk_fout_apll;
|
||||
extern struct clk clk_fout_bpll;
|
||||
extern struct clk clk_fout_cpll;
|
||||
extern struct clk clk_fout_mpll;
|
||||
extern struct clk clk_fout_epll;
|
||||
extern struct clk clk_fout_dpll;
|
||||
|
|
@ -37,6 +41,8 @@ extern struct clk clk_arm;
|
|||
extern struct clk clk_vpll;
|
||||
|
||||
extern struct clksrc_sources clk_src_apll;
|
||||
extern struct clksrc_sources clk_src_bpll;
|
||||
extern struct clksrc_sources clk_src_cpll;
|
||||
extern struct clksrc_sources clk_src_mpll;
|
||||
extern struct clksrc_sources clk_src_epll;
|
||||
extern struct clksrc_sources clk_src_dpll;
|
||||
|
|
|
|||
|
|
@ -37,7 +37,9 @@ static void arch_detect_cpu(void);
|
|||
/* how many bytes we allow into the FIFO at a time in FIFO mode */
|
||||
#define FIFO_MAX (14)
|
||||
|
||||
#ifdef S3C_PA_UART
|
||||
#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
|
||||
#endif
|
||||
|
||||
static __inline__ void
|
||||
uart_wr(unsigned int reg, unsigned int val)
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/io.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/irq-vic-timer.h>
|
||||
#include <plat/regs-timer.h>
|
||||
|
||||
|
|
@ -57,6 +58,21 @@ void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq)
|
|||
struct irq_chip_type *ct;
|
||||
unsigned int i;
|
||||
|
||||
#ifdef CONFIG_ARCH_EXYNOS
|
||||
if (soc_is_exynos5250()) {
|
||||
pirq[0] = EXYNOS5_IRQ_TIMER0_VIC;
|
||||
pirq[1] = EXYNOS5_IRQ_TIMER1_VIC;
|
||||
pirq[2] = EXYNOS5_IRQ_TIMER2_VIC;
|
||||
pirq[3] = EXYNOS5_IRQ_TIMER3_VIC;
|
||||
pirq[4] = EXYNOS5_IRQ_TIMER4_VIC;
|
||||
} else {
|
||||
pirq[0] = EXYNOS4_IRQ_TIMER0_VIC;
|
||||
pirq[1] = EXYNOS4_IRQ_TIMER1_VIC;
|
||||
pirq[2] = EXYNOS4_IRQ_TIMER2_VIC;
|
||||
pirq[3] = EXYNOS4_IRQ_TIMER3_VIC;
|
||||
pirq[4] = EXYNOS4_IRQ_TIMER4_VIC;
|
||||
}
|
||||
#endif
|
||||
s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq,
|
||||
S3C64XX_TINT_CSTAT, handle_level_irq);
|
||||
|
||||
|
|
|
|||
|
|
@ -77,7 +77,6 @@ struct pt_regs {
|
|||
long syscallno; /* Syscall number (used by strace) */
|
||||
long dummy; /* Cheap alignment fix */
|
||||
};
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/* TODO: Rename this to REDZONE because that's what it is */
|
||||
#define STACK_FRAME_OVERHEAD 128 /* size of minimum stack frame */
|
||||
|
|
@ -87,6 +86,13 @@ struct pt_regs {
|
|||
#define user_stack_pointer(regs) ((unsigned long)(regs)->sp)
|
||||
#define profile_pc(regs) instruction_pointer(regs)
|
||||
|
||||
static inline long regs_return_value(struct pt_regs *regs)
|
||||
{
|
||||
return regs->gpr[11];
|
||||
}
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
* Offsets used by 'ptrace' system call interface.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
|
||||
#include <linux/init_task.h>
|
||||
#include <linux/mqueue.h>
|
||||
#include <linux/export.h>
|
||||
|
||||
static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
|
||||
static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
#include <linux/irq.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <linux/export.h>
|
||||
|
||||
#include <linux/irqflags.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -188,11 +188,9 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
|
|||
*/
|
||||
ret = -1L;
|
||||
|
||||
/* Are these regs right??? */
|
||||
if (unlikely(current->audit_context))
|
||||
audit_syscall_entry(audit_arch(), regs->syscallno,
|
||||
regs->gpr[3], regs->gpr[4],
|
||||
regs->gpr[5], regs->gpr[6]);
|
||||
audit_syscall_entry(audit_arch(), regs->syscallno,
|
||||
regs->gpr[3], regs->gpr[4],
|
||||
regs->gpr[5], regs->gpr[6]);
|
||||
|
||||
return ret ? : regs->syscallno;
|
||||
}
|
||||
|
|
@ -201,9 +199,7 @@ asmlinkage void do_syscall_trace_leave(struct pt_regs *regs)
|
|||
{
|
||||
int step;
|
||||
|
||||
if (unlikely(current->audit_context))
|
||||
audit_syscall_exit(AUDITSC_RESULT(regs->gpr[11]),
|
||||
regs->gpr[11]);
|
||||
audit_syscall_exit(regs);
|
||||
|
||||
step = test_thread_flag(TIF_SINGLESTEP);
|
||||
if (step || test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
|
|
|
|||
|
|
@ -31,7 +31,11 @@ ifdef CONFIG_64BIT
|
|||
UTS_MACHINE := parisc64
|
||||
CHECKFLAGS += -D__LP64__=1 -m64
|
||||
WIDTH := 64
|
||||
|
||||
# FIXME: if no default set, should really try to locate dynamically
|
||||
ifeq ($(CROSS_COMPILE),)
|
||||
CROSS_COMPILE := hppa64-linux-gnu-
|
||||
endif
|
||||
else # 32-bit
|
||||
WIDTH :=
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -227,6 +227,9 @@ config COMPAT
|
|||
config SYSVIPC_COMPAT
|
||||
def_bool y if COMPAT && SYSVIPC
|
||||
|
||||
config KEYS_COMPAT
|
||||
def_bool y if COMPAT && KEYS
|
||||
|
||||
config AUDIT_ARCH
|
||||
def_bool y
|
||||
|
||||
|
|
|
|||
|
|
@ -172,13 +172,6 @@ static inline int is_compat_task(void)
|
|||
return is_32bit_task();
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static inline int is_compat_task(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static inline void __user *arch_compat_alloc_user_space(long len)
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue