[Blackfin] arch: Functional power management support: Add support for cpu frequency scaling
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Michael Hennerich
Bryan Wu
parent
fe44193c55
commit
e6c91b64dd
|
|
@ -16,11 +16,35 @@
|
|||
#include <linux/irq.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/cpufreq.h>
|
||||
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
#ifdef CONFIG_CYCLES_CLOCKSOURCE
|
||||
|
||||
/* Accelerators for sched_clock()
|
||||
* convert from cycles(64bits) => nanoseconds (64bits)
|
||||
* basic equation:
|
||||
* ns = cycles / (freq / ns_per_sec)
|
||||
* ns = cycles * (ns_per_sec / freq)
|
||||
* ns = cycles * (10^9 / (cpu_khz * 10^3))
|
||||
* ns = cycles * (10^6 / cpu_khz)
|
||||
*
|
||||
* Then we use scaling math (suggested by george@mvista.com) to get:
|
||||
* ns = cycles * (10^6 * SC / cpu_khz) / SC
|
||||
* ns = cycles * cyc2ns_scale / SC
|
||||
*
|
||||
* And since SC is a constant power of two, we can convert the div
|
||||
* into a shift.
|
||||
*
|
||||
* We can use khz divisor instead of mhz to keep a better precision, since
|
||||
* cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
|
||||
* (mathieu.desnoyers@polymtl.ca)
|
||||
*
|
||||
* -johnstul@us.ibm.com "math is hard, lets go shopping!"
|
||||
*/
|
||||
|
||||
static unsigned long cyc2ns_scale;
|
||||
#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
|
||||
|
||||
|
|
@ -82,8 +106,9 @@ static void bfin_timer_set_mode(enum clock_event_mode mode,
|
|||
{
|
||||
switch (mode) {
|
||||
case CLOCK_EVT_MODE_PERIODIC: {
|
||||
unsigned long tcount = ((get_cclk() / (HZ * 1)) - 1);
|
||||
unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
|
||||
bfin_write_TCNTL(TMPWR);
|
||||
bfin_write_TSCALE(TIME_SCALE - 1);
|
||||
CSYNC();
|
||||
bfin_write_TPERIOD(tcount);
|
||||
bfin_write_TCOUNT(tcount);
|
||||
|
|
@ -92,6 +117,7 @@ static void bfin_timer_set_mode(enum clock_event_mode mode,
|
|||
break;
|
||||
}
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
bfin_write_TSCALE(0);
|
||||
bfin_write_TCOUNT(0);
|
||||
bfin_write_TCNTL(TMPWR | TMREN);
|
||||
CSYNC();
|
||||
|
|
@ -115,7 +141,7 @@ static void __init bfin_timer_init(void)
|
|||
/*
|
||||
* the TSCALE prescaler counter.
|
||||
*/
|
||||
bfin_write_TSCALE(0);
|
||||
bfin_write_TSCALE(TIME_SCALE - 1);
|
||||
bfin_write_TPERIOD(0);
|
||||
bfin_write_TCOUNT(0);
|
||||
|
||||
|
|
|
|||
|
|
@ -6,9 +6,10 @@
|
|||
* Created:
|
||||
* Description: This file contains the bfin-specific time handling details.
|
||||
* Most of the stuff is located in the machine specific files.
|
||||
* FIXME: (This file is subject for removal)
|
||||
*
|
||||
* Modified:
|
||||
* Copyright 2004-2006 Analog Devices Inc.
|
||||
* Copyright 2004-2008 Analog Devices Inc.
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
|
|
@ -35,6 +36,7 @@
|
|||
#include <linux/irq.h>
|
||||
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
/* This is an NTP setting */
|
||||
#define TICK_SIZE (tick_nsec / 1000)
|
||||
|
|
@ -47,21 +49,6 @@ static struct irqaction bfin_timer_irq = {
|
|||
.flags = IRQF_DISABLED
|
||||
};
|
||||
|
||||
/*
|
||||
* The way that the Blackfin core timer works is:
|
||||
* - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE)
|
||||
* - Every time TSCALE ticks, a 32bit is counted down (TCOUNT)
|
||||
*
|
||||
* If you take the fastest clock (1ns, or 1GHz to make the math work easier)
|
||||
* 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter
|
||||
* (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need
|
||||
* to use TSCALE, and program it to zero (which is pass CCLK through).
|
||||
* If you feel like using it, try to keep HZ * TIMESCALE to some
|
||||
* value that divides easy (like power of 2).
|
||||
*/
|
||||
|
||||
#define TIME_SCALE 1
|
||||
|
||||
static void
|
||||
time_sched_init(irq_handler_t timer_routine)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -6,4 +6,5 @@ obj-y := \
|
|||
cache.o cacheinit.o entry.o \
|
||||
interrupt.o lock.o irqpanic.o arch_checks.o ints-priority.o
|
||||
|
||||
obj-$(CONFIG_PM) += pm.o dpmc.o
|
||||
obj-$(CONFIG_PM) += pm.o dpmc.o
|
||||
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,194 @@
|
|||
/*
|
||||
* File: arch/blackfin/mach-common/cpufreq.c
|
||||
* Based on:
|
||||
* Author:
|
||||
*
|
||||
* Created:
|
||||
* Description: Blackfin core clock scaling
|
||||
*
|
||||
* Modified:
|
||||
* Copyright 2004-2008 Analog Devices Inc.
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see the file COPYING, or write
|
||||
* to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/cpufreq.h>
|
||||
#include <linux/fs.h>
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
|
||||
/* this is the table of CCLK frequencies, in Hz */
|
||||
/* .index is the entry in the auxillary dpm_state_table[] */
|
||||
static struct cpufreq_frequency_table bfin_freq_table[] = {
|
||||
{
|
||||
.frequency = CPUFREQ_TABLE_END,
|
||||
.index = 0,
|
||||
},
|
||||
{
|
||||
.frequency = CPUFREQ_TABLE_END,
|
||||
.index = 1,
|
||||
},
|
||||
{
|
||||
.frequency = CPUFREQ_TABLE_END,
|
||||
.index = 2,
|
||||
},
|
||||
{
|
||||
.frequency = CPUFREQ_TABLE_END,
|
||||
.index = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct bfin_dpm_state {
|
||||
unsigned int csel; /* system clock divider */
|
||||
unsigned int tscale; /* change the divider on the core timer interrupt */
|
||||
} dpm_state_table[3];
|
||||
|
||||
/**************************************************************************/
|
||||
|
||||
static unsigned int bfin_getfreq(unsigned int cpu)
|
||||
{
|
||||
/* The driver only support single cpu */
|
||||
if (cpu != 0)
|
||||
return -1;
|
||||
|
||||
return get_cclk();
|
||||
}
|
||||
|
||||
|
||||
static int bfin_target(struct cpufreq_policy *policy,
|
||||
unsigned int target_freq, unsigned int relation)
|
||||
{
|
||||
unsigned int index, plldiv, tscale;
|
||||
unsigned long flags, cclk_hz;
|
||||
struct cpufreq_freqs freqs;
|
||||
|
||||
if (cpufreq_frequency_table_target(policy, bfin_freq_table,
|
||||
target_freq, relation, &index))
|
||||
return -EINVAL;
|
||||
|
||||
cclk_hz = bfin_freq_table[index].frequency;
|
||||
|
||||
freqs.old = bfin_getfreq(0);
|
||||
freqs.new = cclk_hz;
|
||||
freqs.cpu = 0;
|
||||
|
||||
pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n",
|
||||
cclk_hz, target_freq, freqs.old);
|
||||
|
||||
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
|
||||
local_irq_save(flags);
|
||||
plldiv = (bfin_read_PLL_DIV() & SSEL) | dpm_state_table[index].csel;
|
||||
tscale = dpm_state_table[index].tscale;
|
||||
bfin_write_PLL_DIV(plldiv);
|
||||
/* we have to adjust the core timer, because it is using cclk */
|
||||
bfin_write_TSCALE(tscale);
|
||||
SSYNC();
|
||||
local_irq_restore(flags);
|
||||
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_verify_speed(struct cpufreq_policy *policy)
|
||||
{
|
||||
return cpufreq_frequency_table_verify(policy, bfin_freq_table);
|
||||
}
|
||||
|
||||
static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
|
||||
{
|
||||
|
||||
unsigned long cclk, sclk, csel, min_cclk;
|
||||
int index;
|
||||
|
||||
#ifdef CONFIG_CYCLES_CLOCKSOURCE
|
||||
/*
|
||||
* Clocksource CYCLES is still CONTINUOUS but not longer MONOTONIC in case we enable
|
||||
* CPU frequency scaling, since CYCLES runs off Core Clock.
|
||||
*/
|
||||
printk(KERN_WARNING "CPU frequency scaling not supported: Clocksource not suitable\n"
|
||||
return -ENODEV;
|
||||
#endif
|
||||
|
||||
if (policy->cpu != 0)
|
||||
return -EINVAL;
|
||||
|
||||
cclk = get_cclk();
|
||||
sclk = get_sclk();
|
||||
|
||||
#if ANOMALY_05000273
|
||||
min_cclk = sclk * 2;
|
||||
#else
|
||||
min_cclk = sclk;
|
||||
#endif
|
||||
csel = ((bfin_read_PLL_DIV() & CSEL) >> 4);
|
||||
|
||||
for (index = 0; (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) {
|
||||
bfin_freq_table[index].frequency = cclk >> index;
|
||||
dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
|
||||
dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1;
|
||||
|
||||
pr_debug("cpufreq: freq:%d csel:%d tscale:%d\n",
|
||||
bfin_freq_table[index].frequency,
|
||||
dpm_state_table[index].csel,
|
||||
dpm_state_table[index].tscale);
|
||||
}
|
||||
|
||||
policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
|
||||
|
||||
policy->cpuinfo.transition_latency = (bfin_read_PLL_LOCKCNT() / (sclk / 1000000)) * 1000;
|
||||
/*Now ,only support one cpu */
|
||||
policy->cur = cclk;
|
||||
cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);
|
||||
return cpufreq_frequency_table_cpuinfo(policy, bfin_freq_table);
|
||||
}
|
||||
|
||||
static struct freq_attr *bfin_freq_attr[] = {
|
||||
&cpufreq_freq_attr_scaling_available_freqs,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static struct cpufreq_driver bfin_driver = {
|
||||
.verify = bfin_verify_speed,
|
||||
.target = bfin_target,
|
||||
.get = bfin_getfreq,
|
||||
.init = __bfin_cpu_init,
|
||||
.name = "bfin cpufreq",
|
||||
.owner = THIS_MODULE,
|
||||
.attr = bfin_freq_attr,
|
||||
};
|
||||
|
||||
static int __init bfin_cpu_init(void)
|
||||
{
|
||||
return cpufreq_register_driver(&bfin_driver);
|
||||
}
|
||||
|
||||
static void __exit bfin_cpu_exit(void)
|
||||
{
|
||||
cpufreq_unregister_driver(&bfin_driver);
|
||||
}
|
||||
|
||||
MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
|
||||
MODULE_DESCRIPTION("cpufreq driver for Blackfin");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
module_init(bfin_cpu_init);
|
||||
module_exit(bfin_cpu_exit);
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* asm-blackfin/time.h:
|
||||
*
|
||||
* Copyright 2004-2008 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_BLACKFIN_TIME_H
|
||||
#define _ASM_BLACKFIN_TIME_H
|
||||
|
||||
/*
|
||||
* The way that the Blackfin core timer works is:
|
||||
* - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE)
|
||||
* - Every time TSCALE ticks, a 32bit is counted down (TCOUNT)
|
||||
*
|
||||
* If you take the fastest clock (1ns, or 1GHz to make the math work easier)
|
||||
* 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter
|
||||
* (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need
|
||||
* to use TSCALE, and program it to zero (which is pass CCLK through).
|
||||
* If you feel like using it, try to keep HZ * TIMESCALE to some
|
||||
* value that divides easy (like power of 2).
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_CPU_FREQ
|
||||
#define TIME_SCALE 1
|
||||
#else
|
||||
/*
|
||||
* Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
|
||||
* Whenever we change the Core Clock frequency changes we immediately
|
||||
* adjust the Core Timer Presale Register. This way we don't lose time.
|
||||
*/
|
||||
#define TIME_SCALE 4
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue