Merge series "Convert Cadence QSPI bindings to yaml" from Pratyush Yadav <p.yadav@ti.com>:
Hi, This series picks up Ramuthevar's effort on converting the Cadence QSPI bindings to yaml [0]. During the conversion process, I discovered that some TI device tree files were not using the compatible correctly. Those are fixed in patches 1-3. [0] https://patchwork.kernel.org/project/spi-devel-general/patch/20201116031003.19062-6-vadivel.muruganx.ramuthevar@linux.intel.com/ Pratyush Yadav (3): arm64: dts: ti: k3-j721e-mcu: Fix ospi compatible arm64: dts: ti: k3-j7200-mcu: Fix ospi compatible arm64: dts: ti: k3-am64-main: Fix ospi compatible Ramuthevar Vadivel Murugan (1): dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml .../bindings/spi/cadence-quadspi.txt | 68 --------- .../bindings/spi/cdns,qspi-nor.yaml | 143 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 2 +- .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 +- .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 4 +- 5 files changed, 147 insertions(+), 72 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.txt create mode 100644 Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml -- 2.30.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
This commit is contained in:
Mark Brown
commit
e667450802
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* Cadence Quad SPI controller
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Required properties:
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- compatible : should be one of the following:
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Generic default - "cdns,qspi-nor".
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For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
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For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
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For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor".
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- reg : Contains two entries, each of which is a tuple consisting of a
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physical address and length. The first entry is the address and
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length of the controller register set. The second entry is the
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address and length of the QSPI Controller data area.
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- interrupts : Unit interrupt specifier for the controller interrupt.
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- clocks : phandle to the Quad SPI clock.
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- cdns,fifo-depth : Size of the data FIFO in words.
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- cdns,fifo-width : Bus width of the data FIFO in bytes.
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- cdns,trigger-address : 32-bit indirect AHB trigger address.
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Optional properties:
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- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
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- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
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the read data rather than the QSPI clock. Make sure that QSPI return
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clock is populated on the board before using this property.
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Optional subnodes:
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Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
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custom properties:
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- cdns,read-delay : Delay for read capture logic, in clock cycles
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- cdns,tshsl-ns : Delay in nanoseconds for the length that the master
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mode chip select outputs are de-asserted between
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transactions.
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- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being
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de-activated and the activation of another.
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- cdns,tchsh-ns : Delay in nanoseconds between last bit of current
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transaction and deasserting the device chip select
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(qspi_n_ss_out).
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- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low
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and first bit transfer.
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- resets : Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names : Must include either "qspi" and/or "qspi-ocp".
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Example:
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qspi: spi@ff705000 {
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compatible = "cdns,qspi-nor";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xff705000 0x1000>,
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<0xffa00000 0x1000>;
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interrupts = <0 151 4>;
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clocks = <&qspi_clk>;
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cdns,is-decoded-cs;
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cdns,fifo-depth = <128>;
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cdns,fifo-width = <4>;
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cdns,trigger-address = <0x00000000>;
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resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
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reset-names = "qspi", "qspi-ocp";
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flash0: n25q00@0 {
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...
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cdns,read-delay = <4>;
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cdns,tshsl-ns = <50>;
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cdns,tsd2d-ns = <50>;
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cdns,tchsh-ns = <4>;
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cdns,tslch-ns = <4>;
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};
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};
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@ -0,0 +1,143 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Cadence Quad SPI controller
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maintainers:
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- Pratyush Yadav <p.yadav@ti.com>
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allOf:
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- $ref: spi-controller.yaml#
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- ti,k2g-qspi
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- ti,am654-ospi
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- intel,lgm-qspi
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- const: cdns,qspi-nor
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- const: cdns,qspi-nor
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reg:
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items:
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- description: the controller register set
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- description: the controller data area
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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cdns,fifo-depth:
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description:
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Size of the data FIFO in words.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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enum: [ 128, 256 ]
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default: 128
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cdns,fifo-width:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Bus width of the data FIFO in bytes.
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default: 4
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cdns,trigger-address:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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32-bit indirect AHB trigger address.
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cdns,is-decoded-cs:
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type: boolean
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description:
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Flag to indicate whether decoder is used to select different chip select
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for different memory regions.
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cdns,rclk-en:
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type: boolean
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description:
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Flag to indicate that QSPI return clock is used to latch the read
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data rather than the QSPI clock. Make sure that QSPI return clock
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is populated on the board before using this property.
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resets:
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maxItems: 2
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reset-names:
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minItems: 1
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maxItems: 2
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items:
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enum: [ qspi, qspi-ocp ]
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# subnode's properties
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patternProperties:
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"@[0-9a-f]+$":
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type: object
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description:
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Flash device uses the below defined properties in the subnode.
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properties:
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cdns,read-delay:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Delay for read capture logic, in clock cycles.
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cdns,tshsl-ns:
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description:
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Delay in nanoseconds for the length that the master mode chip select
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outputs are de-asserted between transactions.
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cdns,tsd2d-ns:
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description:
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Delay in nanoseconds between one chip select being de-activated
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and the activation of another.
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cdns,tchsh-ns:
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description:
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Delay in nanoseconds between last bit of current transaction and
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deasserting the device chip select (qspi_n_ss_out).
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cdns,tslch-ns:
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description:
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Delay in nanoseconds between setting qspi_n_ss_out low and
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first bit transfer.
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- cdns,fifo-depth
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- cdns,fifo-width
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- cdns,trigger-address
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- '#address-cells'
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- '#size-cells'
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unevaluatedProperties: false
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examples:
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- |
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qspi: spi@ff705000 {
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compatible = "cdns,qspi-nor";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xff705000 0x1000>,
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<0xffa00000 0x1000>;
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interrupts = <0 151 4>;
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clocks = <&qspi_clk>;
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cdns,fifo-depth = <128>;
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cdns,fifo-width = <4>;
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cdns,trigger-address = <0x00000000>;
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resets = <&rst 0x1>, <&rst 0x2>;
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reset-names = "qspi", "qspi-ocp";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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};
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};
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