IB/hfi1: PCIe bus width retry
Retry the PCIe link training up to 'pcie_retry' times if the PCIe link width is narrower than the previous width. Reviewed-by: Michael J. Ruhl <michael.j.ruhl@intel.com> Reviewed-by: Mitko Haralanov <mitko.haralanov@intel.com> Signed-off-by: Kamenee Arumugam <kamenee.arumugam@intel.com> Signed-off-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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@ -1005,6 +1005,7 @@ int do_pcie_gen3_transition(struct hfi1_devdata *dd)
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const u8 (*ctle_tunings)[4];
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const u8 (*ctle_tunings)[4];
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uint static_ctle_mode;
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uint static_ctle_mode;
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int return_error = 0;
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int return_error = 0;
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u32 target_width;
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/* PCIe Gen3 is for the ASIC only */
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/* PCIe Gen3 is for the ASIC only */
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if (dd->icode != ICODE_RTL_SILICON)
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if (dd->icode != ICODE_RTL_SILICON)
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@ -1044,6 +1045,9 @@ int do_pcie_gen3_transition(struct hfi1_devdata *dd)
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return 0;
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return 0;
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}
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}
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/* Previous Gen1/Gen2 bus width */
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target_width = dd->lbus_width;
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/*
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/*
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* Do the Gen3 transition. Steps are those of the PCIe Gen3
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* Do the Gen3 transition. Steps are those of the PCIe Gen3
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* recipe.
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* recipe.
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@ -1412,11 +1416,12 @@ retry:
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dd_dev_info(dd, "%s: new speed and width: %s\n", __func__,
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dd_dev_info(dd, "%s: new speed and width: %s\n", __func__,
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dd->lbus_info);
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dd->lbus_info);
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if (dd->lbus_speed != target_speed) { /* not target */
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if (dd->lbus_speed != target_speed ||
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dd->lbus_width < target_width) { /* not target */
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/* maybe retry */
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/* maybe retry */
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do_retry = retry_count < pcie_retry;
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do_retry = retry_count < pcie_retry;
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dd_dev_err(dd, "PCIe link speed did not switch to Gen%d%s\n",
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dd_dev_err(dd, "PCIe link speed or width did not match target%s\n",
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pcie_target, do_retry ? ", retrying" : "");
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do_retry ? ", retrying" : "");
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retry_count++;
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retry_count++;
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if (do_retry) {
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if (do_retry) {
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msleep(100); /* allow time to settle */
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msleep(100); /* allow time to settle */
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