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staging: brcm80211: fix "ERROR: that open brace { ... prev line" 

Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Jason Cooper 2010-09-14 09:45:35 -04:00 committed by Greg Kroah-Hartman
parent 6214582217
commit e5c4536fa4
8 changed files with 96 additions and 132 deletions
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16
drivers/staging/brcm80211/phy/wlc_phy_lcn.c
View File

@ -1857,17 +1857,17 @@ wlc_lcnphy_tx_iqlo_cal(phy_info_t *pi,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000
};
uint16 commands_fullcal[] =
{ 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234 };
uint16 commands_fullcal[] = {
0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234 };
uint16 commands_recal[] =
{ 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234 };
uint16 commands_recal[] = {
0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234 };
uint16 command_nums_fullcal[] =
{ 0x7a97, 0x7a97, 0x7a97, 0x7a87, 0x7a87, 0x7b97 };
uint16 command_nums_fullcal[] = {
0x7a97, 0x7a97, 0x7a97, 0x7a87, 0x7a87, 0x7b97 };
uint16 command_nums_recal[] =
{ 0x7a97, 0x7a97, 0x7a97, 0x7a87, 0x7a87, 0x7b97 };
uint16 command_nums_recal[] = {
0x7a97, 0x7a97, 0x7a97, 0x7a87, 0x7a87, 0x7b97 };
uint16 *command_nums = command_nums_fullcal;
uint16 *start_coeffs = NULL, *cal_cmds = NULL, cal_type, diq_start;

89
drivers/staging/brcm80211/phy/wlc_phy_n.c
View File

@ -14073,10 +14073,10 @@ static uint32 nphy_tpc_5GHz_txgain_HiPwrEPA[] = {
static uint8 ant_sw_ctrl_tbl_rev8_2o3[] = { 0x14, 0x18 };
static uint8 ant_sw_ctrl_tbl_rev8[] = { 0x4, 0x8, 0x4, 0x8, 0x11, 0x12 };
static uint8 ant_sw_ctrl_tbl_rev8_2057v7_core0[] =
{ 0x09, 0x0a, 0x15, 0x16, 0x09, 0x0a };
static uint8 ant_sw_ctrl_tbl_rev8_2057v7_core1[] =
{ 0x09, 0x0a, 0x09, 0x0a, 0x15, 0x16 };
static uint8 ant_sw_ctrl_tbl_rev8_2057v7_core0[] = {
0x09, 0x0a, 0x15, 0x16, 0x09, 0x0a };
static uint8 ant_sw_ctrl_tbl_rev8_2057v7_core1[] = {
0x09, 0x0a, 0x09, 0x0a, 0x15, 0x16 };
static bool wlc_phy_chan2freq_nphy(phy_info_t *pi, uint channel, int *f,
chan_info_nphy_radio2057_t **t0,
@ -16075,10 +16075,10 @@ static void wlc_phy_workarounds_nphy(phy_info_t *pi)
if ((NREV_GE(pi->pubpi.phy_rev, 4))
&& (chan_freq_range == WL_CHAN_FREQ_RANGE_2G)) {
uint16 auxadc_vmid[] =
{ 0xa2, 0xb4, 0xb4, 0x270 };
uint16 auxadc_gain[] =
{ 0x02, 0x02, 0x02, 0x00 };
uint16 auxadc_vmid[] = {
0xa2, 0xb4, 0xb4, 0x270 };
uint16 auxadc_gain[] = {
0x02, 0x02, 0x02, 0x00 };
wlc_phy_table_write_nphy(pi,
NPHY_TBL_ID_AFECTRL, 4,
@ -16371,42 +16371,42 @@ static void wlc_phy_workarounds_nphy_gainctrl(phy_info_t *pi)
int8 lna2A_gain_db_rev5[] = { -7, 0, 4, 8 };
int8 lna2A_gain_db_rev6[] = { -7, 0, 4, 8 };
int8 *lna2_gain_db = NULL;
int8 tiaG_gain_db[] =
{ 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A };
int8 tiaA_gain_db[] =
{ 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13 };
int8 tiaA_gain_db_rev4[] =
{ 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d };
int8 tiaA_gain_db_rev5[] =
{ 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d };
int8 tiaA_gain_db_rev6[] =
{ 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d };
int8 tiaG_gain_db[] = {
0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A };
int8 tiaA_gain_db[] = {
0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13 };
int8 tiaA_gain_db_rev4[] = {
0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d };
int8 tiaA_gain_db_rev5[] = {
0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d };
int8 tiaA_gain_db_rev6[] = {
0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d };
int8 *tia_gain_db;
int8 tiaG_gainbits[] =
{ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 };
int8 tiaA_gainbits[] =
{ 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 };
int8 tiaA_gainbits_rev4[] =
{ 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 };
int8 tiaA_gainbits_rev5[] =
{ 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 };
int8 tiaA_gainbits_rev6[] =
{ 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 };
int8 tiaG_gainbits[] = {
0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 };
int8 tiaA_gainbits[] = {
0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 };
int8 tiaA_gainbits_rev4[] = {
0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 };
int8 tiaA_gainbits_rev5[] = {
0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 };
int8 tiaA_gainbits_rev6[] = {
0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 };
int8 *tia_gainbits;
int8 lpf_gain_db[] = { 0x00, 0x06, 0x0c, 0x12, 0x12, 0x12 };
int8 lpf_gainbits[] = { 0x00, 0x01, 0x02, 0x03, 0x03, 0x03 };
uint16 rfseqG_init_gain[] = { 0x613f, 0x613f, 0x613f, 0x613f };
uint16 rfseqG_init_gain_rev4[] = { 0x513f, 0x513f, 0x513f, 0x513f };
uint16 rfseqG_init_gain_rev5[] = { 0x413f, 0x413f, 0x413f, 0x413f };
uint16 rfseqG_init_gain_rev5_elna[] =
{ 0x013f, 0x013f, 0x013f, 0x013f };
uint16 rfseqG_init_gain_rev5_elna[] = {
0x013f, 0x013f, 0x013f, 0x013f };
uint16 rfseqG_init_gain_rev6[] = { 0x513f, 0x513f };
uint16 rfseqG_init_gain_rev6_224B0[] = { 0x413f, 0x413f };
uint16 rfseqG_init_gain_rev6_elna[] = { 0x113f, 0x113f };
uint16 rfseqA_init_gain[] = { 0x516f, 0x516f, 0x516f, 0x516f };
uint16 rfseqA_init_gain_rev4[] = { 0x614f, 0x614f, 0x614f, 0x614f };
uint16 rfseqA_init_gain_rev4_elna[] =
{ 0x314f, 0x314f, 0x314f, 0x314f };
uint16 rfseqA_init_gain_rev4_elna[] = {
0x314f, 0x314f, 0x314f, 0x314f };
uint16 rfseqA_init_gain_rev5[] = { 0x714f, 0x714f, 0x714f, 0x714f };
uint16 rfseqA_init_gain_rev6[] = { 0x714f, 0x714f };
uint16 *rfseq_init_gain;
@ -16967,8 +16967,8 @@ static void wlc_phy_workarounds_nphy_gainctrl_2057_rev5(phy_info_t *pi)
int8 lna1_gain_db[] = { 8, 13, 17, 22 };
int8 lna2_gain_db[] = { -2, 7, 11, 15 };
int8 tia_gain_db[] = { -4, -1, 2, 5, 5, 5, 5, 5, 5, 5 };
int8 tia_gainbits[] =
{ 0x0, 0x01, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 };
int8 tia_gainbits[] = {
0x0, 0x01, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 };
mod_phy_reg(pi, 0x1c, (0x1 << 13), (1 << 13));
mod_phy_reg(pi, 0x32, (0x1 << 13), (1 << 13));
@ -17091,8 +17091,8 @@ static void wlc_phy_workarounds_nphy_gainctrl_2057_rev6(phy_info_t *pi)
if ((freq <= 5080) || (freq == 5825)) {
int8 lna1A_gain_db_rev7[] = { 11, 16, 20, 24 };
int8 lna1A_gain_db_2_rev7[] =
{ 11, 17, 22, 25 };
int8 lna1A_gain_db_2_rev7[] = {
11, 17, 22, 25 };
int8 lna2A_gain_db_rev7[] = { -1, 6, 10, 14 };
crsminu_th = 0x3e;
@ -17102,8 +17102,8 @@ static void wlc_phy_workarounds_nphy_gainctrl_2057_rev6(phy_info_t *pi)
} else if ((freq >= 5500) && (freq <= 5700)) {
int8 lna1A_gain_db_rev7[] = { 11, 17, 21, 25 };
int8 lna1A_gain_db_2_rev7[] =
{ 12, 18, 22, 26 };
int8 lna1A_gain_db_2_rev7[] = {
12, 18, 22, 26 };
int8 lna2A_gain_db_rev7[] = { 1, 8, 12, 16 };
crsminu_th = 0x45;
@ -17116,8 +17116,8 @@ static void wlc_phy_workarounds_nphy_gainctrl_2057_rev6(phy_info_t *pi)
} else {
int8 lna1A_gain_db_rev7[] = { 12, 18, 22, 26 };
int8 lna1A_gain_db_2_rev7[] =
{ 12, 18, 22, 26 };
int8 lna1A_gain_db_2_rev7[] = {
12, 18, 22, 26 };
int8 lna2A_gain_db_rev7[] = { -1, 6, 10, 14 };
crsminu_th = 0x41;
@ -22843,8 +22843,7 @@ static void wlc_phy_txcal_radio_setup_nphy(phy_info_t *pi)
core, TX_SSI_MUX, 0x4);
if (!
(pi->
internal_tx_iqlo_cal_tapoff_intpa_nphy))
{
internal_tx_iqlo_cal_tapoff_intpa_nphy)) {
WRITE_RADIO_REG3(pi, RADIO_2057,
TX, core,
@ -22877,8 +22876,7 @@ static void wlc_phy_txcal_radio_setup_nphy(phy_info_t *pi)
0x06);
if (!
(pi->
internal_tx_iqlo_cal_tapoff_intpa_nphy))
{
internal_tx_iqlo_cal_tapoff_intpa_nphy)) {
WRITE_RADIO_REG3(pi, RADIO_2057,
TX, core,
@ -28187,8 +28185,7 @@ static bool BCMATTACHFN(wlc_phy_txpwr_srom_read_nphy) (phy_info_t *pi)
(NPHY_SROM_TEMPSHIFT + NPHY_SROM_MAXTEMPOFFSET)) {
pi->phy_tempsense_offset = NPHY_SROM_MAXTEMPOFFSET;
} else if (pi->phy_tempsense_offset < (NPHY_SROM_TEMPSHIFT +
NPHY_SROM_MINTEMPOFFSET))
{
NPHY_SROM_MINTEMPOFFSET)) {
pi->phy_tempsense_offset = NPHY_SROM_MINTEMPOFFSET;
} else {
pi->phy_tempsense_offset -= NPHY_SROM_TEMPSHIFT;

8
drivers/staging/brcm80211/sys/wlc_bmac.c
View File

@ -1490,8 +1490,8 @@ wlc_bmac_mhf(wlc_hw_info_t *wlc_hw, uint8 idx, uint16 mask, uint16 val,
int bands)
{
uint16 save;
uint16 addr[MHFMAX] =
{ M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
uint16 addr[MHFMAX] = {
M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
M_HOST_FLAGS5
};
wlc_hwband_t *band;
@ -1569,8 +1569,8 @@ uint16 wlc_bmac_mhf_get(wlc_hw_info_t *wlc_hw, uint8 idx, int bands)
static void wlc_write_mhf(wlc_hw_info_t *wlc_hw, uint16 *mhfs)
{
uint8 idx;
uint16 addr[] =
{ M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
uint16 addr[] = {
M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
M_HOST_FLAGS5
};

4
drivers/staging/brcm80211/sys/wlc_channel.c
View File

@ -971,8 +971,8 @@ static void wlc_channels_commit(wlc_cm_info_t *wlc_cm)
mboolset(wlc->pub->radio_disabled, WL_RADIO_COUNTRY_DISABLE);
WL_ERROR(("wl%d: %s: no valid channel for \"%s\" nbands %d bandlocked %d\n", wlc->pub->unit, __func__, wlc_cm->country_abbrev, NBANDS(wlc), wlc->bandlocked));
} else
if (mboolisset(wlc->pub->radio_disabled, WL_RADIO_COUNTRY_DISABLE))
{
if (mboolisset(wlc->pub->radio_disabled,
WL_RADIO_COUNTRY_DISABLE)) {
/* country/locale with valid channel, clear the radio disable bit */
mboolclr(wlc->pub->radio_disabled, WL_RADIO_COUNTRY_DISABLE);
}

4
drivers/staging/brcm80211/sys/wlc_mac80211.c
View File

@ -233,8 +233,8 @@ static bool in_send_q = FALSE;
#define wme_shmemacindex(ac) wme_ac2fifo[ac]
#ifdef BCMDBG
static const char *fifo_names[] =
{ "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
static const char *fifo_names[] = {
"AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
const char *aci_names[] = { "AC_BE", "AC_BK", "AC_VI", "AC_VO" };
#endif

15
drivers/staging/brcm80211/util/bcmsrom.c
View File

@ -256,8 +256,7 @@ static const char BCMATTACHDATA(vstr_manfid)[] = "manfid=0x%x";
static const char BCMATTACHDATA(vstr_prodid)[] = "prodid=0x%x";
#ifdef BCMSDIO
static const char BCMATTACHDATA(vstr_sdmaxspeed)[] = "sdmaxspeed=%d";
static const char BCMATTACHDATA(vstr_sdmaxblk)[][13] =
{
static const char BCMATTACHDATA(vstr_sdmaxblk)[][13] = {
"sdmaxblk0=%d", "sdmaxblk1=%d", "sdmaxblk2=%d"};
#endif
static const char BCMATTACHDATA(vstr_regwindowsz)[] = "regwindowsz=%d";
@ -271,22 +270,18 @@ static const char BCMATTACHDATA(vstr_aa5g)[] = "aa5g=0x%x";
static const char BCMATTACHDATA(vstr_ag)[] = "ag%d=0x%x";
static const char BCMATTACHDATA(vstr_cc)[] = "cc=%d";
static const char BCMATTACHDATA(vstr_opo)[] = "opo=%d";
static const char BCMATTACHDATA(vstr_pa0b)[][9] =
{
static const char BCMATTACHDATA(vstr_pa0b)[][9] = {
"pa0b0=%d", "pa0b1=%d", "pa0b2=%d"};
static const char BCMATTACHDATA(vstr_pa0itssit)[] = "pa0itssit=%d";
static const char BCMATTACHDATA(vstr_pa0maxpwr)[] = "pa0maxpwr=%d";
static const char BCMATTACHDATA(vstr_pa1b)[][9] =
{
static const char BCMATTACHDATA(vstr_pa1b)[][9] = {
"pa1b0=%d", "pa1b1=%d", "pa1b2=%d"};
static const char BCMATTACHDATA(vstr_pa1lob)[][11] =
{
static const char BCMATTACHDATA(vstr_pa1lob)[][11] = {
"pa1lob0=%d", "pa1lob1=%d", "pa1lob2=%d"};
static const char BCMATTACHDATA(vstr_pa1hib)[][11] =
{
static const char BCMATTACHDATA(vstr_pa1hib)[][11] = {
"pa1hib0=%d", "pa1hib1=%d", "pa1hib2=%d"};
static const char BCMATTACHDATA(vstr_pa1itssit)[] = "pa1itssit=%d";

84
drivers/staging/brcm80211/util/hndpmu.c
View File

@ -305,8 +305,7 @@ typedef struct {
#define RES_DEPEND_ADD 1 /* Add to the dependancies mask */
#define RES_DEPEND_REMOVE -1 /* Remove from the dependancies mask */
static const pmu_res_updown_t BCMATTACHDATA(bcm4328a0_res_updown)[] =
{
static const pmu_res_updown_t BCMATTACHDATA(bcm4328a0_res_updown)[] = {
{
RES4328_EXT_SWITCHER_PWM, 0x0101}, {
RES4328_BB_SWITCHER_PWM, 0x1f01}, {
@ -330,8 +329,7 @@ static const pmu_res_updown_t BCMATTACHDATA(bcm4328a0_res_updown)[] =
RES4328_BB_PLL_PU, 0x0701}
};
static const pmu_res_depend_t BCMATTACHDATA(bcm4328a0_res_depend)[] =
{
static const pmu_res_depend_t BCMATTACHDATA(bcm4328a0_res_depend)[] = {
/* Adjust ILP request resource not to force ext/BB switchers into burst mode */
{
PMURES_BIT(RES4328_ILP_REQUEST),
@ -340,8 +338,7 @@ static const pmu_res_depend_t BCMATTACHDATA(bcm4328a0_res_depend)[] =
PMURES_BIT(RES4328_BB_SWITCHER_PWM), NULL}
};
static const pmu_res_updown_t BCMATTACHDATA(bcm4325a0_res_updown_qt)[] =
{
static const pmu_res_updown_t BCMATTACHDATA(bcm4325a0_res_updown_qt)[] = {
{
RES4325_HT_AVAIL, 0x0300}, {
RES4325_BBPLL_PWRSW_PU, 0x0101}, {
@ -353,14 +350,12 @@ static const pmu_res_updown_t BCMATTACHDATA(bcm4325a0_res_updown_qt)[] =
RES4325_CBUCK_PWM, 0x0803}
};
static const pmu_res_updown_t BCMATTACHDATA(bcm4325a0_res_updown)[] =
{
static const pmu_res_updown_t BCMATTACHDATA(bcm4325a0_res_updown)[] = {
{
RES4325_XTAL_PU, 0x1501}
};
static const pmu_res_depend_t BCMATTACHDATA(bcm4325a0_res_depend)[] =
{
static const pmu_res_depend_t BCMATTACHDATA(bcm4325a0_res_depend)[] = {
/* Adjust OTP PU resource dependencies - remove BB BURST */
{
PMURES_BIT(RES4325_OTP_PU),
@ -401,8 +396,7 @@ static const pmu_res_depend_t BCMATTACHDATA(bcm4325a0_res_depend)[] =
PMURES_BIT(RES4325B0_CBUCK_PWM), si_pmu_res_depfltr_ncb}
};
static const pmu_res_updown_t BCMATTACHDATA(bcm4315a0_res_updown_qt)[] =
{
static const pmu_res_updown_t BCMATTACHDATA(bcm4315a0_res_updown_qt)[] = {
{
RES4315_HT_AVAIL, 0x0101}, {
RES4315_XTAL_PU, 0x0100}, {
@ -414,14 +408,12 @@ static const pmu_res_updown_t BCMATTACHDATA(bcm4315a0_res_updown_qt)[] =
RES4315_CBUCK_LPOM, 0x0100}
};
static const pmu_res_updown_t BCMATTACHDATA(bcm4315a0_res_updown)[] =
{
static const pmu_res_updown_t BCMATTACHDATA(bcm4315a0_res_updown)[] = {
{
RES4315_XTAL_PU, 0x2501}
};
static const pmu_res_depend_t BCMATTACHDATA(bcm4315a0_res_depend)[] =
{
static const pmu_res_depend_t BCMATTACHDATA(bcm4315a0_res_depend)[] = {
/* Adjust OTP PU resource dependencies - not need PALDO unless write */
{
PMURES_BIT(RES4315_OTP_PU),
@ -461,14 +453,12 @@ static const pmu_res_depend_t BCMATTACHDATA(bcm4315a0_res_depend)[] =
};
/* 4329 specific. needs to come back this issue later */
static const pmu_res_updown_t BCMINITDATA(bcm4329_res_updown)[] =
{
static const pmu_res_updown_t BCMINITDATA(bcm4329_res_updown)[] = {
{
RES4329_XTAL_PU, 0x1501}
};
static const pmu_res_depend_t BCMINITDATA(bcm4329_res_depend)[] =
{
static const pmu_res_depend_t BCMINITDATA(bcm4329_res_depend)[] = {
/* Adjust HT Avail resource dependencies */
{
PMURES_BIT(RES4329_HT_AVAIL),
@ -489,8 +479,7 @@ static const pmu_res_depend_t BCMINITDATA(bcm4329_res_depend)[] =
PMURES_BIT(RES4329_BBPLL_PWRSW_PU), NULL}
};
static const pmu_res_updown_t BCMATTACHDATA(bcm4319a0_res_updown_qt)[] =
{
static const pmu_res_updown_t BCMATTACHDATA(bcm4319a0_res_updown_qt)[] = {
{
RES4319_HT_AVAIL, 0x0101}, {
RES4319_XTAL_PU, 0x0100}, {
@ -502,14 +491,12 @@ static const pmu_res_updown_t BCMATTACHDATA(bcm4319a0_res_updown_qt)[] =
RES4319_CBUCK_LPOM, 0x0100}
};
static const pmu_res_updown_t BCMATTACHDATA(bcm4319a0_res_updown)[] =
{
static const pmu_res_updown_t BCMATTACHDATA(bcm4319a0_res_updown)[] = {
{
RES4319_XTAL_PU, 0x3f01}
};
static const pmu_res_depend_t BCMATTACHDATA(bcm4319a0_res_depend)[] =
{
static const pmu_res_depend_t BCMATTACHDATA(bcm4319a0_res_depend)[] = {
/* Adjust OTP PU resource dependencies - not need PALDO unless write */
{
PMURES_BIT(RES4319_OTP_PU),
@ -531,8 +518,7 @@ static const pmu_res_depend_t BCMATTACHDATA(bcm4319a0_res_depend)[] =
PMURES_BIT(RES4319_AFE_PWRSW_PU), NULL}
};
static const pmu_res_updown_t BCMATTACHDATA(bcm4336a0_res_updown_qt)[] =
{
static const pmu_res_updown_t BCMATTACHDATA(bcm4336a0_res_updown_qt)[] = {
{
RES4336_HT_AVAIL, 0x0101}, {
RES4336_XTAL_PU, 0x0100}, {
@ -542,21 +528,18 @@ static const pmu_res_updown_t BCMATTACHDATA(bcm4336a0_res_updown_qt)[] =
RES4336_CBUCK_LPOM, 0x0100}
};
static const pmu_res_updown_t BCMATTACHDATA(bcm4336a0_res_updown)[] =
{
static const pmu_res_updown_t BCMATTACHDATA(bcm4336a0_res_updown)[] = {
{
RES4336_HT_AVAIL, 0x0D01}
};
static const pmu_res_depend_t BCMATTACHDATA(bcm4336a0_res_depend)[] =
{
static const pmu_res_depend_t BCMATTACHDATA(bcm4336a0_res_depend)[] = {
/* Just a dummy entry for now */
{
PMURES_BIT(RES4336_RSVD), RES_DEPEND_ADD, 0, NULL}
};
static const pmu_res_updown_t BCMATTACHDATA(bcm4330a0_res_updown_qt)[] =
{
static const pmu_res_updown_t BCMATTACHDATA(bcm4330a0_res_updown_qt)[] = {
{
RES4330_HT_AVAIL, 0x0101}, {
RES4330_XTAL_PU, 0x0100}, {
@ -566,14 +549,12 @@ static const pmu_res_updown_t BCMATTACHDATA(bcm4330a0_res_updown_qt)[] =
RES4330_CBUCK_LPOM, 0x0100}
};
static const pmu_res_updown_t BCMATTACHDATA(bcm4330a0_res_updown)[] =
{
static const pmu_res_updown_t BCMATTACHDATA(bcm4330a0_res_updown)[] = {
{
RES4330_HT_AVAIL, 0x0e02}
};
static const pmu_res_depend_t BCMATTACHDATA(bcm4330a0_res_depend)[] =
{
static const pmu_res_depend_t BCMATTACHDATA(bcm4330a0_res_depend)[] = {
/* Just a dummy entry for now */
{
PMURES_BIT(RES4330_HT_AVAIL), RES_DEPEND_ADD, 0, NULL}
@ -895,8 +876,7 @@ typedef struct {
} pmu0_xtaltab0_t;
/* the following table is based on 880Mhz fvco */
static const pmu0_xtaltab0_t BCMINITDATA(pmu0_xtaltab0)[] =
{
static const pmu0_xtaltab0_t BCMINITDATA(pmu0_xtaltab0)[] = {
{
12000, 1, 73, 349525}, {
13000, 2, 67, 725937}, {
@ -927,8 +907,7 @@ typedef struct {
uint32 ndiv_frac;
} pmu1_xtaltab0_t;
static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_880_4329)[] =
{
static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_880_4329)[] = {
{
12000, 1, 3, 22, 0x9, 0xFFFFEF}, {
13000, 2, 1, 6, 0xb, 0x483483}, {
@ -950,8 +929,7 @@ static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_880_4329)[] =
};
/* the following table is based on 880Mhz fvco */
static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_880)[] =
{
static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_880)[] = {
{
12000, 1, 3, 22, 0x9, 0xFFFFEF}, {
13000, 2, 1, 6, 0xb, 0x483483}, {
@ -990,8 +968,7 @@ static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_880)[] =
#define PMU1_XTALTAB0_880_40000K 15
/* the following table is based on 1760Mhz fvco */
static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_1760)[] =
{
static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_1760)[] = {
{
12000, 1, 3, 44, 0x9, 0xFFFFEF}, {
13000, 2, 1, 12, 0xb, 0x483483}, {
@ -1029,8 +1006,7 @@ static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_1760)[] =
#define PMU1_XTALTAB0_1760_40000K 14
/* the following table is based on 1440Mhz fvco */
static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_1440)[] =
{
static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_1440)[] = {
{
12000, 1, 1, 1, 0x78, 0x0}, {
13000, 2, 1, 1, 0x6E, 0xC4EC4E}, {
@ -1074,8 +1050,7 @@ static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_1440)[] =
#define XTAL_FREQ_37400MHZ 37400
#define XTAL_FREQ_48000MHZ 48000
static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_960)[] =
{
static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_960)[] = {
{
12000, 1, 1, 1, 0x50, 0x0}, {
13000, 2, 1, 1, 0x49, 0xD89D89}, {
@ -1895,8 +1870,7 @@ typedef struct {
} sdiod_drive_str_t;
/* SDIO Drive Strength to sel value table for PMU Rev 1 */
static const sdiod_drive_str_t BCMINITDATA(sdiod_drive_strength_tab1)[] =
{
static const sdiod_drive_str_t BCMINITDATA(sdiod_drive_strength_tab1)[] = {
{
4, 0x2}, {
2, 0x3}, {
@ -1904,8 +1878,7 @@ static const sdiod_drive_str_t BCMINITDATA(sdiod_drive_strength_tab1)[] =
0, 0x0}};
/* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
static const sdiod_drive_str_t BCMINITDATA(sdiod_drive_strength_tab2)[] =
{
static const sdiod_drive_str_t BCMINITDATA(sdiod_drive_strength_tab2)[] = {
{
12, 0x7}, {
10, 0x6}, {
@ -1916,8 +1889,7 @@ static const sdiod_drive_str_t BCMINITDATA(sdiod_drive_strength_tab2)[] =
0, 0x0}};
/* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
static const sdiod_drive_str_t BCMINITDATA(sdiod_drive_strength_tab3)[] =
{
static const sdiod_drive_str_t BCMINITDATA(sdiod_drive_strength_tab3)[] = {
{
32, 0x7}, {
26, 0x6}, {

8
drivers/staging/brcm80211/util/siutils.c
View File

@ -2905,10 +2905,10 @@ BCMATTACHFN(si_sprom_enable) (si_t *sih, bool enable)
int si_cis_source(si_t *sih)
{
/* Many chips have the same mapping of their chipstatus field */
static const uint cis_sel[] =
{ CIS_DEFAULT, CIS_SROM, CIS_OTP, CIS_SROM };
static const uint cis_43236_sel[] =
{ CIS_DEFAULT, CIS_SROM, CIS_OTP, CIS_OTP };
static const uint cis_sel[] = {
CIS_DEFAULT, CIS_SROM, CIS_OTP, CIS_SROM };
static const uint cis_43236_sel[] = {
CIS_DEFAULT, CIS_SROM, CIS_OTP, CIS_OTP };
/* PCI chips use SROM format instead of CIS */
if (BUSTYPE(sih->bustype) == PCI_BUS)