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powerpc/powernv/ioda2: Rework iommu_table creation 

This moves iommu_table creation to the beginning to make following changes
easier to review. This starts using table parameters from the iommu_table
struct.

This should cause no behavioural change.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Alexey Kardashevskiy 2015-06-05 16:35:16 +10:00 committed by Michael Ellerman
parent 05c6cfb9dc
commit e5aad1e678
1 changed files with 12 additions and 12 deletions
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24
arch/powerpc/platforms/powernv/pci-ioda.c
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@ -2071,13 +2071,23 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
addr = page_address(tce_mem); addr = page_address(tce_mem);
memset(addr, 0, tce_table_size); memset(addr, 0, tce_table_size);
/* Setup linux iommu table */
pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0,
IOMMU_PAGE_SHIFT_4K);
tbl->it_ops = &pnv_ioda2_iommu_ops;
iommu_init_table(tbl, phb->hose->node);
#ifdef CONFIG_IOMMU_API
pe->table_group.ops = &pnv_pci_ioda2_ops;
#endif
/* /*
* Map TCE table through TVT. The TVE index is the PE number * Map TCE table through TVT. The TVE index is the PE number
* shifted by 1 bit for 32-bits DMA space. * shifted by 1 bit for 32-bits DMA space.
*/ */
rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
pe->pe_number << 1, 1, __pa(addr), pe->pe_number << 1, 1, __pa(tbl->it_base),
tce_table_size, 0x1000); tbl->it_size << 3, 1ULL << tbl->it_page_shift);
if (rc) { if (rc) {
pe_err(pe, "Failed to configure 32-bit TCE table," pe_err(pe, "Failed to configure 32-bit TCE table,"
" err %ld\n", rc); " err %ld\n", rc);
@ -2086,20 +2096,10 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
pnv_pci_ioda2_tce_invalidate_entire(pe); pnv_pci_ioda2_tce_invalidate_entire(pe);
/* Setup linux iommu table */
pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0,
IOMMU_PAGE_SHIFT_4K);
/* OPAL variant of PHB3 invalidated TCEs */ /* OPAL variant of PHB3 invalidated TCEs */
if (phb->ioda.tce_inval_reg) if (phb->ioda.tce_inval_reg)
tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
tbl->it_ops = &pnv_ioda2_iommu_ops;
iommu_init_table(tbl, phb->hose->node);
#ifdef CONFIG_IOMMU_API
pe->table_group.ops = &pnv_pci_ioda2_ops;
#endif
if (pe->flags & PNV_IODA_PE_DEV) { if (pe->flags & PNV_IODA_PE_DEV) {
/* /*
* Setting table base here only for carrying iommu_group * Setting table base here only for carrying iommu_group