amd-xgbe: Support for 64-bit management counter registers
Add support for reading all management counter registers as 64-bit values. The indication of whether to read the high 32-bits to form a 64-bit value is indicated in the version data. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -2588,17 +2588,33 @@ static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo)
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bool read_hi;
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u64 val;
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switch (reg_lo) {
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/* These registers are always 64 bit */
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case MMC_TXOCTETCOUNT_GB_LO:
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case MMC_TXOCTETCOUNT_G_LO:
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case MMC_RXOCTETCOUNT_GB_LO:
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case MMC_RXOCTETCOUNT_G_LO:
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read_hi = true;
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break;
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if (pdata->vdata->mmc_64bit) {
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switch (reg_lo) {
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/* These registers are always 32 bit */
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case MMC_RXRUNTERROR:
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case MMC_RXJABBERERROR:
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case MMC_RXUNDERSIZE_G:
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case MMC_RXOVERSIZE_G:
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case MMC_RXWATCHDOGERROR:
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read_hi = false;
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break;
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default:
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read_hi = false;
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default:
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read_hi = true;
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}
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} else {
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switch (reg_lo) {
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/* These registers are always 64 bit */
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case MMC_TXOCTETCOUNT_GB_LO:
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case MMC_TXOCTETCOUNT_G_LO:
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case MMC_RXOCTETCOUNT_GB_LO:
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case MMC_RXOCTETCOUNT_G_LO:
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read_hi = true;
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break;
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default:
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read_hi = false;
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}
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}
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val = XGMAC_IOREAD(pdata, reg_lo);
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@ -804,6 +804,7 @@ struct xgbe_hw_features {
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struct xgbe_version_data {
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void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *);
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enum xgbe_xpcs_access xpcs_access;
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unsigned int mmc_64bit;
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};
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struct xgbe_prv_data {
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