Staging: comedi: add me4000 driver
This adds the me4000 driver to the comedi staging tree From: Guenter Gebhardt <g.gebhardt@meilhaus.com> Cc: David Schleef <ds@schleef.org> Cc: Frank Mori Hess <fmhess@users.sourceforge.net> Cc: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Guenter Gebhardt
Greg Kroah-Hartman
parent
96341f7153
commit
e55c95a3be
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@ -10,6 +10,7 @@ obj-$(CONFIG_COMEDI) += comedi_parport.o
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# Comedi PCI drivers
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obj-$(CONFIG_COMEDI_PCI_DRIVERS) += mite.o
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obj-$(CONFIG_COMEDI_PCI_DRIVERS) += icp_multi.o
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obj-$(CONFIG_COMEDI_PCI_DRIVERS) += me4000.o
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# Comedi USB drivers
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obj-$(CONFIG_COMEDI_USB_DRIVERS) += usbdux.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,446 @@
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/*
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me4000.h
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Register descriptions and defines for the ME-4000 board family
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COMEDI - Linux Control and Measurement Device Interface
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Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _ME4000_H_
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#define _ME4000_H_
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/*=============================================================================
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Debug section
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===========================================================================*/
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#undef ME4000_CALL_DEBUG // Debug function entry and exit
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#undef ME4000_PORT_DEBUG // Debug port access
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#undef ME4000_ISR_DEBUG // Debug the interrupt service routine
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#undef ME4000_DEBUG // General purpose debug masseges
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#ifdef ME4000_CALL_DEBUG
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#undef CALL_PDEBUG
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#define CALL_PDEBUG(fmt, args...) printk(KERN_DEBUG"comedi%d: me4000: " fmt, dev->minor, ##args)
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#else
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# define CALL_PDEBUG(fmt, args...) // no debugging, do nothing
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#endif
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#ifdef ME4000_PORT_DEBUG
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#undef PORT_PDEBUG
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#define PORT_PDEBUG(fmt, args...) printk(KERN_DEBUG"comedi%d: me4000: " fmt, dev->minor, ##args)
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#else
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#define PORT_PDEBUG(fmt, args...) // no debugging, do nothing
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#endif
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#ifdef ME4000_ISR_DEBUG
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#undef ISR_PDEBUG
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#define ISR_PDEBUG(fmt, args...) printk(KERN_DEBUG"comedi%d: me4000: " fmt, dev->minor, ##args)
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#else
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#define ISR_PDEBUG(fmt, args...) // no debugging, do nothing
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#endif
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#ifdef ME4000_DEBUG
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#undef PDEBUG
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#define PDEBUG(fmt, args...) printk(KERN_DEBUG"comedi%d: me4000: " fmt, dev->minor, ##args)
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#else
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#define PDEBUG(fmt, args...) // no debugging, do nothing
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#endif
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/*=============================================================================
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PCI vendor and device IDs
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===========================================================================*/
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#define PCI_VENDOR_ID_MEILHAUS 0x1402
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#define PCI_DEVICE_ID_MEILHAUS_ME4650 0x4650 // Low Cost version
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#define PCI_DEVICE_ID_MEILHAUS_ME4660 0x4660 // Standard version
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#define PCI_DEVICE_ID_MEILHAUS_ME4660I 0x4661 // Isolated version
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#define PCI_DEVICE_ID_MEILHAUS_ME4660S 0x4662 // Standard version with Sample and Hold
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#define PCI_DEVICE_ID_MEILHAUS_ME4660IS 0x4663 // Isolated version with Sample and Hold
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#define PCI_DEVICE_ID_MEILHAUS_ME4670 0x4670 // Standard version
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#define PCI_DEVICE_ID_MEILHAUS_ME4670I 0x4671 // Isolated version
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#define PCI_DEVICE_ID_MEILHAUS_ME4670S 0x4672 // Standard version with Sample and Hold
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#define PCI_DEVICE_ID_MEILHAUS_ME4670IS 0x4673 // Isolated version with Sample and Hold
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#define PCI_DEVICE_ID_MEILHAUS_ME4680 0x4680 // Standard version
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#define PCI_DEVICE_ID_MEILHAUS_ME4680I 0x4681 // Isolated version
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#define PCI_DEVICE_ID_MEILHAUS_ME4680S 0x4682 // Standard version with Sample and Hold
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#define PCI_DEVICE_ID_MEILHAUS_ME4680IS 0x4683 // Isolated version with Sample and Hold
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/*=============================================================================
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ME-4000 base register offsets
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===========================================================================*/
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#define ME4000_AO_00_CTRL_REG 0x00 // R/W
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#define ME4000_AO_00_STATUS_REG 0x04 // R/_
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#define ME4000_AO_00_FIFO_REG 0x08 // _/W
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#define ME4000_AO_00_SINGLE_REG 0x0C // R/W
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#define ME4000_AO_00_TIMER_REG 0x10 // _/W
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#define ME4000_AO_01_CTRL_REG 0x18 // R/W
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#define ME4000_AO_01_STATUS_REG 0x1C // R/_
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#define ME4000_AO_01_FIFO_REG 0x20 // _/W
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#define ME4000_AO_01_SINGLE_REG 0x24 // R/W
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#define ME4000_AO_01_TIMER_REG 0x28 // _/W
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#define ME4000_AO_02_CTRL_REG 0x30 // R/W
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#define ME4000_AO_02_STATUS_REG 0x34 // R/_
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#define ME4000_AO_02_FIFO_REG 0x38 // _/W
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#define ME4000_AO_02_SINGLE_REG 0x3C // R/W
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#define ME4000_AO_02_TIMER_REG 0x40 // _/W
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#define ME4000_AO_03_CTRL_REG 0x48 // R/W
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#define ME4000_AO_03_STATUS_REG 0x4C // R/_
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#define ME4000_AO_03_FIFO_REG 0x50 // _/W
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#define ME4000_AO_03_SINGLE_REG 0x54 // R/W
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#define ME4000_AO_03_TIMER_REG 0x58 // _/W
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#define ME4000_AI_CTRL_REG 0x74 // _/W
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#define ME4000_AI_STATUS_REG 0x74 // R/_
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#define ME4000_AI_CHANNEL_LIST_REG 0x78 // _/W
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#define ME4000_AI_DATA_REG 0x7C // R/_
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#define ME4000_AI_CHAN_TIMER_REG 0x80 // _/W
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#define ME4000_AI_CHAN_PRE_TIMER_REG 0x84 // _/W
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#define ME4000_AI_SCAN_TIMER_LOW_REG 0x88 // _/W
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#define ME4000_AI_SCAN_TIMER_HIGH_REG 0x8C // _/W
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#define ME4000_AI_SCAN_PRE_TIMER_LOW_REG 0x90 // _/W
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#define ME4000_AI_SCAN_PRE_TIMER_HIGH_REG 0x94 // _/W
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#define ME4000_AI_START_REG 0x98 // R/_
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#define ME4000_IRQ_STATUS_REG 0x9C // R/_
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#define ME4000_DIO_PORT_0_REG 0xA0 // R/W
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#define ME4000_DIO_PORT_1_REG 0xA4 // R/W
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#define ME4000_DIO_PORT_2_REG 0xA8 // R/W
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#define ME4000_DIO_PORT_3_REG 0xAC // R/W
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#define ME4000_DIO_DIR_REG 0xB0 // R/W
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#define ME4000_AO_LOADSETREG_XX 0xB4 // R/W
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#define ME4000_DIO_CTRL_REG 0xB8 // R/W
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#define ME4000_AO_DEMUX_ADJUST_REG 0xBC // -/W
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#define ME4000_AI_SAMPLE_COUNTER_REG 0xC0 // _/W
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/*=============================================================================
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Value to adjust Demux
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===========================================================================*/
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#define ME4000_AO_DEMUX_ADJUST_VALUE 0x4C
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/*=============================================================================
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Counter base register offsets
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===========================================================================*/
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#define ME4000_CNT_COUNTER_0_REG 0x00
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#define ME4000_CNT_COUNTER_1_REG 0x01
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#define ME4000_CNT_COUNTER_2_REG 0x02
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#define ME4000_CNT_CTRL_REG 0x03
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/*=============================================================================
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PLX base register offsets
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===========================================================================*/
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#define PLX_INTCSR 0x4C // Interrupt control and status register
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#define PLX_ICR 0x50 // Initialization control register
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/*=============================================================================
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Bits for the PLX_ICSR register
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===========================================================================*/
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#define PLX_INTCSR_LOCAL_INT1_EN 0x01 // If set, local interrupt 1 is enabled (r/w)
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#define PLX_INTCSR_LOCAL_INT1_POL 0x02 // If set, local interrupt 1 polarity is active high (r/w)
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#define PLX_INTCSR_LOCAL_INT1_STATE 0x04 // If set, local interrupt 1 is active (r/_)
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#define PLX_INTCSR_LOCAL_INT2_EN 0x08 // If set, local interrupt 2 is enabled (r/w)
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#define PLX_INTCSR_LOCAL_INT2_POL 0x10 // If set, local interrupt 2 polarity is active high (r/w)
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#define PLX_INTCSR_LOCAL_INT2_STATE 0x20 // If set, local interrupt 2 is active (r/_)
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#define PLX_INTCSR_PCI_INT_EN 0x40 // If set, PCI interrupt is enabled (r/w)
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#define PLX_INTCSR_SOFT_INT 0x80 // If set, a software interrupt is generated (r/w)
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/*=============================================================================
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Bits for the PLX_ICR register
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===========================================================================*/
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#define PLX_ICR_BIT_EEPROM_CLOCK_SET 0x01000000
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#define PLX_ICR_BIT_EEPROM_CHIP_SELECT 0x02000000
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#define PLX_ICR_BIT_EEPROM_WRITE 0x04000000
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#define PLX_ICR_BIT_EEPROM_READ 0x08000000
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#define PLX_ICR_BIT_EEPROM_VALID 0x10000000
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#define PLX_ICR_MASK_EEPROM 0x1F000000
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#define EEPROM_DELAY 1
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/*=============================================================================
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Bits for the ME4000_AO_CTRL_REG register
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===========================================================================*/
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#define ME4000_AO_CTRL_BIT_MODE_0 0x001
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#define ME4000_AO_CTRL_BIT_MODE_1 0x002
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#define ME4000_AO_CTRL_MASK_MODE 0x003
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#define ME4000_AO_CTRL_BIT_STOP 0x004
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#define ME4000_AO_CTRL_BIT_ENABLE_FIFO 0x008
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#define ME4000_AO_CTRL_BIT_ENABLE_EX_TRIG 0x010
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#define ME4000_AO_CTRL_BIT_EX_TRIG_EDGE 0x020
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#define ME4000_AO_CTRL_BIT_IMMEDIATE_STOP 0x080
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#define ME4000_AO_CTRL_BIT_ENABLE_DO 0x100
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#define ME4000_AO_CTRL_BIT_ENABLE_IRQ 0x200
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#define ME4000_AO_CTRL_BIT_RESET_IRQ 0x400
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/*=============================================================================
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Bits for the ME4000_AO_STATUS_REG register
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===========================================================================*/
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#define ME4000_AO_STATUS_BIT_FSM 0x01
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#define ME4000_AO_STATUS_BIT_FF 0x02
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#define ME4000_AO_STATUS_BIT_HF 0x04
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#define ME4000_AO_STATUS_BIT_EF 0x08
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/*=============================================================================
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Bits for the ME4000_AI_CTRL_REG register
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===========================================================================*/
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#define ME4000_AI_CTRL_BIT_MODE_0 0x00000001
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#define ME4000_AI_CTRL_BIT_MODE_1 0x00000002
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#define ME4000_AI_CTRL_BIT_MODE_2 0x00000004
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#define ME4000_AI_CTRL_BIT_SAMPLE_HOLD 0x00000008
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#define ME4000_AI_CTRL_BIT_IMMEDIATE_STOP 0x00000010
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#define ME4000_AI_CTRL_BIT_STOP 0x00000020
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#define ME4000_AI_CTRL_BIT_CHANNEL_FIFO 0x00000040
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#define ME4000_AI_CTRL_BIT_DATA_FIFO 0x00000080
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#define ME4000_AI_CTRL_BIT_FULLSCALE 0x00000100
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#define ME4000_AI_CTRL_BIT_OFFSET 0x00000200
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#define ME4000_AI_CTRL_BIT_EX_TRIG_ANALOG 0x00000400
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#define ME4000_AI_CTRL_BIT_EX_TRIG 0x00000800
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#define ME4000_AI_CTRL_BIT_EX_TRIG_FALLING 0x00001000
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#define ME4000_AI_CTRL_BIT_EX_IRQ 0x00002000
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#define ME4000_AI_CTRL_BIT_EX_IRQ_RESET 0x00004000
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#define ME4000_AI_CTRL_BIT_LE_IRQ 0x00008000
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#define ME4000_AI_CTRL_BIT_LE_IRQ_RESET 0x00010000
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#define ME4000_AI_CTRL_BIT_HF_IRQ 0x00020000
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#define ME4000_AI_CTRL_BIT_HF_IRQ_RESET 0x00040000
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#define ME4000_AI_CTRL_BIT_SC_IRQ 0x00080000
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#define ME4000_AI_CTRL_BIT_SC_IRQ_RESET 0x00100000
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#define ME4000_AI_CTRL_BIT_SC_RELOAD 0x00200000
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#define ME4000_AI_CTRL_BIT_EX_TRIG_BOTH 0x80000000
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/*=============================================================================
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Bits for the ME4000_AI_STATUS_REG register
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===========================================================================*/
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#define ME4000_AI_STATUS_BIT_EF_CHANNEL 0x00400000
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#define ME4000_AI_STATUS_BIT_HF_CHANNEL 0x00800000
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#define ME4000_AI_STATUS_BIT_FF_CHANNEL 0x01000000
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#define ME4000_AI_STATUS_BIT_EF_DATA 0x02000000
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#define ME4000_AI_STATUS_BIT_HF_DATA 0x04000000
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#define ME4000_AI_STATUS_BIT_FF_DATA 0x08000000
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#define ME4000_AI_STATUS_BIT_LE 0x10000000
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#define ME4000_AI_STATUS_BIT_FSM 0x20000000
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/*=============================================================================
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Bits for the ME4000_IRQ_STATUS_REG register
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===========================================================================*/
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#define ME4000_IRQ_STATUS_BIT_EX 0x01
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#define ME4000_IRQ_STATUS_BIT_LE 0x02
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#define ME4000_IRQ_STATUS_BIT_AI_HF 0x04
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#define ME4000_IRQ_STATUS_BIT_AO_0_HF 0x08
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#define ME4000_IRQ_STATUS_BIT_AO_1_HF 0x10
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#define ME4000_IRQ_STATUS_BIT_AO_2_HF 0x20
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#define ME4000_IRQ_STATUS_BIT_AO_3_HF 0x40
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#define ME4000_IRQ_STATUS_BIT_SC 0x80
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/*=============================================================================
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Bits for the ME4000_DIO_CTRL_REG register
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===========================================================================*/
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#define ME4000_DIO_CTRL_BIT_MODE_0 0x0001
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#define ME4000_DIO_CTRL_BIT_MODE_1 0x0002
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#define ME4000_DIO_CTRL_BIT_MODE_2 0x0004
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#define ME4000_DIO_CTRL_BIT_MODE_3 0x0008
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#define ME4000_DIO_CTRL_BIT_MODE_4 0x0010
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#define ME4000_DIO_CTRL_BIT_MODE_5 0x0020
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#define ME4000_DIO_CTRL_BIT_MODE_6 0x0040
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#define ME4000_DIO_CTRL_BIT_MODE_7 0x0080
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#define ME4000_DIO_CTRL_BIT_FUNCTION_0 0x0100
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#define ME4000_DIO_CTRL_BIT_FUNCTION_1 0x0200
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#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_0 0x0400
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#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_1 0x0800
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#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_2 0x1000
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#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_3 0x2000
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/*=============================================================================
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Information about the hardware capabilities
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===========================================================================*/
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typedef struct me4000_ao_info {
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int count;
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int fifo_count;
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} me4000_ao_info_t;
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typedef struct me4000_ai_info {
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int count;
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int sh_count;
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int diff_count;
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int ex_trig_analog;
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} me4000_ai_info_t;
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typedef struct me4000_dio_info {
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int count;
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} me4000_dio_info_t;
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typedef struct me4000_cnt_info {
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int count;
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} me4000_cnt_info_t;
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typedef struct me4000_board {
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const char *name;
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unsigned short device_id;
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me4000_ao_info_t ao;
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me4000_ai_info_t ai;
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me4000_dio_info_t dio;
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me4000_cnt_info_t cnt;
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} me4000_board_t;
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#define thisboard ((const me4000_board_t *)dev->board_ptr)
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/*=============================================================================
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Global board and subdevice information structures
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===========================================================================*/
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typedef struct me4000_ao_context {
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int irq;
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unsigned long mirror; // Store the last written value
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unsigned long ctrl_reg;
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unsigned long status_reg;
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unsigned long fifo_reg;
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unsigned long single_reg;
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unsigned long timer_reg;
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unsigned long irq_status_reg;
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unsigned long preload_reg;
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} me4000_ao_context_t;
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typedef struct me4000_ai_context {
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int irq;
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unsigned long ctrl_reg;
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unsigned long status_reg;
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unsigned long channel_list_reg;
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unsigned long data_reg;
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unsigned long chan_timer_reg;
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unsigned long chan_pre_timer_reg;
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unsigned long scan_timer_low_reg;
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unsigned long scan_timer_high_reg;
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unsigned long scan_pre_timer_low_reg;
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unsigned long scan_pre_timer_high_reg;
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unsigned long start_reg;
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unsigned long irq_status_reg;
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unsigned long sample_counter_reg;
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} me4000_ai_context_t;
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typedef struct me4000_dio_context {
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unsigned long dir_reg;
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unsigned long ctrl_reg;
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unsigned long port_0_reg;
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unsigned long port_1_reg;
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unsigned long port_2_reg;
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unsigned long port_3_reg;
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} me4000_dio_context_t;
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typedef struct me4000_cnt_context {
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unsigned long ctrl_reg;
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unsigned long counter_0_reg;
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unsigned long counter_1_reg;
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unsigned long counter_2_reg;
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} me4000_cnt_context_t;
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typedef struct me4000_info {
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unsigned long plx_regbase; // PLX configuration space base address
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unsigned long me4000_regbase; // Base address of the ME4000
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unsigned long timer_regbase; // Base address of the timer circuit
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unsigned long program_regbase; // Base address to set the program pin for the xilinx
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unsigned long plx_regbase_size; // PLX register set space
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unsigned long me4000_regbase_size; // ME4000 register set space
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unsigned long timer_regbase_size; // Timer circuit register set space
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unsigned long program_regbase_size; // Size of program base address of the ME4000
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unsigned int serial_no; // Serial number of the board
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unsigned char hw_revision; // Hardware revision of the board
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unsigned short vendor_id; // Meilhaus vendor id
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unsigned short device_id; // Device id
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struct pci_dev *pci_dev_p; // General PCI information
|
||||
|
||||
unsigned int irq; // IRQ assigned from the PCI BIOS
|
||||
|
||||
struct me4000_ai_context ai_context; // Analog input specific context
|
||||
struct me4000_ao_context ao_context[4]; // Vector with analog output specific context
|
||||
struct me4000_dio_context dio_context; // Digital I/O specific context
|
||||
struct me4000_cnt_context cnt_context; // Counter specific context
|
||||
} me4000_info_t;
|
||||
|
||||
#define info ((me4000_info_t *)dev->private)
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
Defines for analog input
|
||||
----------------------------------------------------------------------------*/
|
||||
|
||||
/* General stuff */
|
||||
#define ME4000_AI_FIFO_COUNT 2048
|
||||
|
||||
#define ME4000_AI_MIN_TICKS 66
|
||||
#define ME4000_AI_MIN_SAMPLE_TIME 2000 // Minimum sample time [ns]
|
||||
#define ME4000_AI_BASE_FREQUENCY (unsigned int) 33E6
|
||||
|
||||
/* Channel list defines and masks */
|
||||
#define ME4000_AI_CHANNEL_LIST_COUNT 1024
|
||||
|
||||
#define ME4000_AI_LIST_INPUT_SINGLE_ENDED 0x000
|
||||
#define ME4000_AI_LIST_INPUT_DIFFERENTIAL 0x020
|
||||
|
||||
#define ME4000_AI_LIST_RANGE_BIPOLAR_10 0x000
|
||||
#define ME4000_AI_LIST_RANGE_BIPOLAR_2_5 0x040
|
||||
#define ME4000_AI_LIST_RANGE_UNIPOLAR_10 0x080
|
||||
#define ME4000_AI_LIST_RANGE_UNIPOLAR_2_5 0x0C0
|
||||
|
||||
#define ME4000_AI_LIST_LAST_ENTRY 0x100
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
Defines for counters
|
||||
----------------------------------------------------------------------------*/
|
||||
|
||||
#define ME4000_CNT_COUNTER_0 0x00
|
||||
#define ME4000_CNT_COUNTER_1 0x40
|
||||
#define ME4000_CNT_COUNTER_2 0x80
|
||||
|
||||
#define ME4000_CNT_MODE_0 0x00 // Change state if zero crossing
|
||||
#define ME4000_CNT_MODE_1 0x02 // Retriggerable One-Shot
|
||||
#define ME4000_CNT_MODE_2 0x04 // Asymmetrical divider
|
||||
#define ME4000_CNT_MODE_3 0x06 // Symmetrical divider
|
||||
#define ME4000_CNT_MODE_4 0x08 // Counter start by software trigger
|
||||
#define ME4000_CNT_MODE_5 0x0A // Counter start by hardware trigger
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue