Merge branch 'lorenzo/pci/rockchip'
- update arm64 defconfig for Rockchip (Shawn Lin)
- refactor Rockchip code to facilitate both root port and endpoint mode
(Shawn Lin)
- add Rockchip endpoint mode driver (Shawn Lin)
* lorenzo/pci/rockchip:
arm64: defconfig: update config for Rockchip PCIe
dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe EP driver
PCI: rockchip: Add EP driver for Rockchip PCIe controller
dt-bindings: PCI: rockchip: Rename rockchip-pcie.txt to rockchip-pcie-host.txt
PCI: rockchip: Split out common function to init controller
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT
PCI: rockchip: Separate common code from RC driver
# Conflicts:
# drivers/pci/host/pcie-rockchip.c
This commit is contained in:
Bjorn Helgaas
commit
e52d38f4ab
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|
@ -0,0 +1,62 @@
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* Rockchip AXI PCIe Endpoint Controller DT description
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Required properties:
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- compatible: Should contain "rockchip,rk3399-pcie-ep"
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- reg: Two register ranges as listed in the reg-names property
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- reg-names: Must include the following names
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- "apb-base"
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- "mem-base"
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- "aclk"
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- "aclk-perf"
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- "hclk"
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- "pm"
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- resets: Must contain seven entries for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following names
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- "core"
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- "mgmt"
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- "mgmt-sticky"
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- "pipe"
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- "pm"
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- "aclk"
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- "pclk"
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- pinctrl-names : The pin control state names
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- pinctrl-0: The "default" pinctrl state
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- phys: Must contain an phandle to a PHY for each entry in phy-names.
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- phy-names: Must include 4 entries for all 4 lanes even if some of
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them won't be used for your cases. Entries are of the form "pcie-phy-N":
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where N ranges from 0 to 3.
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(see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
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for changing the #phy-cells of phy node to support it)
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- rockchip,max-outbound-regions: Maximum number of outbound regions
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Optional Property:
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- num-lanes: number of lanes to use
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- max-functions: Maximum number of functions that can be configured (default 1).
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pcie0-ep: pcie@f8000000 {
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compatible = "rockchip,rk3399-pcie-ep";
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#address-cells = <3>;
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#size-cells = <2>;
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rockchip,max-outbound-regions = <16>;
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clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
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<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
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clock-names = "aclk", "aclk-perf",
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"hclk", "pm";
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max-functions = /bits/ 8 <8>;
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num-lanes = <4>;
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reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
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reg-names = "apb-base", "mem-base";
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resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
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<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
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<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
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reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
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"pm", "pclk", "aclk";
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phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
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phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_clkreq>;
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};
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@ -10947,8 +10947,8 @@ M: Shawn Lin <shawn.lin@rock-chips.com>
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L: linux-pci@vger.kernel.org
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L: linux-rockchip@lists.infradead.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/rockchip-pcie.txt
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F: drivers/pci/host/pcie-rockchip.c
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F: Documentation/devicetree/bindings/pci/rockchip-pcie*
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F: drivers/pci/host/pcie-rockchip*
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PCI DRIVER FOR V3 SEMICONDUCTOR V360EPC
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M: Linus Walleij <linus.walleij@linaro.org>
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|
|
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@ -78,7 +78,8 @@ CONFIG_PCIE_ARMADA_8K=y
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CONFIG_PCI_AARDVARK=y
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CONFIG_PCI_TEGRA=y
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CONFIG_PCIE_RCAR=y
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CONFIG_PCIE_ROCKCHIP=m
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CONFIG_PCIE_ROCKCHIP=y
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CONFIG_PCIE_ROCKCHIP_HOST=m
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CONFIG_PCI_HOST_GENERIC=y
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CONFIG_PCI_XGENE=y
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CONFIG_PCI_HOST_THUNDER_PEM=y
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|
|
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@ -179,16 +179,33 @@ config PCI_HOST_THUNDER_ECAM
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Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
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config PCIE_ROCKCHIP
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tristate "Rockchip PCIe controller"
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bool
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depends on PCI
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config PCIE_ROCKCHIP_HOST
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tristate "Rockchip PCIe host controller"
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depends on ARCH_ROCKCHIP || COMPILE_TEST
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depends on OF
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depends on PCI_MSI_IRQ_DOMAIN
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select MFD_SYSCON
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select PCIE_ROCKCHIP
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help
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Say Y here if you want internal PCI support on Rockchip SoC.
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There is 1 internal PCIe port available to support GEN2 with
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4 slots.
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config PCIE_ROCKCHIP_EP
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bool "Rockchip PCIe endpoint controller"
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depends on ARCH_ROCKCHIP || COMPILE_TEST
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depends on OF
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depends on PCI_ENDPOINT
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select MFD_SYSCON
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select PCIE_ROCKCHIP
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help
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Say Y here if you want to support Rockchip PCIe controller in
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endpoint mode on Rockchip SoC. There is 1 internal PCIe port
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available to support GEN2 with 4 slots.
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config PCIE_MEDIATEK
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bool "MediaTek PCIe controller"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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|
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@ -20,6 +20,8 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
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obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
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obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
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obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
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obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
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obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
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obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
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obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
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obj-$(CONFIG_VMD) += vmd.o
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@ -0,0 +1,642 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Rockchip AXI PCIe endpoint controller driver
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*
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* Copyright (c) 2018 Rockchip, Inc.
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*
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* Author: Shawn Lin <shawn.lin@rock-chips.com>
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* Simon Xue <xxm@rock-chips.com>
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*/
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#include <linux/configfs.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/pci-epc.h>
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#include <linux/platform_device.h>
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#include <linux/pci-epf.h>
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#include <linux/sizes.h>
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#include "pcie-rockchip.h"
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|
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/**
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* struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
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* @rockchip: Rockchip PCIe controller
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* @max_regions: maximum number of regions supported by hardware
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* @ob_region_map: bitmask of mapped outbound regions
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* @ob_addr: base addresses in the AXI bus where the outbound regions start
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* @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ
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* dedicated outbound regions is mapped.
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* @irq_cpu_addr: base address in the CPU space where a write access triggers
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* the sending of a memory write (MSI) / normal message (legacy
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* IRQ) TLP through the PCIe bus.
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* @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ
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* dedicated outbound region.
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* @irq_pci_fn: the latest PCI function that has updated the mapping of
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* the MSI/legacy IRQ dedicated outbound region.
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* @irq_pending: bitmask of asserted legacy IRQs.
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*/
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struct rockchip_pcie_ep {
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struct rockchip_pcie rockchip;
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struct pci_epc *epc;
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u32 max_regions;
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unsigned long ob_region_map;
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phys_addr_t *ob_addr;
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phys_addr_t irq_phys_addr;
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void __iomem *irq_cpu_addr;
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u64 irq_pci_addr;
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u8 irq_pci_fn;
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u8 irq_pending;
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};
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static void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip,
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u32 region)
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{
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rockchip_pcie_write(rockchip, 0,
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ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(region));
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rockchip_pcie_write(rockchip, 0,
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ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(region));
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rockchip_pcie_write(rockchip, 0,
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ROCKCHIP_PCIE_AT_OB_REGION_DESC0(region));
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rockchip_pcie_write(rockchip, 0,
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ROCKCHIP_PCIE_AT_OB_REGION_DESC1(region));
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rockchip_pcie_write(rockchip, 0,
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ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(region));
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rockchip_pcie_write(rockchip, 0,
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ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(region));
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}
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static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn,
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u32 r, u32 type, u64 cpu_addr,
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u64 pci_addr, size_t size)
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{
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u64 sz = 1ULL << fls64(size - 1);
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int num_pass_bits = ilog2(sz);
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u32 addr0, addr1, desc0, desc1;
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bool is_nor_msg = (type == AXI_WRAPPER_NOR_MSG);
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/* The minimal region size is 1MB */
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if (num_pass_bits < 8)
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num_pass_bits = 8;
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cpu_addr -= rockchip->mem_res->start;
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addr0 = ((is_nor_msg ? 0x10 : (num_pass_bits - 1)) &
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PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) |
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(lower_32_bits(cpu_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR);
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addr1 = upper_32_bits(is_nor_msg ? cpu_addr : pci_addr);
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desc0 = ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(fn) | type;
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desc1 = 0;
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|
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if (is_nor_msg) {
|
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rockchip_pcie_write(rockchip, 0,
|
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ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r));
|
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rockchip_pcie_write(rockchip, 0,
|
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ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r));
|
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rockchip_pcie_write(rockchip, desc0,
|
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ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r));
|
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rockchip_pcie_write(rockchip, desc1,
|
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ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r));
|
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} else {
|
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/* PCI bus address region */
|
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rockchip_pcie_write(rockchip, addr0,
|
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ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r));
|
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rockchip_pcie_write(rockchip, addr1,
|
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ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r));
|
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rockchip_pcie_write(rockchip, desc0,
|
||||
ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r));
|
||||
rockchip_pcie_write(rockchip, desc1,
|
||||
ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r));
|
||||
|
||||
addr0 =
|
||||
((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) |
|
||||
(lower_32_bits(cpu_addr) &
|
||||
PCIE_CORE_OB_REGION_ADDR0_LO_ADDR);
|
||||
addr1 = upper_32_bits(cpu_addr);
|
||||
}
|
||||
|
||||
/* CPU bus address region */
|
||||
rockchip_pcie_write(rockchip, addr0,
|
||||
ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r));
|
||||
rockchip_pcie_write(rockchip, addr1,
|
||||
ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r));
|
||||
}
|
||||
|
||||
static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn,
|
||||
struct pci_epf_header *hdr)
|
||||
{
|
||||
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
|
||||
struct rockchip_pcie *rockchip = &ep->rockchip;
|
||||
|
||||
/* All functions share the same vendor ID with function 0 */
|
||||
if (fn == 0) {
|
||||
u32 vid_regs = (hdr->vendorid & GENMASK(15, 0)) |
|
||||
(hdr->subsys_vendor_id & GENMASK(31, 16)) << 16;
|
||||
|
||||
rockchip_pcie_write(rockchip, vid_regs,
|
||||
PCIE_CORE_CONFIG_VENDOR);
|
||||
}
|
||||
|
||||
rockchip_pcie_write(rockchip, hdr->deviceid << 16,
|
||||
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_VENDOR_ID);
|
||||
|
||||
rockchip_pcie_write(rockchip,
|
||||
hdr->revid |
|
||||
hdr->progif_code << 8 |
|
||||
hdr->subclass_code << 16 |
|
||||
hdr->baseclass_code << 24,
|
||||
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_REVISION_ID);
|
||||
rockchip_pcie_write(rockchip, hdr->cache_line_size,
|
||||
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
|
||||
PCI_CACHE_LINE_SIZE);
|
||||
rockchip_pcie_write(rockchip, hdr->subsys_id << 16,
|
||||
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
|
||||
PCI_SUBSYSTEM_VENDOR_ID);
|
||||
rockchip_pcie_write(rockchip, hdr->interrupt_pin << 8,
|
||||
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
|
||||
PCI_INTERRUPT_LINE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn,
|
||||
struct pci_epf_bar *epf_bar)
|
||||
{
|
||||
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
|
||||
struct rockchip_pcie *rockchip = &ep->rockchip;
|
||||
dma_addr_t bar_phys = epf_bar->phys_addr;
|
||||
enum pci_barno bar = epf_bar->barno;
|
||||
int flags = epf_bar->flags;
|
||||
u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
|
||||
u64 sz;
|
||||
|
||||
/* BAR size is 2^(aperture + 7) */
|
||||
sz = max_t(size_t, epf_bar->size, MIN_EP_APERTURE);
|
||||
|
||||
/*
|
||||
* roundup_pow_of_two() returns an unsigned long, which is not suited
|
||||
* for 64bit values.
|
||||
*/
|
||||
sz = 1ULL << fls64(sz - 1);
|
||||
aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
|
||||
|
||||
if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
|
||||
ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS;
|
||||
} else {
|
||||
bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
|
||||
bool is_64bits = sz > SZ_2G;
|
||||
|
||||
if (is_64bits && (bar & 1))
|
||||
return -EINVAL;
|
||||
|
||||
if (is_64bits && is_prefetch)
|
||||
ctrl =
|
||||
ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
|
||||
else if (is_prefetch)
|
||||
ctrl =
|
||||
ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
|
||||
else if (is_64bits)
|
||||
ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS;
|
||||
else
|
||||
ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS;
|
||||
}
|
||||
|
||||
if (bar < BAR_4) {
|
||||
reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn);
|
||||
b = bar;
|
||||
} else {
|
||||
reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn);
|
||||
b = bar - BAR_4;
|
||||
}
|
||||
|
||||
addr0 = lower_32_bits(bar_phys);
|
||||
addr1 = upper_32_bits(bar_phys);
|
||||
|
||||
cfg = rockchip_pcie_read(rockchip, reg);
|
||||
cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
|
||||
ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
|
||||
cfg |= (ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
|
||||
ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
|
||||
|
||||
rockchip_pcie_write(rockchip, cfg, reg);
|
||||
rockchip_pcie_write(rockchip, addr0,
|
||||
ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar));
|
||||
rockchip_pcie_write(rockchip, addr1,
|
||||
ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rockchip_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn,
|
||||
struct pci_epf_bar *epf_bar)
|
||||
{
|
||||
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
|
||||
struct rockchip_pcie *rockchip = &ep->rockchip;
|
||||
u32 reg, cfg, b, ctrl;
|
||||
enum pci_barno bar = epf_bar->barno;
|
||||
|
||||
if (bar < BAR_4) {
|
||||
reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn);
|
||||
b = bar;
|
||||
} else {
|
||||
reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn);
|
||||
b = bar - BAR_4;
|
||||
}
|
||||
|
||||
ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED;
|
||||
cfg = rockchip_pcie_read(rockchip, reg);
|
||||
cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
|
||||
ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
|
||||
cfg |= ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
|
||||
|
||||
rockchip_pcie_write(rockchip, cfg, reg);
|
||||
rockchip_pcie_write(rockchip, 0x0,
|
||||
ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar));
|
||||
rockchip_pcie_write(rockchip, 0x0,
|
||||
ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar));
|
||||
}
|
||||
|
||||
static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn,
|
||||
phys_addr_t addr, u64 pci_addr,
|
||||
size_t size)
|
||||
{
|
||||
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
|
||||
struct rockchip_pcie *pcie = &ep->rockchip;
|
||||
u32 r;
|
||||
|
||||
r = find_first_zero_bit(&ep->ob_region_map,
|
||||
sizeof(ep->ob_region_map) * BITS_PER_LONG);
|
||||
/*
|
||||
* Region 0 is reserved for configuration space and shouldn't
|
||||
* be used elsewhere per TRM, so leave it out.
|
||||
*/
|
||||
if (r >= ep->max_regions - 1) {
|
||||
dev_err(&epc->dev, "no free outbound region\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
rockchip_pcie_prog_ep_ob_atu(pcie, fn, r, AXI_WRAPPER_MEM_WRITE, addr,
|
||||
pci_addr, size);
|
||||
|
||||
set_bit(r, &ep->ob_region_map);
|
||||
ep->ob_addr[r] = addr;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rockchip_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn,
|
||||
phys_addr_t addr)
|
||||
{
|
||||
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
|
||||
struct rockchip_pcie *rockchip = &ep->rockchip;
|
||||
u32 r;
|
||||
|
||||
for (r = 0; r < ep->max_regions - 1; r++)
|
||||
if (ep->ob_addr[r] == addr)
|
||||
break;
|
||||
|
||||
/*
|
||||
* Region 0 is reserved for configuration space and shouldn't
|
||||
* be used elsewhere per TRM, so leave it out.
|
||||
*/
|
||||
if (r == ep->max_regions - 1)
|
||||
return;
|
||||
|
||||
rockchip_pcie_clear_ep_ob_atu(rockchip, r);
|
||||
|
||||
ep->ob_addr[r] = 0;
|
||||
clear_bit(r, &ep->ob_region_map);
|
||||
}
|
||||
|
||||
static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn,
|
||||
u8 multi_msg_cap)
|
||||
{
|
||||
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
|
||||
struct rockchip_pcie *rockchip = &ep->rockchip;
|
||||
u16 flags;
|
||||
|
||||
flags = rockchip_pcie_read(rockchip,
|
||||
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
|
||||
ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
|
||||
flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK;
|
||||
flags |=
|
||||
((multi_msg_cap << 1) << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) |
|
||||
PCI_MSI_FLAGS_64BIT;
|
||||
flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP;
|
||||
rockchip_pcie_write(rockchip, flags,
|
||||
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
|
||||
ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn)
|
||||
{
|
||||
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
|
||||
struct rockchip_pcie *rockchip = &ep->rockchip;
|
||||
u16 flags;
|
||||
|
||||
flags = rockchip_pcie_read(rockchip,
|
||||
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
|
||||
ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
|
||||
if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME))
|
||||
return -EINVAL;
|
||||
|
||||
return ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >>
|
||||
ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET);
|
||||
}
|
||||
|
||||
static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn,
|
||||
u8 intx, bool is_asserted)
|
||||
{
|
||||
struct rockchip_pcie *rockchip = &ep->rockchip;
|
||||
u32 r = ep->max_regions - 1;
|
||||
u32 offset;
|
||||
u16 status;
|
||||
u8 msg_code;
|
||||
|
||||
if (unlikely(ep->irq_pci_addr != ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR ||
|
||||
ep->irq_pci_fn != fn)) {
|
||||
rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r,
|
||||
AXI_WRAPPER_NOR_MSG,
|
||||
ep->irq_phys_addr, 0, 0);
|
||||
ep->irq_pci_addr = ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR;
|
||||
ep->irq_pci_fn = fn;
|
||||
}
|
||||
|
||||
intx &= 3;
|
||||
if (is_asserted) {
|
||||
ep->irq_pending |= BIT(intx);
|
||||
msg_code = ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTA + intx;
|
||||
} else {
|
||||
ep->irq_pending &= ~BIT(intx);
|
||||
msg_code = ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA + intx;
|
||||
}
|
||||
|
||||
status = rockchip_pcie_read(rockchip,
|
||||
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
|
||||
ROCKCHIP_PCIE_EP_CMD_STATUS);
|
||||
status &= ROCKCHIP_PCIE_EP_CMD_STATUS_IS;
|
||||
|
||||
if ((status != 0) ^ (ep->irq_pending != 0)) {
|
||||
status ^= ROCKCHIP_PCIE_EP_CMD_STATUS_IS;
|
||||
rockchip_pcie_write(rockchip, status,
|
||||
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
|
||||
ROCKCHIP_PCIE_EP_CMD_STATUS);
|
||||
}
|
||||
|
||||
offset =
|
||||
ROCKCHIP_PCIE_MSG_ROUTING(ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX) |
|
||||
ROCKCHIP_PCIE_MSG_CODE(msg_code) | ROCKCHIP_PCIE_MSG_NO_DATA;
|
||||
writel(0, ep->irq_cpu_addr + offset);
|
||||
}
|
||||
|
||||
static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn,
|
||||
u8 intx)
|
||||
{
|
||||
u16 cmd;
|
||||
|
||||
cmd = rockchip_pcie_read(&ep->rockchip,
|
||||
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
|
||||
ROCKCHIP_PCIE_EP_CMD_STATUS);
|
||||
|
||||
if (cmd & PCI_COMMAND_INTX_DISABLE)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* Should add some delay between toggling INTx per TRM vaguely saying
|
||||
* it depends on some cycles of the AHB bus clock to function it. So
|
||||
* add sufficient 1ms here.
|
||||
*/
|
||||
rockchip_pcie_ep_assert_intx(ep, fn, intx, true);
|
||||
mdelay(1);
|
||||
rockchip_pcie_ep_assert_intx(ep, fn, intx, false);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn,
|
||||
u8 interrupt_num)
|
||||
{
|
||||
struct rockchip_pcie *rockchip = &ep->rockchip;
|
||||
u16 flags, mme, data, data_mask;
|
||||
u8 msi_count;
|
||||
u64 pci_addr, pci_addr_mask = 0xff;
|
||||
|
||||
/* Check MSI enable bit */
|
||||
flags = rockchip_pcie_read(&ep->rockchip,
|
||||
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
|
||||
ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
|
||||
if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME))
|
||||
return -EINVAL;
|
||||
|
||||
/* Get MSI numbers from MME */
|
||||
mme = ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >>
|
||||
ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET);
|
||||
msi_count = 1 << mme;
|
||||
if (!interrupt_num || interrupt_num > msi_count)
|
||||
return -EINVAL;
|
||||
|
||||
/* Set MSI private data */
|
||||
data_mask = msi_count - 1;
|
||||
data = rockchip_pcie_read(rockchip,
|
||||
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
|
||||
ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
|
||||
PCI_MSI_DATA_64);
|
||||
data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask);
|
||||
|
||||
/* Get MSI PCI address */
|
||||
pci_addr = rockchip_pcie_read(rockchip,
|
||||
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
|
||||
ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
|
||||
PCI_MSI_ADDRESS_HI);
|
||||
pci_addr <<= 32;
|
||||
pci_addr |= rockchip_pcie_read(rockchip,
|
||||
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
|
||||
ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
|
||||
PCI_MSI_ADDRESS_LO);
|
||||
pci_addr &= GENMASK_ULL(63, 2);
|
||||
|
||||
/* Set the outbound region if needed. */
|
||||
if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) ||
|
||||
ep->irq_pci_fn != fn)) {
|
||||
rockchip_pcie_prog_ep_ob_atu(rockchip, fn, ep->max_regions - 1,
|
||||
AXI_WRAPPER_MEM_WRITE,
|
||||
ep->irq_phys_addr,
|
||||
pci_addr & ~pci_addr_mask,
|
||||
pci_addr_mask + 1);
|
||||
ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
|
||||
ep->irq_pci_fn = fn;
|
||||
}
|
||||
|
||||
writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
|
||||
enum pci_epc_irq_type type,
|
||||
u8 interrupt_num)
|
||||
{
|
||||
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
|
||||
|
||||
switch (type) {
|
||||
case PCI_EPC_IRQ_LEGACY:
|
||||
return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0);
|
||||
case PCI_EPC_IRQ_MSI:
|
||||
return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static int rockchip_pcie_ep_start(struct pci_epc *epc)
|
||||
{
|
||||
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
|
||||
struct rockchip_pcie *rockchip = &ep->rockchip;
|
||||
struct pci_epf *epf;
|
||||
u32 cfg;
|
||||
|
||||
cfg = BIT(0);
|
||||
list_for_each_entry(epf, &epc->pci_epf, list)
|
||||
cfg |= BIT(epf->func_no);
|
||||
|
||||
rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG);
|
||||
|
||||
list_for_each_entry(epf, &epc->pci_epf, list)
|
||||
pci_epf_linkup(epf);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct pci_epc_ops rockchip_pcie_epc_ops = {
|
||||
.write_header = rockchip_pcie_ep_write_header,
|
||||
.set_bar = rockchip_pcie_ep_set_bar,
|
||||
.clear_bar = rockchip_pcie_ep_clear_bar,
|
||||
.map_addr = rockchip_pcie_ep_map_addr,
|
||||
.unmap_addr = rockchip_pcie_ep_unmap_addr,
|
||||
.set_msi = rockchip_pcie_ep_set_msi,
|
||||
.get_msi = rockchip_pcie_ep_get_msi,
|
||||
.raise_irq = rockchip_pcie_ep_raise_irq,
|
||||
.start = rockchip_pcie_ep_start,
|
||||
};
|
||||
|
||||
static int rockchip_pcie_parse_ep_dt(struct rockchip_pcie *rockchip,
|
||||
struct rockchip_pcie_ep *ep)
|
||||
{
|
||||
struct device *dev = rockchip->dev;
|
||||
int err;
|
||||
|
||||
err = rockchip_pcie_parse_dt(rockchip);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = rockchip_pcie_get_phys(rockchip);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = of_property_read_u32(dev->of_node,
|
||||
"rockchip,max-outbound-regions",
|
||||
&ep->max_regions);
|
||||
if (err < 0 || ep->max_regions > MAX_REGION_LIMIT)
|
||||
ep->max_regions = MAX_REGION_LIMIT;
|
||||
|
||||
err = of_property_read_u8(dev->of_node, "max-functions",
|
||||
&ep->epc->max_functions);
|
||||
if (err < 0)
|
||||
ep->epc->max_functions = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rockchip_pcie_ep_of_match[] = {
|
||||
{ .compatible = "rockchip,rk3399-pcie-ep"},
|
||||
{},
|
||||
};
|
||||
|
||||
static int rockchip_pcie_ep_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct rockchip_pcie_ep *ep;
|
||||
struct rockchip_pcie *rockchip;
|
||||
struct pci_epc *epc;
|
||||
size_t max_regions;
|
||||
int err;
|
||||
|
||||
ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
|
||||
if (!ep)
|
||||
return -ENOMEM;
|
||||
|
||||
rockchip = &ep->rockchip;
|
||||
rockchip->is_rc = false;
|
||||
rockchip->dev = dev;
|
||||
|
||||
epc = devm_pci_epc_create(dev, &rockchip_pcie_epc_ops);
|
||||
if (IS_ERR(epc)) {
|
||||
dev_err(dev, "failed to create epc device\n");
|
||||
return PTR_ERR(epc);
|
||||
}
|
||||
|
||||
ep->epc = epc;
|
||||
epc_set_drvdata(epc, ep);
|
||||
|
||||
err = rockchip_pcie_parse_ep_dt(rockchip, ep);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = rockchip_pcie_enable_clocks(rockchip);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = rockchip_pcie_init_port(rockchip);
|
||||
if (err)
|
||||
goto err_disable_clocks;
|
||||
|
||||
/* Establish the link automatically */
|
||||
rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
|
||||
PCIE_CLIENT_CONFIG);
|
||||
|
||||
max_regions = ep->max_regions;
|
||||
ep->ob_addr = devm_kzalloc(dev, max_regions * sizeof(*ep->ob_addr),
|
||||
GFP_KERNEL);
|
||||
|
||||
if (!ep->ob_addr) {
|
||||
err = -ENOMEM;
|
||||
goto err_uninit_port;
|
||||
}
|
||||
|
||||
/* Only enable function 0 by default */
|
||||
rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG);
|
||||
|
||||
err = pci_epc_mem_init(epc, rockchip->mem_res->start,
|
||||
resource_size(rockchip->mem_res));
|
||||
if (err < 0) {
|
||||
dev_err(dev, "failed to initialize the memory space\n");
|
||||
goto err_uninit_port;
|
||||
}
|
||||
|
||||
ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
|
||||
SZ_128K);
|
||||
if (!ep->irq_cpu_addr) {
|
||||
dev_err(dev, "failed to reserve memory space for MSI\n");
|
||||
err = -ENOMEM;
|
||||
goto err_epc_mem_exit;
|
||||
}
|
||||
|
||||
ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR;
|
||||
|
||||
return 0;
|
||||
err_epc_mem_exit:
|
||||
pci_epc_mem_exit(epc);
|
||||
err_uninit_port:
|
||||
rockchip_pcie_deinit_phys(rockchip);
|
||||
err_disable_clocks:
|
||||
rockchip_pcie_disable_clocks(rockchip);
|
||||
return err;
|
||||
}
|
||||
|
||||
static struct platform_driver rockchip_pcie_ep_driver = {
|
||||
.driver = {
|
||||
.name = "rockchip-pcie-ep",
|
||||
.of_match_table = rockchip_pcie_ep_of_match,
|
||||
},
|
||||
.probe = rockchip_pcie_ep_probe,
|
||||
};
|
||||
|
||||
builtin_platform_driver(rockchip_pcie_ep_driver);
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,338 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Rockchip AXI PCIe controller driver
|
||||
*
|
||||
* Copyright (c) 2018 Rockchip, Inc.
|
||||
*
|
||||
* Author: Shawn Lin <shawn.lin@rock-chips.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _PCIE_ROCKCHIP_H
|
||||
#define _PCIE_ROCKCHIP_H
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
/*
|
||||
* The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
|
||||
* bits. This allows atomic updates of the register without locking.
|
||||
*/
|
||||
#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
|
||||
#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
|
||||
|
||||
#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
|
||||
#define MAX_LANE_NUM 4
|
||||
#define MAX_REGION_LIMIT 32
|
||||
#define MIN_EP_APERTURE 28
|
||||
|
||||
#define PCIE_CLIENT_BASE 0x0
|
||||
#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
|
||||
#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
|
||||
#define PCIE_CLIENT_CONF_DISABLE HIWORD_UPDATE(0x0001, 0)
|
||||
#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
|
||||
#define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008)
|
||||
#define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
|
||||
#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
|
||||
#define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0)
|
||||
#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
|
||||
#define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080)
|
||||
#define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c)
|
||||
#define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0)
|
||||
#define PCIE_CLIENT_DEBUG_LTSSM_L1 0x18
|
||||
#define PCIE_CLIENT_DEBUG_LTSSM_L2 0x19
|
||||
#define PCIE_CLIENT_BASIC_STATUS1 (PCIE_CLIENT_BASE + 0x48)
|
||||
#define PCIE_CLIENT_LINK_STATUS_UP 0x00300000
|
||||
#define PCIE_CLIENT_LINK_STATUS_MASK 0x00300000
|
||||
#define PCIE_CLIENT_INT_MASK (PCIE_CLIENT_BASE + 0x4c)
|
||||
#define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
|
||||
#define PCIE_CLIENT_INTR_MASK GENMASK(8, 5)
|
||||
#define PCIE_CLIENT_INTR_SHIFT 5
|
||||
#define PCIE_CLIENT_INT_LEGACY_DONE BIT(15)
|
||||
#define PCIE_CLIENT_INT_MSG BIT(14)
|
||||
#define PCIE_CLIENT_INT_HOT_RST BIT(13)
|
||||
#define PCIE_CLIENT_INT_DPA BIT(12)
|
||||
#define PCIE_CLIENT_INT_FATAL_ERR BIT(11)
|
||||
#define PCIE_CLIENT_INT_NFATAL_ERR BIT(10)
|
||||
#define PCIE_CLIENT_INT_CORR_ERR BIT(9)
|
||||
#define PCIE_CLIENT_INT_INTD BIT(8)
|
||||
#define PCIE_CLIENT_INT_INTC BIT(7)
|
||||
#define PCIE_CLIENT_INT_INTB BIT(6)
|
||||
#define PCIE_CLIENT_INT_INTA BIT(5)
|
||||
#define PCIE_CLIENT_INT_LOCAL BIT(4)
|
||||
#define PCIE_CLIENT_INT_UDMA BIT(3)
|
||||
#define PCIE_CLIENT_INT_PHY BIT(2)
|
||||
#define PCIE_CLIENT_INT_HOT_PLUG BIT(1)
|
||||
#define PCIE_CLIENT_INT_PWR_STCG BIT(0)
|
||||
|
||||
#define PCIE_CLIENT_INT_LEGACY \
|
||||
(PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \
|
||||
PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD)
|
||||
|
||||
#define PCIE_CLIENT_INT_CLI \
|
||||
(PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR | \
|
||||
PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA | \
|
||||
PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG | \
|
||||
PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \
|
||||
PCIE_CLIENT_INT_PHY)
|
||||
|
||||
#define PCIE_CORE_CTRL_MGMT_BASE 0x900000
|
||||
#define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000)
|
||||
#define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008
|
||||
#define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018
|
||||
#define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006
|
||||
#define PCIE_CORE_PL_CONF_LANE_SHIFT 1
|
||||
#define PCIE_CORE_CTRL_PLC1 (PCIE_CORE_CTRL_MGMT_BASE + 0x004)
|
||||
#define PCIE_CORE_CTRL_PLC1_FTS_MASK GENMASK(23, 8)
|
||||
#define PCIE_CORE_CTRL_PLC1_FTS_SHIFT 8
|
||||
#define PCIE_CORE_CTRL_PLC1_FTS_CNT 0xffff
|
||||
#define PCIE_CORE_TXCREDIT_CFG1 (PCIE_CORE_CTRL_MGMT_BASE + 0x020)
|
||||
#define PCIE_CORE_TXCREDIT_CFG1_MUI_MASK 0xFFFF0000
|
||||
#define PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT 16
|
||||
#define PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(x) \
|
||||
(((x) >> 3) << PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT)
|
||||
#define PCIE_CORE_LANE_MAP (PCIE_CORE_CTRL_MGMT_BASE + 0x200)
|
||||
#define PCIE_CORE_LANE_MAP_MASK 0x0000000f
|
||||
#define PCIE_CORE_LANE_MAP_REVERSE BIT(16)
|
||||
#define PCIE_CORE_INT_STATUS (PCIE_CORE_CTRL_MGMT_BASE + 0x20c)
|
||||
#define PCIE_CORE_INT_PRFPE BIT(0)
|
||||
#define PCIE_CORE_INT_CRFPE BIT(1)
|
||||
#define PCIE_CORE_INT_RRPE BIT(2)
|
||||
#define PCIE_CORE_INT_PRFO BIT(3)
|
||||
#define PCIE_CORE_INT_CRFO BIT(4)
|
||||
#define PCIE_CORE_INT_RT BIT(5)
|
||||
#define PCIE_CORE_INT_RTR BIT(6)
|
||||
#define PCIE_CORE_INT_PE BIT(7)
|
||||
#define PCIE_CORE_INT_MTR BIT(8)
|
||||
#define PCIE_CORE_INT_UCR BIT(9)
|
||||
#define PCIE_CORE_INT_FCE BIT(10)
|
||||
#define PCIE_CORE_INT_CT BIT(11)
|
||||
#define PCIE_CORE_INT_UTC BIT(18)
|
||||
#define PCIE_CORE_INT_MMVC BIT(19)
|
||||
#define PCIE_CORE_CONFIG_VENDOR (PCIE_CORE_CTRL_MGMT_BASE + 0x44)
|
||||
#define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210)
|
||||
#define PCIE_CORE_PHY_FUNC_CFG (PCIE_CORE_CTRL_MGMT_BASE + 0x2c0)
|
||||
#define PCIE_RC_BAR_CONF (PCIE_CORE_CTRL_MGMT_BASE + 0x300)
|
||||
#define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED 0x0
|
||||
#define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS 0x1
|
||||
#define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS 0x4
|
||||
#define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5
|
||||
#define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS 0x6
|
||||
#define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7
|
||||
|
||||
#define PCIE_CORE_INT \
|
||||
(PCIE_CORE_INT_PRFPE | PCIE_CORE_INT_CRFPE | \
|
||||
PCIE_CORE_INT_RRPE | PCIE_CORE_INT_CRFO | \
|
||||
PCIE_CORE_INT_RT | PCIE_CORE_INT_RTR | \
|
||||
PCIE_CORE_INT_PE | PCIE_CORE_INT_MTR | \
|
||||
PCIE_CORE_INT_UCR | PCIE_CORE_INT_FCE | \
|
||||
PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \
|
||||
PCIE_CORE_INT_MMVC)
|
||||
|
||||
#define PCIE_RC_RP_ATS_BASE 0x400000
|
||||
#define PCIE_RC_CONFIG_NORMAL_BASE 0x800000
|
||||
#define PCIE_RC_CONFIG_BASE 0xa00000
|
||||
#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
|
||||
#define PCIE_RC_CONFIG_SCC_SHIFT 16
|
||||
#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4)
|
||||
#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
|
||||
#define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff
|
||||
#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
|
||||
#define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8)
|
||||
#define PCIE_RC_CONFIG_DCSR_MPS_MASK GENMASK(7, 5)
|
||||
#define PCIE_RC_CONFIG_DCSR_MPS_256 (0x1 << 5)
|
||||
#define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc)
|
||||
#define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10)
|
||||
#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
|
||||
#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
|
||||
#define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)
|
||||
#define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20)
|
||||
|
||||
#define PCIE_CORE_AXI_CONF_BASE 0xc00000
|
||||
#define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
|
||||
#define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
|
||||
#define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR 0xffffff00
|
||||
#define PCIE_CORE_OB_REGION_ADDR1 (PCIE_CORE_AXI_CONF_BASE + 0x4)
|
||||
#define PCIE_CORE_OB_REGION_DESC0 (PCIE_CORE_AXI_CONF_BASE + 0x8)
|
||||
#define PCIE_CORE_OB_REGION_DESC1 (PCIE_CORE_AXI_CONF_BASE + 0xc)
|
||||
|
||||
#define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
|
||||
#define PCIE_RP_IB_ADDR0 (PCIE_CORE_AXI_INBOUND_BASE + 0x0)
|
||||
#define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f
|
||||
#define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR 0xffffff00
|
||||
#define PCIE_RP_IB_ADDR1 (PCIE_CORE_AXI_INBOUND_BASE + 0x4)
|
||||
|
||||
/* Size of one AXI Region (not Region 0) */
|
||||
#define AXI_REGION_SIZE BIT(20)
|
||||
/* Size of Region 0, equal to sum of sizes of other regions */
|
||||
#define AXI_REGION_0_SIZE (32 * (0x1 << 20))
|
||||
#define OB_REG_SIZE_SHIFT 5
|
||||
#define IB_ROOT_PORT_REG_SIZE_SHIFT 3
|
||||
#define AXI_WRAPPER_IO_WRITE 0x6
|
||||
#define AXI_WRAPPER_MEM_WRITE 0x2
|
||||
#define AXI_WRAPPER_TYPE0_CFG 0xa
|
||||
#define AXI_WRAPPER_TYPE1_CFG 0xb
|
||||
#define AXI_WRAPPER_NOR_MSG 0xc
|
||||
|
||||
#define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
|
||||
#define MIN_AXI_ADDR_BITS_PASSED 8
|
||||
#define PCIE_RC_SEND_PME_OFF 0x11960
|
||||
#define ROCKCHIP_VENDOR_ID 0x1d87
|
||||
#define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20)
|
||||
#define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15)
|
||||
#define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12)
|
||||
#define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0)
|
||||
#define PCIE_ECAM_ADDR(bus, dev, func, reg) \
|
||||
(PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
|
||||
PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
|
||||
#define PCIE_LINK_IS_L2(x) \
|
||||
(((x) & PCIE_CLIENT_DEBUG_LTSSM_MASK) == PCIE_CLIENT_DEBUG_LTSSM_L2)
|
||||
#define PCIE_LINK_UP(x) \
|
||||
(((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
|
||||
#define PCIE_LINK_IS_GEN2(x) \
|
||||
(((x) & PCIE_CORE_PL_CONF_SPEED_MASK) == PCIE_CORE_PL_CONF_SPEED_5G)
|
||||
|
||||
#define RC_REGION_0_ADDR_TRANS_H 0x00000000
|
||||
#define RC_REGION_0_ADDR_TRANS_L 0x00000000
|
||||
#define RC_REGION_0_PASS_BITS (25 - 1)
|
||||
#define RC_REGION_0_TYPE_MASK GENMASK(3, 0)
|
||||
#define MAX_AXI_WRAPPER_REGION_NUM 33
|
||||
|
||||
#define ROCKCHIP_PCIE_MSG_ROUTING_TO_RC 0x0
|
||||
#define ROCKCHIP_PCIE_MSG_ROUTING_VIA_ADDR 0x1
|
||||
#define ROCKCHIP_PCIE_MSG_ROUTING_VIA_ID 0x2
|
||||
#define ROCKCHIP_PCIE_MSG_ROUTING_BROADCAST 0x3
|
||||
#define ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX 0x4
|
||||
#define ROCKCHIP_PCIE_MSG_ROUTING_PME_ACK 0x5
|
||||
#define ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTA 0x20
|
||||
#define ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTB 0x21
|
||||
#define ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTC 0x22
|
||||
#define ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTD 0x23
|
||||
#define ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA 0x24
|
||||
#define ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTB 0x25
|
||||
#define ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTC 0x26
|
||||
#define ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTD 0x27
|
||||
#define ROCKCHIP_PCIE_MSG_ROUTING_MASK GENMASK(7, 5)
|
||||
#define ROCKCHIP_PCIE_MSG_ROUTING(route) \
|
||||
(((route) << 5) & ROCKCHIP_PCIE_MSG_ROUTING_MASK)
|
||||
#define ROCKCHIP_PCIE_MSG_CODE_MASK GENMASK(15, 8)
|
||||
#define ROCKCHIP_PCIE_MSG_CODE(code) \
|
||||
(((code) << 8) & ROCKCHIP_PCIE_MSG_CODE_MASK)
|
||||
#define ROCKCHIP_PCIE_MSG_NO_DATA BIT(16)
|
||||
|
||||
#define ROCKCHIP_PCIE_EP_CMD_STATUS 0x4
|
||||
#define ROCKCHIP_PCIE_EP_CMD_STATUS_IS BIT(19)
|
||||
#define ROCKCHIP_PCIE_EP_MSI_CTRL_REG 0x90
|
||||
#define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET 17
|
||||
#define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK GENMASK(19, 17)
|
||||
#define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET 20
|
||||
#define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK GENMASK(22, 20)
|
||||
#define ROCKCHIP_PCIE_EP_MSI_CTRL_ME BIT(16)
|
||||
#define ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP BIT(24)
|
||||
#define ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR 0x1
|
||||
#define ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR 0x3
|
||||
#define ROCKCHIP_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12))
|
||||
#define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \
|
||||
(PCIE_RC_RP_ATS_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008)
|
||||
#define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \
|
||||
(PCIE_RC_RP_ATS_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r) \
|
||||
(PCIE_RC_RP_ATS_BASE + 0x0000 + ((r) & 0x1f) * 0x0020)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \
|
||||
(((devfn) << 12) & \
|
||||
ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \
|
||||
(((bus) << 20) & ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r) \
|
||||
(PCIE_RC_RP_ATS_BASE + 0x0004 + ((r) & 0x1f) * 0x0020)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \
|
||||
(((devfn) << 24) & ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r) \
|
||||
(PCIE_RC_RP_ATS_BASE + 0x0008 + ((r) & 0x1f) * 0x0020)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r) \
|
||||
(PCIE_RC_RP_ATS_BASE + 0x000c + ((r) & 0x1f) * 0x0020)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r) \
|
||||
(PCIE_RC_RP_ATS_BASE + 0x0018 + ((r) & 0x1f) * 0x0020)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r) \
|
||||
(PCIE_RC_RP_ATS_BASE + 0x001c + ((r) & 0x1f) * 0x0020)
|
||||
|
||||
#define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn) \
|
||||
(PCIE_CORE_CTRL_MGMT_BASE + 0x0240 + (fn) * 0x0008)
|
||||
#define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn) \
|
||||
(PCIE_CORE_CTRL_MGMT_BASE + 0x0244 + (fn) * 0x0008)
|
||||
#define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \
|
||||
(GENMASK(4, 0) << ((b) * 8))
|
||||
#define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \
|
||||
(((a) << ((b) * 8)) & \
|
||||
ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b))
|
||||
#define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \
|
||||
(GENMASK(7, 5) << ((b) * 8))
|
||||
#define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \
|
||||
(((c) << ((b) * 8 + 5)) & \
|
||||
ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))
|
||||
|
||||
struct rockchip_pcie {
|
||||
void __iomem *reg_base; /* DT axi-base */
|
||||
void __iomem *apb_base; /* DT apb-base */
|
||||
bool legacy_phy;
|
||||
struct phy *phys[MAX_LANE_NUM];
|
||||
struct reset_control *core_rst;
|
||||
struct reset_control *mgmt_rst;
|
||||
struct reset_control *mgmt_sticky_rst;
|
||||
struct reset_control *pipe_rst;
|
||||
struct reset_control *pm_rst;
|
||||
struct reset_control *aclk_rst;
|
||||
struct reset_control *pclk_rst;
|
||||
struct clk *aclk_pcie;
|
||||
struct clk *aclk_perf_pcie;
|
||||
struct clk *hclk_pcie;
|
||||
struct clk *clk_pcie_pm;
|
||||
struct regulator *vpcie12v; /* 12V power supply */
|
||||
struct regulator *vpcie3v3; /* 3.3V power supply */
|
||||
struct regulator *vpcie1v8; /* 1.8V power supply */
|
||||
struct regulator *vpcie0v9; /* 0.9V power supply */
|
||||
struct gpio_desc *ep_gpio;
|
||||
u32 lanes;
|
||||
u8 lanes_map;
|
||||
u8 root_bus_nr;
|
||||
int link_gen;
|
||||
struct device *dev;
|
||||
struct irq_domain *irq_domain;
|
||||
int offset;
|
||||
struct pci_bus *root_bus;
|
||||
struct resource *io;
|
||||
phys_addr_t io_bus_addr;
|
||||
u32 io_size;
|
||||
void __iomem *msg_region;
|
||||
u32 mem_size;
|
||||
phys_addr_t msg_bus_addr;
|
||||
phys_addr_t mem_bus_addr;
|
||||
bool is_rc;
|
||||
struct resource *mem_res;
|
||||
};
|
||||
|
||||
static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
|
||||
{
|
||||
return readl(rockchip->apb_base + reg);
|
||||
}
|
||||
|
||||
static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
|
||||
u32 reg)
|
||||
{
|
||||
writel(val, rockchip->apb_base + reg);
|
||||
}
|
||||
|
||||
int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip);
|
||||
int rockchip_pcie_init_port(struct rockchip_pcie *rockchip);
|
||||
int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip);
|
||||
void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip);
|
||||
int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip);
|
||||
void rockchip_pcie_disable_clocks(void *data);
|
||||
void rockchip_pcie_cfg_configuration_accesses(
|
||||
struct rockchip_pcie *rockchip, u32 type);
|
||||
|
||||
#endif /* _PCIE_ROCKCHIP_H */
|
||||
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Reference in New Issue