mt76: mt7615: measure channel noise and report it via survey
Read measurements every 100 ms and build a simple moving average Signed-off-by: Felix Fietkau <nbd@nbd.name>
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@ -618,6 +618,9 @@ int mt76_get_survey(struct ieee80211_hw *hw, int idx,
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survey->channel = chan;
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survey->filled = SURVEY_INFO_TIME | SURVEY_INFO_TIME_BUSY;
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survey->filled |= dev->drv->survey_flags;
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if (state->noise)
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survey->filled |= SURVEY_INFO_NOISE_DBM;
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if (chan == phy->main_chan) {
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survey->filled |= SURVEY_INFO_IN_USE;
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@ -628,6 +631,7 @@ int mt76_get_survey(struct ieee80211_hw *hw, int idx,
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survey->time_busy = div_u64(state->cc_busy, 1000);
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survey->time_rx = div_u64(state->cc_rx, 1000);
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survey->time = div_u64(state->cc_active, 1000);
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survey->noise = state->noise;
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spin_lock_bh(&dev->cc_lock);
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survey->time_bss_rx = div_u64(state->cc_bss_rx, 1000);
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@ -328,6 +328,8 @@ struct mt76_channel_state {
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u64 cc_rx;
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u64 cc_bss_rx;
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u64 cc_tx;
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s8 noise;
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};
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struct mt76_sband {
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@ -1379,6 +1379,19 @@ out:
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mutex_unlock(&dev->mt76.mutex);
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}
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void mt7615_mac_enable_nf(struct mt7615_dev *dev, bool ext_phy)
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{
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u32 rxtd;
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if (ext_phy)
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rxtd = MT_WF_PHY_RXTD2(10);
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else
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rxtd = MT_WF_PHY_RXTD(12);
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mt76_set(dev, rxtd, BIT(18) | BIT(29));
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mt76_set(dev, MT_WF_PHY_R0_PHYMUX_5(ext_phy), 0x5 << 12);
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}
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void mt7615_mac_cca_stats_reset(struct mt7615_phy *phy)
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{
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struct mt7615_dev *dev = phy->dev;
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@ -1511,13 +1524,35 @@ mt7615_mac_scs_check(struct mt7615_phy *phy)
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mt7615_mac_set_default_sensitivity(phy);
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}
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static u8
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mt7615_phy_get_nf(struct mt7615_dev *dev, int idx)
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{
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static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 };
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u32 reg = idx ? MT_WF_PHY_RXTD2(17) : MT_WF_PHY_RXTD(20);
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u32 val, sum = 0, n = 0;
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int i;
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for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) {
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val = mt76_rr(dev, reg);
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sum += val * nf_power[i];
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n += val;
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}
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if (!n)
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return 0;
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return sum / n;
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}
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static void
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mt7615_phy_update_channel(struct mt76_phy *mphy, int idx)
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{
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struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76);
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struct mt7615_phy *phy = mphy->priv;
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struct mt76_channel_state *state;
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u64 busy_time, tx_time, rx_time, obss_time;
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u32 obss_reg = idx ? MT_WF_RMAC_MIB_TIME6 : MT_WF_RMAC_MIB_TIME5;
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int nf;
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busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx),
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MT_MIB_SDR9_BUSY_MASK);
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@ -1527,11 +1562,18 @@ mt7615_phy_update_channel(struct mt76_phy *mphy, int idx)
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MT_MIB_SDR37_RXTIME_MASK);
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obss_time = mt76_get_field(dev, obss_reg, MT_MIB_OBSSTIME_MASK);
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nf = mt7615_phy_get_nf(dev, idx);
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if (!phy->noise)
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phy->noise = nf << 4;
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else if (nf)
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phy->noise += nf - (phy->noise >> 4);
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state = mphy->chan_state;
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state->cc_busy += busy_time;
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state->cc_tx += tx_time;
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state->cc_rx += rx_time + obss_time;
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state->cc_bss_rx += rx_time;
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state->noise = -(phy->noise >> 4);
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}
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void mt7615_update_channel(struct mt76_dev *mdev)
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@ -40,11 +40,13 @@ static int mt7615_start(struct ieee80211_hw *hw)
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if (!running) {
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mt7615_mcu_ctrl_pm_state(dev, 0, 0);
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mt7615_mcu_set_mac_enable(dev, 0, true);
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mt7615_mac_enable_nf(dev, 0);
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}
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if (phy != &dev->phy) {
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mt7615_mcu_ctrl_pm_state(dev, 1, 0);
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mt7615_mcu_set_mac_enable(dev, 1, true);
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mt7615_mac_enable_nf(dev, 1);
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}
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set_bit(MT76_STATE_RUNNING, &phy->mt76->state);
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@ -238,6 +240,7 @@ static int mt7615_set_channel(struct mt7615_phy *phy)
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mt7615_mac_cca_stats_reset(phy);
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mt7615_mac_reset_counters(dev);
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phy->noise = 0;
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out:
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clear_bit(MT76_RESET, &phy->mt76->state);
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@ -94,6 +94,8 @@ struct mt7615_phy {
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u32 rxfilter;
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u32 omac_mask;
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u16 noise;
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unsigned long last_cca_adj;
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int false_cca_ofdm, false_cca_cck;
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s8 ofdm_sensitivity;
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@ -288,6 +290,7 @@ bool mt7615_mac_wtbl_update(struct mt7615_dev *dev, int idx, u32 mask);
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void mt7615_mac_reset_counters(struct mt7615_dev *dev);
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void mt7615_mac_cca_stats_reset(struct mt7615_phy *phy);
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void mt7615_mac_set_scs(struct mt7615_dev *dev, bool enable);
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void mt7615_mac_enable_nf(struct mt7615_dev *dev, bool ext_phy);
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void mt7615_mac_sta_poll(struct mt7615_dev *dev);
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int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi,
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struct sk_buff *skb, struct mt76_wcid *wcid,
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@ -104,6 +104,9 @@
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#define MT_WF_PHY_B1_PD_OFDM(v) ((v) << 16)
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#define MT_WF_PHY_B1_PD_BLK BIT(25)
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#define MT_WF_PHY_RXTD_BASE MT_WF_PHY(0x2200)
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#define MT_WF_PHY_RXTD(_n) (MT_WF_PHY_RXTD_BASE + ((_n) << 2))
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#define MT_WF_PHY_B0_RXTD_CCK_PD MT_WF_PHY(0x2310)
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#define MT_WF_PHY_B0_PD_CCK_MASK GENMASK(8, 1)
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#define MT_WF_PHY_B0_PD_CCK(v) ((v) << 1)
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@ -112,6 +115,9 @@
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#define MT_WF_PHY_B1_PD_CCK_MASK GENMASK(31, 24)
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#define MT_WF_PHY_B1_PD_CCK(v) ((v) << 24)
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#define MT_WF_PHY_RXTD2_BASE MT_WF_PHY(0x2a00)
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#define MT_WF_PHY_RXTD2(_n) (MT_WF_PHY_RXTD2_BASE + ((_n) << 2))
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#define MT_WF_CFG_BASE 0x20200
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#define MT_WF_CFG(ofs) (MT_WF_CFG_BASE + (ofs))
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