drm/i915/cnl: WaRsUseTimeoutMode
Apparently RC6 residency is lower than expected with EI mode for most of the cases on CNL A0, B0 and C0. This Wa doesn't solve our lower residency, but I believe it is better to have it since EI is not expected to work by HW engineers anyways. Cc: David Weinehall <david.weinehall@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: David Weinehall <david.weinehall@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170822235828.18322-1-rodrigo.vivi@intel.com
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@ -3077,6 +3077,7 @@ intel_info(const struct drm_i915_private *dev_priv)
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#define CNL_REVID_A0 0x0
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#define CNL_REVID_B0 0x1
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#define CNL_REVID_C0 0x2
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#define IS_CNL_REVID(p, since, until) \
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(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
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@ -6591,7 +6591,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
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{
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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uint32_t rc6_mask = 0;
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u32 rc6_mode, rc6_mask = 0;
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/* 1a: Software RC state - RC0 */
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I915_WRITE(GEN6_RC_STATE, 0);
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@ -6629,8 +6629,15 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
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rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
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DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
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I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
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/* WaRsUseTimeoutMode:cnl (pre-prod) */
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if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_C0))
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rc6_mode = GEN7_RC_CTL_TO_MODE;
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else
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rc6_mode = GEN6_RC_CTL_EI_MODE(1);
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I915_WRITE(GEN6_RC_CONTROL,
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GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) | rc6_mask);
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GEN6_RC_CTL_HW_ENABLE | rc6_mode | rc6_mask);
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/*
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* 3b: Enable Coarse Power Gating only when RC6 is enabled.
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