drm/amdgpu: update df_v3_6 for xgmi perfmons (v2)
add pmu attribute groups and structures for perf events. add sysfs to track available df perfmon counters fix overflow handling in perfmon counter reads. v2: squash in fix (Alex) Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jonathan Kim
Alex Deucher
parent
496091fa04
commit
e4cf4bf5b8
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@ -679,6 +679,7 @@ struct amdgpu_nbio_funcs {
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struct amdgpu_df_funcs {
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void (*init)(struct amdgpu_device *adev);
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void (*sw_init)(struct amdgpu_device *adev);
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void (*enable_broadcast_mode)(struct amdgpu_device *adev,
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bool enable);
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u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
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@ -729,6 +730,7 @@ struct amd_powerplay {
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};
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#define AMDGPU_RESET_MAGIC_NUM 64
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#define AMDGPU_MAX_DF_PERFMONS 4
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struct amdgpu_device {
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struct device *dev;
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struct drm_device *ddev;
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@ -959,6 +961,7 @@ struct amdgpu_device {
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long compute_timeout;
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uint64_t unique_id;
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uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
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};
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static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
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@ -1198,4 +1201,19 @@ static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return
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#endif
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#include "amdgpu_object.h"
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/* used by df_v3_6.c and amdgpu_pmu.c */
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#define AMDGPU_PMU_ATTR(_name, _object) \
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static ssize_t \
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_name##_show(struct device *dev, \
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struct device_attribute *attr, \
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char *page) \
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{ \
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BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \
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return sprintf(page, _object "\n"); \
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} \
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\
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static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
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#endif
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@ -30,8 +30,104 @@
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static u32 df_v3_6_channel_number[] = {1, 2, 0, 4, 0, 8, 0,
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16, 32, 0, 0, 0, 2, 4, 8};
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static void df_v3_6_init(struct amdgpu_device *adev)
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/* init df format attrs */
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AMDGPU_PMU_ATTR(event, "config:0-7");
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AMDGPU_PMU_ATTR(instance, "config:8-15");
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AMDGPU_PMU_ATTR(umask, "config:16-23");
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/* df format attributes */
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static struct attribute *df_v3_6_format_attrs[] = {
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&pmu_attr_event.attr,
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&pmu_attr_instance.attr,
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&pmu_attr_umask.attr,
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NULL
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};
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/* df format attribute group */
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static struct attribute_group df_v3_6_format_attr_group = {
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.name = "format",
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.attrs = df_v3_6_format_attrs,
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};
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/* df event attrs */
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AMDGPU_PMU_ATTR(cake0_pcsout_txdata,
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"event=0x7,instance=0x46,umask=0x2");
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AMDGPU_PMU_ATTR(cake1_pcsout_txdata,
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"event=0x7,instance=0x47,umask=0x2");
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AMDGPU_PMU_ATTR(cake0_pcsout_txmeta,
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"event=0x7,instance=0x46,umask=0x4");
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AMDGPU_PMU_ATTR(cake1_pcsout_txmeta,
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"event=0x7,instance=0x47,umask=0x4");
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AMDGPU_PMU_ATTR(cake0_ftiinstat_reqalloc,
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"event=0xb,instance=0x46,umask=0x4");
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AMDGPU_PMU_ATTR(cake1_ftiinstat_reqalloc,
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"event=0xb,instance=0x47,umask=0x4");
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AMDGPU_PMU_ATTR(cake0_ftiinstat_rspalloc,
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"event=0xb,instance=0x46,umask=0x8");
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AMDGPU_PMU_ATTR(cake1_ftiinstat_rspalloc,
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"event=0xb,instance=0x47,umask=0x8");
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/* df event attributes */
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static struct attribute *df_v3_6_event_attrs[] = {
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&pmu_attr_cake0_pcsout_txdata.attr,
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&pmu_attr_cake1_pcsout_txdata.attr,
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&pmu_attr_cake0_pcsout_txmeta.attr,
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&pmu_attr_cake1_pcsout_txmeta.attr,
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&pmu_attr_cake0_ftiinstat_reqalloc.attr,
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&pmu_attr_cake1_ftiinstat_reqalloc.attr,
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&pmu_attr_cake0_ftiinstat_rspalloc.attr,
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&pmu_attr_cake1_ftiinstat_rspalloc.attr,
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NULL
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};
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/* df event attribute group */
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static struct attribute_group df_v3_6_event_attr_group = {
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.name = "events",
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.attrs = df_v3_6_event_attrs
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};
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/* df event attr groups */
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const struct attribute_group *df_v3_6_attr_groups[] = {
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&df_v3_6_format_attr_group,
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&df_v3_6_event_attr_group,
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NULL
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};
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/* get the number of df counters available */
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static ssize_t df_v3_6_get_df_cntr_avail(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct amdgpu_device *adev;
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struct drm_device *ddev;
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int i, count;
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ddev = dev_get_drvdata(dev);
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adev = ddev->dev_private;
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count = 0;
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for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) {
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if (adev->df_perfmon_config_assign_mask[i] == 0)
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count++;
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}
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return snprintf(buf, PAGE_SIZE, "%i\n", count);
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}
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/* device attr for available perfmon counters */
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static DEVICE_ATTR(df_cntr_avail, S_IRUGO, df_v3_6_get_df_cntr_avail, NULL);
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/* init perfmons */
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static void df_v3_6_sw_init(struct amdgpu_device *adev)
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{
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int i, ret;
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ret = device_create_file(adev->dev, &dev_attr_df_cntr_avail);
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if (ret)
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DRM_ERROR("failed to create file for available df counters\n");
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for (i = 0; i < AMDGPU_MAX_DF_PERFMONS; i++)
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adev->df_perfmon_config_assign_mask[i] = 0;
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}
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static void df_v3_6_enable_broadcast_mode(struct amdgpu_device *adev,
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@ -105,28 +201,19 @@ static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev,
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*flags |= AMD_CG_SUPPORT_DF_MGCG;
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}
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/* hold counter assignment per gpu struct */
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struct df_v3_6_event_mask {
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struct amdgpu_device gpu;
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uint64_t config_assign_mask[AMDGPU_DF_MAX_COUNTERS];
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};
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/* get assigned df perfmon ctr as int */
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static void df_v3_6_pmc_config_2_cntr(struct amdgpu_device *adev,
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uint64_t config,
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int *counter)
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static int df_v3_6_pmc_config_2_cntr(struct amdgpu_device *adev,
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uint64_t config)
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{
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struct df_v3_6_event_mask *mask;
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int i;
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mask = container_of(adev, struct df_v3_6_event_mask, gpu);
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for (i = 0; i < AMDGPU_DF_MAX_COUNTERS; i++) {
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if ((config & 0x0FFFFFFUL) == mask->config_assign_mask[i]) {
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*counter = i;
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return;
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}
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for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) {
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if ((config & 0x0FFFFFFUL) ==
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adev->df_perfmon_config_assign_mask[i])
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return i;
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}
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return -EINVAL;
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}
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/* get address based on counter assignment */
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@ -136,10 +223,7 @@ static void df_v3_6_pmc_get_addr(struct amdgpu_device *adev,
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uint32_t *lo_base_addr,
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uint32_t *hi_base_addr)
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{
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int target_cntr = -1;
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df_v3_6_pmc_config_2_cntr(adev, config, &target_cntr);
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int target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);
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if (target_cntr < 0)
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return;
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@ -184,33 +268,29 @@ static int df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev,
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uint32_t *lo_val,
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uint32_t *hi_val)
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{
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uint32_t eventsel, instance, unitmask;
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uint32_t es_5_0, es_13_0, es_13_6, es_13_12, es_11_8, es_7_0;
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df_v3_6_pmc_get_addr(adev, config, 1, lo_base_addr, hi_base_addr);
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if (lo_val == NULL || hi_val == NULL)
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return -EINVAL;
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if ((*lo_base_addr == 0) || (*hi_base_addr == 0)) {
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DRM_ERROR("DF PMC addressing not retrieved! Lo: %x, Hi: %x",
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DRM_ERROR("[DF PMC] addressing not retrieved! Lo: %x, Hi: %x",
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*lo_base_addr, *hi_base_addr);
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return -ENXIO;
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}
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eventsel = GET_EVENT(config);
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instance = GET_INSTANCE(config);
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unitmask = GET_UNITMASK(config);
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if (lo_val && hi_val) {
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uint32_t eventsel, instance, unitmask;
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uint32_t instance_10, instance_5432, instance_76;
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es_5_0 = eventsel & 0x3FUL;
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es_13_6 = instance;
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es_13_0 = (es_13_6 << 6) + es_5_0;
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es_13_12 = (es_13_0 & 0x03000UL) >> 12;
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es_11_8 = (es_13_0 & 0x0F00UL) >> 8;
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es_7_0 = es_13_0 & 0x0FFUL;
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*lo_val = (es_7_0 & 0xFFUL) | ((unitmask & 0x0FUL) << 8);
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*hi_val = (es_11_8 | ((es_13_12)<<(29)));
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eventsel = DF_V3_6_GET_EVENT(config) & 0x3f;
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unitmask = DF_V3_6_GET_UNITMASK(config) & 0xf;
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instance = DF_V3_6_GET_INSTANCE(config);
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instance_10 = instance & 0x3;
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instance_5432 = (instance >> 2) & 0xf;
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instance_76 = (instance >> 6) & 0x3;
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*lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel;
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*hi_val = (instance_76 << 29) | instance_5432;
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}
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return 0;
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}
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@ -220,26 +300,21 @@ static int df_v3_6_pmc_assign_cntr(struct amdgpu_device *adev,
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uint64_t config,
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int *is_assigned)
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{
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struct df_v3_6_event_mask *mask;
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int i, target_cntr;
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target_cntr = -1;
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*is_assigned = 0;
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df_v3_6_pmc_config_2_cntr(adev, config, &target_cntr);
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target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);
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if (target_cntr >= 0) {
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*is_assigned = 1;
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return 0;
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}
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mask = container_of(adev, struct df_v3_6_event_mask, gpu);
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for (i = 0; i < AMDGPU_DF_MAX_COUNTERS; i++) {
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if (mask->config_assign_mask[i] == 0ULL) {
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mask->config_assign_mask[i] = config & 0x0FFFFFFUL;
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for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) {
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if (adev->df_perfmon_config_assign_mask[i] == 0U) {
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adev->df_perfmon_config_assign_mask[i] =
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config & 0x0FFFFFFUL;
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return 0;
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}
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}
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@ -251,66 +326,17 @@ static int df_v3_6_pmc_assign_cntr(struct amdgpu_device *adev,
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static void df_v3_6_pmc_release_cntr(struct amdgpu_device *adev,
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uint64_t config)
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{
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struct df_v3_6_event_mask *mask;
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int target_cntr;
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target_cntr = -1;
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df_v3_6_pmc_config_2_cntr(adev, config, &target_cntr);
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mask = container_of(adev, struct df_v3_6_event_mask, gpu);
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int target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);
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if (target_cntr >= 0)
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mask->config_assign_mask[target_cntr] = 0ULL;
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adev->df_perfmon_config_assign_mask[target_cntr] = 0ULL;
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}
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/*
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* get xgmi link counters via programmable data fabric (df) counters (max 4)
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* using cake tx event.
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*
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* @adev -> amdgpu device
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* @instance-> currently cake has 2 links to poll on vega20
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* @count -> counters to pass
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*
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*/
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static void df_v3_6_get_xgmi_link_cntr(struct amdgpu_device *adev,
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int instance,
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uint64_t *count)
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{
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uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
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uint64_t config;
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config = GET_INSTANCE_CONFIG(instance);
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df_v3_6_pmc_get_read_settings(adev, config, &lo_base_addr,
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&hi_base_addr);
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if ((lo_base_addr == 0) || (hi_base_addr == 0))
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return;
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lo_val = RREG32_PCIE(lo_base_addr);
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hi_val = RREG32_PCIE(hi_base_addr);
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*count = ((hi_val | 0ULL) << 32) | (lo_val | 0ULL);
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}
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/*
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* reset xgmi link counters
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*
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* @adev -> amdgpu device
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* @instance-> currently cake has 2 links to poll on vega20
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*
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*/
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static void df_v3_6_reset_xgmi_link_cntr(struct amdgpu_device *adev,
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int instance)
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static void df_v3_6_reset_perfmon_cntr(struct amdgpu_device *adev,
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uint64_t config)
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{
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uint32_t lo_base_addr, hi_base_addr;
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uint64_t config;
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config = 0ULL | (0x7ULL) | ((0x46ULL + instance) << 8) | (0x2 << 16);
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df_v3_6_pmc_get_read_settings(adev, config, &lo_base_addr,
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&hi_base_addr);
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@ -322,26 +348,13 @@ static void df_v3_6_reset_xgmi_link_cntr(struct amdgpu_device *adev,
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WREG32_PCIE(hi_base_addr, 0UL);
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}
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/*
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* add xgmi link counters
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*
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* @adev -> amdgpu device
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* @instance-> currently cake has 2 links to poll on vega20
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*
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*/
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static int df_v3_6_add_xgmi_link_cntr(struct amdgpu_device *adev,
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int instance)
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static int df_v3_6_add_perfmon_cntr(struct amdgpu_device *adev,
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uint64_t config)
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{
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uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
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uint64_t config;
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int ret, is_assigned;
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if (instance < 0 || instance > 1)
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return -EINVAL;
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config = GET_INSTANCE_CONFIG(instance);
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ret = df_v3_6_pmc_assign_cntr(adev, config, &is_assigned);
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if (ret || is_assigned)
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@ -357,125 +370,47 @@ static int df_v3_6_add_xgmi_link_cntr(struct amdgpu_device *adev,
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if (ret)
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return ret;
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DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
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config, lo_base_addr, hi_base_addr, lo_val, hi_val);
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WREG32_PCIE(lo_base_addr, lo_val);
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WREG32_PCIE(hi_base_addr, hi_val);
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return ret;
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}
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/*
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* start xgmi link counters
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*
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* @adev -> amdgpu device
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* @instance-> currently cake has 2 links to poll on vega20
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* @is_enable -> either resume or assign event via df perfmon
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*
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*/
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static int df_v3_6_start_xgmi_link_cntr(struct amdgpu_device *adev,
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int instance,
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int is_enable)
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{
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uint32_t lo_base_addr, hi_base_addr, lo_val;
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uint64_t config;
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int ret;
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if (instance < 0 || instance > 1)
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return -EINVAL;
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if (is_enable) {
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ret = df_v3_6_add_xgmi_link_cntr(adev, instance);
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if (ret)
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return ret;
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|
||||
} else {
|
||||
|
||||
config = GET_INSTANCE_CONFIG(instance);
|
||||
|
||||
df_v3_6_pmc_get_ctrl_settings(adev,
|
||||
config,
|
||||
&lo_base_addr,
|
||||
&hi_base_addr,
|
||||
NULL,
|
||||
NULL);
|
||||
|
||||
if (lo_base_addr == 0)
|
||||
return -EINVAL;
|
||||
|
||||
lo_val = RREG32_PCIE(lo_base_addr);
|
||||
|
||||
WREG32_PCIE(lo_base_addr, lo_val | (1ULL << 22));
|
||||
|
||||
ret = 0;
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* start xgmi link counters
|
||||
*
|
||||
* @adev -> amdgpu device
|
||||
* @instance-> currently cake has 2 links to poll on vega20
|
||||
* @is_enable -> either pause or unassign event via df perfmon
|
||||
*
|
||||
*/
|
||||
|
||||
static int df_v3_6_stop_xgmi_link_cntr(struct amdgpu_device *adev,
|
||||
int instance,
|
||||
int is_disable)
|
||||
{
|
||||
|
||||
uint32_t lo_base_addr, hi_base_addr, lo_val;
|
||||
uint64_t config;
|
||||
|
||||
config = GET_INSTANCE_CONFIG(instance);
|
||||
|
||||
if (is_disable) {
|
||||
df_v3_6_reset_xgmi_link_cntr(adev, instance);
|
||||
df_v3_6_pmc_release_cntr(adev, config);
|
||||
} else {
|
||||
|
||||
df_v3_6_pmc_get_ctrl_settings(adev,
|
||||
config,
|
||||
&lo_base_addr,
|
||||
&hi_base_addr,
|
||||
NULL,
|
||||
NULL);
|
||||
|
||||
if ((lo_base_addr == 0) || (hi_base_addr == 0))
|
||||
return -EINVAL;
|
||||
|
||||
lo_val = RREG32_PCIE(lo_base_addr);
|
||||
|
||||
WREG32_PCIE(lo_base_addr, lo_val & ~(1ULL << 22));
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
|
||||
int is_enable)
|
||||
{
|
||||
int xgmi_tx_link, ret = 0;
|
||||
uint32_t lo_base_addr, hi_base_addr, lo_val;
|
||||
int ret = 0;
|
||||
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_VEGA20:
|
||||
xgmi_tx_link = IS_DF_XGMI_0_TX(config) ? 0
|
||||
: (IS_DF_XGMI_1_TX(config) ? 1 : -1);
|
||||
|
||||
if (xgmi_tx_link >= 0)
|
||||
ret = df_v3_6_start_xgmi_link_cntr(adev, xgmi_tx_link,
|
||||
is_enable);
|
||||
df_v3_6_reset_perfmon_cntr(adev, config);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
if (is_enable) {
|
||||
ret = df_v3_6_add_perfmon_cntr(adev, config);
|
||||
} else {
|
||||
ret = df_v3_6_pmc_get_ctrl_settings(adev,
|
||||
config,
|
||||
&lo_base_addr,
|
||||
&hi_base_addr,
|
||||
NULL,
|
||||
NULL);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
lo_val = RREG32_PCIE(lo_base_addr);
|
||||
|
||||
DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x",
|
||||
config, lo_base_addr, hi_base_addr, lo_val);
|
||||
|
||||
WREG32_PCIE(lo_base_addr, lo_val | (1ULL << 22));
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
|
@ -487,23 +422,32 @@ static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
|
|||
static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config,
|
||||
int is_disable)
|
||||
{
|
||||
int xgmi_tx_link, ret = 0;
|
||||
uint32_t lo_base_addr, hi_base_addr, lo_val;
|
||||
int ret = 0;
|
||||
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_VEGA20:
|
||||
xgmi_tx_link = IS_DF_XGMI_0_TX(config) ? 0
|
||||
: (IS_DF_XGMI_1_TX(config) ? 1 : -1);
|
||||
ret = df_v3_6_pmc_get_ctrl_settings(adev,
|
||||
config,
|
||||
&lo_base_addr,
|
||||
&hi_base_addr,
|
||||
NULL,
|
||||
NULL);
|
||||
|
||||
if (xgmi_tx_link >= 0) {
|
||||
ret = df_v3_6_stop_xgmi_link_cntr(adev,
|
||||
xgmi_tx_link,
|
||||
is_disable);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = 0;
|
||||
break;
|
||||
lo_val = RREG32_PCIE(lo_base_addr);
|
||||
|
||||
DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x",
|
||||
config, lo_base_addr, hi_base_addr, lo_val);
|
||||
|
||||
WREG32_PCIE(lo_base_addr, lo_val & ~(1ULL << 22));
|
||||
|
||||
if (is_disable)
|
||||
df_v3_6_pmc_release_cntr(adev, config);
|
||||
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
@ -515,28 +459,38 @@ static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
|
|||
uint64_t config,
|
||||
uint64_t *count)
|
||||
{
|
||||
|
||||
int xgmi_tx_link;
|
||||
uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
|
||||
*count = 0;
|
||||
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_VEGA20:
|
||||
xgmi_tx_link = IS_DF_XGMI_0_TX(config) ? 0
|
||||
: (IS_DF_XGMI_1_TX(config) ? 1 : -1);
|
||||
|
||||
if (xgmi_tx_link >= 0) {
|
||||
df_v3_6_reset_xgmi_link_cntr(adev, xgmi_tx_link);
|
||||
df_v3_6_get_xgmi_link_cntr(adev, xgmi_tx_link, count);
|
||||
}
|
||||
df_v3_6_pmc_get_read_settings(adev, config, &lo_base_addr,
|
||||
&hi_base_addr);
|
||||
|
||||
if ((lo_base_addr == 0) || (hi_base_addr == 0))
|
||||
return;
|
||||
|
||||
lo_val = RREG32_PCIE(lo_base_addr);
|
||||
hi_val = RREG32_PCIE(hi_base_addr);
|
||||
|
||||
*count = ((hi_val | 0ULL) << 32) | (lo_val | 0ULL);
|
||||
|
||||
if (*count >= DF_V3_6_PERFMON_OVERFLOW)
|
||||
*count = 0;
|
||||
|
||||
DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
|
||||
config, lo_base_addr, hi_base_addr, lo_val, hi_val);
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
const struct amdgpu_df_funcs df_v3_6_funcs = {
|
||||
.init = df_v3_6_init,
|
||||
.sw_init = df_v3_6_sw_init,
|
||||
.enable_broadcast_mode = df_v3_6_enable_broadcast_mode,
|
||||
.get_fb_channel_number = df_v3_6_get_fb_channel_number,
|
||||
.get_hbm_channel_number = df_v3_6_get_hbm_channel_number,
|
||||
|
|
|
|||
|
|
@ -36,22 +36,15 @@ enum DF_V3_6_MGCG {
|
|||
};
|
||||
|
||||
/* Defined in global_features.h as FTI_PERFMON_VISIBLE */
|
||||
#define AMDGPU_DF_MAX_COUNTERS 4
|
||||
#define DF_V3_6_MAX_COUNTERS 4
|
||||
|
||||
/* get flags from df perfmon config */
|
||||
#define GET_EVENT(x) (x & 0xFFUL)
|
||||
#define GET_INSTANCE(x) ((x >> 8) & 0xFFUL)
|
||||
#define GET_UNITMASK(x) ((x >> 16) & 0xFFUL)
|
||||
#define GET_INSTANCE_CONFIG(x) (0ULL | (0x07ULL) \
|
||||
| ((0x046ULL + x) << 8) \
|
||||
| (0x02 << 16))
|
||||
|
||||
/* df event conf macros */
|
||||
#define IS_DF_XGMI_0_TX(x) (GET_EVENT(x) == 0x7 \
|
||||
&& GET_INSTANCE(x) == 0x46 && GET_UNITMASK(x) == 0x2)
|
||||
#define IS_DF_XGMI_1_TX(x) (GET_EVENT(x) == 0x7 \
|
||||
&& GET_INSTANCE(x) == 0x47 && GET_UNITMASK(x) == 0x2)
|
||||
#define DF_V3_6_GET_EVENT(x) (x & 0xFFUL)
|
||||
#define DF_V3_6_GET_INSTANCE(x) ((x >> 8) & 0xFFUL)
|
||||
#define DF_V3_6_GET_UNITMASK(x) ((x >> 16) & 0xFFUL)
|
||||
#define DF_V3_6_PERFMON_OVERFLOW 0xFFFFFFFFFFFFULL
|
||||
|
||||
extern const struct attribute_group *df_v3_6_attr_groups[];
|
||||
extern const struct amdgpu_df_funcs df_v3_6_funcs;
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1034,6 +1034,8 @@ static int soc15_common_sw_init(void *handle)
|
|||
if (amdgpu_sriov_vf(adev))
|
||||
xgpu_ai_mailbox_add_irq_id(adev);
|
||||
|
||||
adev->df_funcs->sw_init(adev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1080,6 +1082,7 @@ static int soc15_common_hw_init(void *handle)
|
|||
*/
|
||||
if (adev->nbio_funcs->remap_hdp_registers)
|
||||
adev->nbio_funcs->remap_hdp_registers(adev);
|
||||
|
||||
/* enable the doorbell aperture */
|
||||
soc15_enable_doorbell_aperture(adev, true);
|
||||
/* HW doorbell routing policy: doorbell writing not
|
||||
|
|
|
|||
Loading…
Reference in New Issue