powerpc/64s: Leave interrupts hard enabled in context switch for radix
Commit 4387e9ff25 ("[POWERPC] Fix PMU + soft interrupt disable bug") hard disabled interrupts over the low level context switch, because the SLB management can't cope with a PMU interrupt accesing the stack in that window. Radix based kernel mapping does not use the SLB so it does not require interrupts hard disabled here. This is worth 1-2% in context switch performance on POWER9. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -607,6 +607,14 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
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top of the kernel stack. */
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addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
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/*
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* PMU interrupts in radix may come in here. They will use r1, not
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* PACAKSAVE, so this stack switch will not cause a problem. They
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* will store to the process stack, which may then be migrated to
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* another CPU. However the rq lock release on this CPU paired with
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* the rq lock acquire on the new CPU before the stack becomes
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* active on the new CPU, will order those stores.
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*/
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mr r1,r8 /* start using new stack pointer */
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std r7,PACAKSAVE(r13)
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@ -1199,12 +1199,14 @@ struct task_struct *__switch_to(struct task_struct *prev,
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__switch_to_tm(prev, new);
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/*
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* We can't take a PMU exception inside _switch() since there is a
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* window where the kernel stack SLB and the kernel stack are out
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* of sync. Hard disable here.
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*/
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hard_irq_disable();
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if (!radix_enabled()) {
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/*
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* We can't take a PMU exception inside _switch() since there
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* is a window where the kernel stack SLB and the kernel stack
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* are out of sync. Hard disable here.
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*/
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hard_irq_disable();
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}
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/*
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* Call restore_sprs() before calling _switch(). If we move it after
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