arm64: tegra: Device tree changes for v4.13-rc1
This adds the CCPLEX cluster on Tegra186, which is used to initiate CPU frequency and voltage transitions. Also included is a bit of cleanup for PCI related device tree content, in preparation for a future DTC release that has additional checks for the PCI bus. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAllDkc0THHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoVAtEACNPwpKvx7jTNmP8Z2nGARRU/7X5PjK BXRd3C4IgCgOmUHrUQCOvxPVdtYqc/lyW7Bs8v3jo3o5eOG+glXoZ/QRRlwKmBnV hJrxT4qfgC0MwdXdukbxQ44wP4ehQdZBTxhyBuRHj0JpW6/cJ8DKfe6hNYhexzR0 sUXiRzf6VskehZHVeowkqNNoltoEsIzwshIwWKh1Z6gZydPHTmop3jd+v/iWFBj6 jDkF1FZv80I+MulChz5enGEKq1b5E9E0IU9zd8jnelqRAqCDy+xw7x1sGg6KM2st z3lL17msDPV73KBWfyPJ20vIodFfY9WUlQ4E3DzHHTkdUUMBzQ7C804c4HPf/8KE rF9/0Kr+JFOuzo8znHtvz8WQiimK3X8BH7MwhuFNlfzniu3PPqBeFmf/mZcxl1Cx xf17l43tTM14e7+8rjVMmuIfqCnrIbW0bmr74YgU20VOvdQ1T0VUBQCFDG3bU+zT t4ljt7G8/i4SoWf1eVUtv7PW/miwEb8qnjx7yfHS7Qzfjhr+z3OxorqIdc1A0n4l rxVBkpjRpcRyXicmF8j+aT3cU5inVQ0UnvKbkiFmsia3hIPKlAnLJXFQLvTRizKa 1BXa0HH4QvQxnmLzVGx9aOcndI1XoCMmNQMAdFeC4XXD7IDJ8CXke9hVU875cj6V YWX4IqtXljIDgg== =nFWX -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.13-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64 arm64: tegra: Device tree changes for v4.13-rc1 This adds the CCPLEX cluster on Tegra186, which is used to initiate CPU frequency and voltage transitions. Also included is a bit of cleanup for PCI related device tree content, in preparation for a future DTC release that has additional checks for the PCI bus. * tag 'tegra-for-4.13-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: dts: nvidia: fix PCI bus dtc warnings arm64: tegra: Add CCPLEX_CLUSTER area in Tegra186 Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
e4b79c3b6b
|
@ -12,7 +12,7 @@
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
|
|
||||||
pcie-controller@01003000 {
|
pcie@1003000 {
|
||||||
compatible = "nvidia,tegra124-pcie";
|
compatible = "nvidia,tegra124-pcie";
|
||||||
device_type = "pci";
|
device_type = "pci";
|
||||||
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
|
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
|
||||||
|
@ -55,6 +55,7 @@
|
||||||
device_type = "pci";
|
device_type = "pci";
|
||||||
assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
|
assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
|
||||||
reg = <0x000800 0 0 0 0>;
|
reg = <0x000800 0 0 0 0>;
|
||||||
|
bus-range = <0x00 0xff>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
||||||
#address-cells = <3>;
|
#address-cells = <3>;
|
||||||
|
@ -68,6 +69,7 @@
|
||||||
device_type = "pci";
|
device_type = "pci";
|
||||||
assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
|
assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
|
||||||
reg = <0x001000 0 0 0 0>;
|
reg = <0x001000 0 0 0 0>;
|
||||||
|
bus-range = <0x00 0xff>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
||||||
#address-cells = <3>;
|
#address-cells = <3>;
|
||||||
|
|
|
@ -348,6 +348,13 @@
|
||||||
reg-names = "pmc", "wake", "aotag", "scratch";
|
reg-names = "pmc", "wake", "aotag", "scratch";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
ccplex@e000000 {
|
||||||
|
compatible = "nvidia,tegra186-ccplex-cluster";
|
||||||
|
reg = <0x0 0x0e000000 0x0 0x3fffff>;
|
||||||
|
|
||||||
|
nvidia,bpmp = <&bpmp>;
|
||||||
|
};
|
||||||
|
|
||||||
gpu@17000000 {
|
gpu@17000000 {
|
||||||
compatible = "nvidia,gp10b";
|
compatible = "nvidia,gp10b";
|
||||||
reg = <0x0 0x17000000 0x0 0x1000000>,
|
reg = <0x0 0x17000000 0x0 0x1000000>,
|
||||||
|
|
|
@ -7,7 +7,7 @@
|
||||||
model = "NVIDIA Jetson TX1 Developer Kit";
|
model = "NVIDIA Jetson TX1 Developer Kit";
|
||||||
compatible = "nvidia,p2371-2180", "nvidia,tegra210";
|
compatible = "nvidia,p2371-2180", "nvidia,tegra210";
|
||||||
|
|
||||||
pcie-controller@01003000 {
|
pcie@1003000 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
||||||
avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
|
avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
|
||||||
|
|
|
@ -11,7 +11,7 @@
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
|
|
||||||
pcie-controller@01003000 {
|
pcie@1003000 {
|
||||||
compatible = "nvidia,tegra210-pcie";
|
compatible = "nvidia,tegra210-pcie";
|
||||||
device_type = "pci";
|
device_type = "pci";
|
||||||
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
|
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
|
||||||
|
@ -51,6 +51,7 @@
|
||||||
device_type = "pci";
|
device_type = "pci";
|
||||||
assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
|
assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
|
||||||
reg = <0x000800 0 0 0 0>;
|
reg = <0x000800 0 0 0 0>;
|
||||||
|
bus-range = <0x00 0xff>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
||||||
#address-cells = <3>;
|
#address-cells = <3>;
|
||||||
|
@ -64,6 +65,7 @@
|
||||||
device_type = "pci";
|
device_type = "pci";
|
||||||
assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
|
assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
|
||||||
reg = <0x001000 0 0 0 0>;
|
reg = <0x001000 0 0 0 0>;
|
||||||
|
bus-range = <0x00 0xff>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
||||||
#address-cells = <3>;
|
#address-cells = <3>;
|
||||||
|
|
Loading…
Reference in New Issue