UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

iio: adc: exynos_adc: Add exynos_adc_data structure to improve readability 

This patchset add 'exynos_adc_data' structure which includes some functions
to control ADC operation and specific data according to ADC version (v1 or v2).

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
This commit is contained in:
Chanwoo Choi 2014-07-22 03:04:00 +01:00 committed by Jonathan Cameron
parent d3f1621960
commit e49d99e0ec
1 changed files with 150 additions and 82 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

212
drivers/iio/adc/exynos_adc.c
View File

@ -39,11 +39,6 @@
#include <linux/iio/machine.h> #include <linux/iio/machine.h>
#include <linux/iio/driver.h> #include <linux/iio/driver.h>
enum adc_version {
ADC_V1,
ADC_V2
};
/* EXYNOS4412/5250 ADC_V1 registers definitions */ /* EXYNOS4412/5250 ADC_V1 registers definitions */
#define ADC_V1_CON(x) ((x) + 0x00) #define ADC_V1_CON(x) ((x) + 0x00)
#define ADC_V1_DLY(x) ((x) + 0x08) #define ADC_V1_DLY(x) ((x) + 0x08)
@ -85,6 +80,7 @@ enum adc_version {
#define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100)) #define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100))
struct exynos_adc { struct exynos_adc {
struct exynos_adc_data *data;
void __iomem *regs; void __iomem *regs;
void __iomem *enable_reg; void __iomem *enable_reg;
struct clk *clk; struct clk *clk;
@ -97,26 +93,71 @@ struct exynos_adc {
unsigned int version; unsigned int version;
}; };
static const struct of_device_id exynos_adc_match[] = { struct exynos_adc_data {
{ .compatible = "samsung,exynos-adc-v1", .data = (void *)ADC_V1 }, int num_channels;
{ .compatible = "samsung,exynos-adc-v2", .data = (void *)ADC_V2 },
{}, void (*init_hw)(struct exynos_adc *info);
void (*exit_hw)(struct exynos_adc *info);
void (*clear_irq)(struct exynos_adc *info);
void (*start_conv)(struct exynos_adc *info, unsigned long addr);
}; };
MODULE_DEVICE_TABLE(of, exynos_adc_match);
static inline unsigned int exynos_adc_get_version(struct platform_device *pdev) static void exynos_adc_v1_init_hw(struct exynos_adc *info)
{ {
const struct of_device_id *match; u32 con1;
match = of_match_node(exynos_adc_match, pdev->dev.of_node); writel(1, info->enable_reg);
return (unsigned int)match->data;
/* set default prescaler values and Enable prescaler */
con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
/* Enable 12-bit ADC resolution */
con1 |= ADC_V1_CON_RES;
writel(con1, ADC_V1_CON(info->regs));
} }
static void exynos_adc_hw_init(struct exynos_adc *info) static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
{
u32 con;
writel(0, info->enable_reg);
con = readl(ADC_V1_CON(info->regs));
con |= ADC_V1_CON_STANDBY;
writel(con, ADC_V1_CON(info->regs));
}
static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
{
writel(1, ADC_V1_INTCLR(info->regs));
}
static void exynos_adc_v1_start_conv(struct exynos_adc *info,
unsigned long addr)
{
u32 con1;
writel(addr, ADC_V1_MUX(info->regs));
con1 = readl(ADC_V1_CON(info->regs));
writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
}
static const struct exynos_adc_data exynos_adc_v1_data = {
.num_channels = MAX_ADC_V1_CHANNELS,
.init_hw = exynos_adc_v1_init_hw,
.exit_hw = exynos_adc_v1_exit_hw,
.clear_irq = exynos_adc_v1_clear_irq,
.start_conv = exynos_adc_v1_start_conv,
};
static void exynos_adc_v2_init_hw(struct exynos_adc *info)
{ {
u32 con1, con2; u32 con1, con2;
if (info->version == ADC_V2) { writel(1, info->enable_reg);
con1 = ADC_V2_CON1_SOFT_RESET; con1 = ADC_V2_CON1_SOFT_RESET;
writel(con1, ADC_V2_CON1(info->regs)); writel(con1, ADC_V2_CON1(info->regs));
@ -126,14 +167,65 @@ static void exynos_adc_hw_init(struct exynos_adc *info)
/* Enable interrupts */ /* Enable interrupts */
writel(1, ADC_V2_INT_EN(info->regs)); writel(1, ADC_V2_INT_EN(info->regs));
} else {
/* set default prescaler values and Enable prescaler */
con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
/* Enable 12-bit ADC resolution */
con1 |= ADC_V1_CON_RES;
writel(con1, ADC_V1_CON(info->regs));
} }
static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
{
u32 con;
writel(0, info->enable_reg);
con = readl(ADC_V2_CON1(info->regs));
con &= ~ADC_CON_EN_START;
writel(con, ADC_V2_CON1(info->regs));
}
static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
{
writel(1, ADC_V2_INT_ST(info->regs));
}
static void exynos_adc_v2_start_conv(struct exynos_adc *info,
unsigned long addr)
{
u32 con1, con2;
con2 = readl(ADC_V2_CON2(info->regs));
con2 &= ~ADC_V2_CON2_ACH_MASK;
con2 |= ADC_V2_CON2_ACH_SEL(addr);
writel(con2, ADC_V2_CON2(info->regs));
con1 = readl(ADC_V2_CON1(info->regs));
writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs));
}
static const struct exynos_adc_data exynos_adc_v2_data = {
.num_channels = MAX_ADC_V2_CHANNELS,
.init_hw = exynos_adc_v2_init_hw,
.exit_hw = exynos_adc_v2_exit_hw,
.clear_irq = exynos_adc_v2_clear_irq,
.start_conv = exynos_adc_v2_start_conv,
};
static const struct of_device_id exynos_adc_match[] = {
{
.compatible = "samsung,exynos-adc-v1",
.data = &exynos_adc_v1_data,
}, {
.compatible = "samsung,exynos-adc-v2",
.data = &exynos_adc_v2_data,
},
{},
};
MODULE_DEVICE_TABLE(of, exynos_adc_match);
static struct exynos_adc_data *exynos_adc_get_data(struct platform_device *pdev)
{
const struct of_device_id *match;
match = of_match_node(exynos_adc_match, pdev->dev.of_node);
return (struct exynos_adc_data *)match->data;
} }
static int exynos_read_raw(struct iio_dev *indio_dev, static int exynos_read_raw(struct iio_dev *indio_dev,
@ -144,7 +236,6 @@ static int exynos_read_raw(struct iio_dev *indio_dev,
{ {
struct exynos_adc *info = iio_priv(indio_dev); struct exynos_adc *info = iio_priv(indio_dev);
unsigned long timeout; unsigned long timeout;
u32 con1, con2;
int ret; int ret;
if (mask != IIO_CHAN_INFO_RAW) if (mask != IIO_CHAN_INFO_RAW)
@ -154,28 +245,15 @@ static int exynos_read_raw(struct iio_dev *indio_dev,
reinit_completion(&info->completion); reinit_completion(&info->completion);
/* Select the channel to be used and Trigger conversion */ /* Select the channel to be used and Trigger conversion */
if (info->version == ADC_V2) { if (info->data->start_conv)
con2 = readl(ADC_V2_CON2(info->regs)); info->data->start_conv(info, chan->address);
con2 &= ~ADC_V2_CON2_ACH_MASK;
con2 |= ADC_V2_CON2_ACH_SEL(chan->address);
writel(con2, ADC_V2_CON2(info->regs));
con1 = readl(ADC_V2_CON1(info->regs));
writel(con1 | ADC_CON_EN_START,
ADC_V2_CON1(info->regs));
} else {
writel(chan->address, ADC_V1_MUX(info->regs));
con1 = readl(ADC_V1_CON(info->regs));
writel(con1 | ADC_CON_EN_START,
ADC_V1_CON(info->regs));
}
timeout = wait_for_completion_timeout timeout = wait_for_completion_timeout
(&info->completion, EXYNOS_ADC_TIMEOUT); (&info->completion, EXYNOS_ADC_TIMEOUT);
if (timeout == 0) { if (timeout == 0) {
dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n"); dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n");
exynos_adc_hw_init(info); if (info->data->init_hw)
info->data->init_hw(info);
ret = -ETIMEDOUT; ret = -ETIMEDOUT;
} else { } else {
*val = info->value; *val = info->value;
@ -193,13 +271,11 @@ static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
struct exynos_adc *info = (struct exynos_adc *)dev_id; struct exynos_adc *info = (struct exynos_adc *)dev_id;
/* Read value */ /* Read value */
info->value = readl(ADC_V1_DATX(info->regs)) & info->value = readl(ADC_V1_DATX(info->regs)) & ADC_DATX_MASK;
ADC_DATX_MASK;
/* clear irq */ /* clear irq */
if (info->version == ADC_V2) if (info->data->clear_irq)
writel(1, ADC_V2_INT_ST(info->regs)); info->data->clear_irq(info);
else
writel(1, ADC_V1_INTCLR(info->regs));
complete(&info->completion); complete(&info->completion);
@ -277,6 +353,12 @@ static int exynos_adc_probe(struct platform_device *pdev)
info = iio_priv(indio_dev); info = iio_priv(indio_dev);
info->data = exynos_adc_get_data(pdev);
if (!info->data) {
dev_err(&pdev->dev, "failed getting exynos_adc_data\n");
return -EINVAL;
}
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
info->regs = devm_ioremap_resource(&pdev->dev, mem); info->regs = devm_ioremap_resource(&pdev->dev, mem);
if (IS_ERR(info->regs)) if (IS_ERR(info->regs))
@ -319,10 +401,6 @@ static int exynos_adc_probe(struct platform_device *pdev)
if (ret) if (ret)
goto err_disable_reg; goto err_disable_reg;
writel(1, info->enable_reg);
info->version = exynos_adc_get_version(pdev);
platform_set_drvdata(pdev, indio_dev); platform_set_drvdata(pdev, indio_dev);
indio_dev->name = dev_name(&pdev->dev); indio_dev->name = dev_name(&pdev->dev);
@ -331,11 +409,7 @@ static int exynos_adc_probe(struct platform_device *pdev)
indio_dev->info = &exynos_adc_iio_info; indio_dev->info = &exynos_adc_iio_info;
indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = exynos_adc_iio_channels; indio_dev->channels = exynos_adc_iio_channels;
indio_dev->num_channels = info->data->num_channels;
if (info->version == ADC_V1)
indio_dev->num_channels = MAX_ADC_V1_CHANNELS;
else
indio_dev->num_channels = MAX_ADC_V2_CHANNELS;
ret = request_irq(info->irq, exynos_adc_isr, ret = request_irq(info->irq, exynos_adc_isr,
0, dev_name(&pdev->dev), info); 0, dev_name(&pdev->dev), info);
@ -349,7 +423,8 @@ static int exynos_adc_probe(struct platform_device *pdev)
if (ret) if (ret)
goto err_irq; goto err_irq;
exynos_adc_hw_init(info); if (info->data->init_hw)
info->data->init_hw(info);
ret = of_platform_populate(np, exynos_adc_match, NULL, &indio_dev->dev); ret = of_platform_populate(np, exynos_adc_match, NULL, &indio_dev->dev);
if (ret < 0) { if (ret < 0) {
@ -366,7 +441,8 @@ err_of_populate:
err_irq: err_irq:
free_irq(info->irq, info); free_irq(info->irq, info);
err_disable_clk: err_disable_clk:
writel(0, info->enable_reg); if (info->data->exit_hw)
info->data->exit_hw(info);
clk_disable_unprepare(info->clk); clk_disable_unprepare(info->clk);
err_disable_reg: err_disable_reg:
regulator_disable(info->vdd); regulator_disable(info->vdd);
@ -382,7 +458,8 @@ static int exynos_adc_remove(struct platform_device *pdev)
exynos_adc_remove_devices); exynos_adc_remove_devices);
iio_device_unregister(indio_dev); iio_device_unregister(indio_dev);
free_irq(info->irq, info); free_irq(info->irq, info);
writel(0, info->enable_reg); if (info->data->exit_hw)
info->data->exit_hw(info);
clk_disable_unprepare(info->clk); clk_disable_unprepare(info->clk);
regulator_disable(info->vdd); regulator_disable(info->vdd);
@ -394,19 +471,10 @@ static int exynos_adc_suspend(struct device *dev)
{ {
struct iio_dev *indio_dev = dev_get_drvdata(dev); struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct exynos_adc *info = iio_priv(indio_dev); struct exynos_adc *info = iio_priv(indio_dev);
u32 con;
if (info->version == ADC_V2) { if (info->data->exit_hw)
con = readl(ADC_V2_CON1(info->regs)); info->data->exit_hw(info);
con &= ~ADC_CON_EN_START;
writel(con, ADC_V2_CON1(info->regs));
} else {
con = readl(ADC_V1_CON(info->regs));
con |= ADC_V1_CON_STANDBY;
writel(con, ADC_V1_CON(info->regs));
}
writel(0, info->enable_reg);
clk_disable_unprepare(info->clk); clk_disable_unprepare(info->clk);
regulator_disable(info->vdd); regulator_disable(info->vdd);
@ -427,8 +495,8 @@ static int exynos_adc_resume(struct device *dev)
if (ret) if (ret)
return ret; return ret;
writel(1, info->enable_reg); if (info->data->init_hw)
exynos_adc_hw_init(info); info->data->init_hw(info);
return 0; return 0;
} }