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staging: iio: frequency: ad9834: Fix alignment for DMA safety 

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220807151218.656881-3-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-08-07 16:12:16 +01:00
parent 282d16b628
commit e48668a38b
1 changed files with 1 additions and 1 deletions
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2
drivers/staging/iio/frequency/ad9834.c
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@ -83,7 +83,7 @@ struct ad9834_state {
* DMA (thus cache coherency maintenance) requires the
* transfer buffers to live in their own cache lines.
*/
__be16 data ____cacheline_aligned;
__be16 data __aligned(IIO_DMA_MINALIGN);
__be16 freq_data[2];
};