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devicetree: bindings: Renesas APMU and SMP Enable method 

Add DT binding documentation for the APMU hardware and add "renesas,apmu"
to the list of enable methods for the ARM cpus.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Magnus Damm 2016-06-28 16:10:30 +02:00 committed by Simon Horman
parent 54389e981c
commit e454b359b7
2 changed files with 32 additions and 0 deletions
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1
Documentation/devicetree/bindings/arm/cpus.txt
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@ -204,6 +204,7 @@ nodes to be present and contain the properties described below.
"qcom,gcc-msm8660"
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
"renesas,apmu"
"rockchip,rk3036-smp"
"rockchip,rk3066-smp"
"ste,dbx500-smp"

31
Documentation/devicetree/bindings/power/renesas,apmu.txt Normal file
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@ -0,0 +1,31 @@
DT bindings for the Renesas Advanced Power Management Unit
Renesas R-Car line of SoCs utilize one or more APMU hardware units
for CPU core power domain control including SMP boot and CPU Hotplug.
Required properties:
- compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback.
Examples with soctypes are:
- "renesas,r8a7790-apmu" (R-Car H2)
- "renesas,r8a7791-apmu" (R-Car M2-W)
- "renesas,r8a7792-apmu" (R-Car V2H)
- "renesas,r8a7793-apmu" (R-Car M2-N)
- "renesas,r8a7794-apmu" (R-Car E2)
- reg: Base address and length of the I/O registers used by the APMU.
- cpus: This node contains a list of CPU cores, which should match the order
of CPU cores used by the WUPCR and PSTR registers in the Advanced Power
Management Unit section of the device's datasheet.
Example:
This shows the r8a7791 APMU that can control CPU0 and CPU1.
apmu@e6152000 {
compatible = "renesas,r8a7791-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
};