ASoC: fsl_sai: Configure dataline/FIFO information from dts property
The SAI has multiple successive FIFO registers, but in some use case the required dataline/FIFOs are not successive, so need get such information from dts property "fsl,dataline" fsl,dataline has 3 values for each configuration: first one means the type: I2S(1) or DSD(2), second one is dataline mask for 'rx', third one is dataline mask for 'tx'. Also set dma peripheral address and TRCE bits according to data lane. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Link: https://lore.kernel.org/r/1655451877-16382-8-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Shengjiu Wang
Mark Brown
parent
6b878ac271
commit
e3f4e5b1a3
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@ -487,13 +487,18 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
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unsigned int ofs = sai->soc_data->reg_offset;
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bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
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unsigned int channels = params_channels(params);
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struct snd_dmaengine_dai_dma_data *dma_params;
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struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg;
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u32 word_width = params_width(params);
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int trce_mask = 0, dl_cfg_idx = 0;
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int dl_cfg_cnt = sai->dl_cfg_cnt;
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u32 dl_type = FSL_SAI_DL_I2S;
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u32 val_cr4 = 0, val_cr5 = 0;
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u32 slots = (channels == 1) ? 2 : channels;
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u32 slot_width = word_width;
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int adir = tx ? RX : TX;
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u32 pins, bclk;
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int ret;
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int ret, i;
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if (sai->slots)
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slots = sai->slots;
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@ -507,8 +512,22 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
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* PDM mode, channels are independent
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* each channels are on one dataline/FIFO.
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*/
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if (sai->is_pdm_mode)
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if (sai->is_pdm_mode) {
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pins = channels;
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dl_type = FSL_SAI_DL_PDM;
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}
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for (i = 0; i < dl_cfg_cnt; i++) {
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if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) {
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dl_cfg_idx = i;
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break;
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}
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}
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if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) {
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dev_err(cpu_dai->dev, "channel not supported\n");
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return -EINVAL;
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}
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bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width);
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@ -571,13 +590,28 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
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FSL_SAI_CR5_FBT_MASK, val_cr5);
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}
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if (sai->soc_data->pins > 1)
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if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1)
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regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
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FSL_SAI_CR4_FCOMB_MASK, 0);
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else
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regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
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FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT);
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dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx;
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dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) +
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dl_cfg[dl_cfg_idx].start_off[tx] * 0x4;
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/* Find a proper tcre setting */
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for (i = 0; i < sai->soc_data->pins; i++) {
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trce_mask = (1 << (i + 1)) - 1;
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if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins)
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break;
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}
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regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
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FSL_SAI_CR3_TRCE_MASK,
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FSL_SAI_CR3_TRCE((1 << pins) - 1));
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FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask)));
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regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
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FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
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FSL_SAI_CR4_CHMOD_MASK,
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@ -1068,6 +1102,118 @@ static int fsl_sai_check_version(struct device *dev)
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return 0;
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}
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/*
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* Calculate the offset between first two datalines, don't
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* different offset in one case.
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*/
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static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask)
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{
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int fbidx, nbidx, offset;
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fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
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nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1);
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offset = nbidx - fbidx - 1;
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return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset);
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}
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/*
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* read the fsl,dataline property from dts file.
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* It has 3 value for each configuration, first one means the type:
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* I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is
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* dataline mask for 'tx'. for example
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*
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* fsl,dataline = <1 0xff 0xff 2 0xff 0x11>,
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*
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* It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type
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* rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled).
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*
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*/
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static int fsl_sai_read_dlcfg(struct fsl_sai *sai)
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{
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struct platform_device *pdev = sai->pdev;
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struct device_node *np = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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int ret, elems, i, index, num_cfg;
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char *propname = "fsl,dataline";
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struct fsl_sai_dl_cfg *cfg;
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unsigned long dl_mask;
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unsigned int soc_dl;
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u32 rx, tx, type;
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elems = of_property_count_u32_elems(np, propname);
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if (elems <= 0) {
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elems = 0;
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} else if (elems % 3) {
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dev_err(dev, "Number of elements must be divisible to 3.\n");
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return -EINVAL;
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}
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num_cfg = elems / 3;
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/* Add one more for default value */
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cfg = devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL);
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if (!cfg)
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return -ENOMEM;
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/* Consider default value "0 0xFF 0xFF" if property is missing */
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soc_dl = BIT(sai->soc_data->pins) - 1;
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cfg[0].type = FSL_SAI_DL_DEFAULT;
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cfg[0].pins[0] = sai->soc_data->pins;
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cfg[0].mask[0] = soc_dl;
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cfg[0].start_off[0] = 0;
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cfg[0].next_off[0] = 0;
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cfg[0].pins[1] = sai->soc_data->pins;
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cfg[0].mask[1] = soc_dl;
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cfg[0].start_off[1] = 0;
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cfg[0].next_off[1] = 0;
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for (i = 1, index = 0; i < num_cfg + 1; i++) {
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/*
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* type of dataline
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* 0 means default mode
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* 1 means I2S mode
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* 2 means PDM mode
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*/
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ret = of_property_read_u32_index(np, propname, index++, &type);
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if (ret)
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return -EINVAL;
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ret = of_property_read_u32_index(np, propname, index++, &rx);
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if (ret)
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return -EINVAL;
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ret = of_property_read_u32_index(np, propname, index++, &tx);
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if (ret)
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return -EINVAL;
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if ((rx & ~soc_dl) || (tx & ~soc_dl)) {
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dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl);
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return -EINVAL;
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}
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rx = rx & soc_dl;
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tx = tx & soc_dl;
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cfg[i].type = type;
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cfg[i].pins[0] = hweight8(rx);
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cfg[i].mask[0] = rx;
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dl_mask = rx;
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cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
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cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx);
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cfg[i].pins[1] = hweight8(tx);
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cfg[i].mask[1] = tx;
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dl_mask = tx;
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cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
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cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx);
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}
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sai->dl_cfg = cfg;
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sai->dl_cfg_cnt = num_cfg + 1;
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return 0;
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}
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static int fsl_sai_runtime_suspend(struct device *dev);
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static int fsl_sai_runtime_resume(struct device *dev);
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@ -1134,6 +1280,13 @@ static int fsl_sai_probe(struct platform_device *pdev)
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else
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sai->mclk_clk[0] = sai->bus_clk;
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/* read dataline mask for rx and tx*/
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ret = fsl_sai_read_dlcfg(sai);
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if (ret < 0) {
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dev_err(dev, "failed to read dlcfg %d\n", ret);
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return ret;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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@ -218,6 +218,13 @@
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#define PMQOS_CPU_LATENCY BIT(0)
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/* Max number of dataline */
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#define FSL_SAI_DL_NUM (8)
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/* default dataline type is zero */
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#define FSL_SAI_DL_DEFAULT (0)
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#define FSL_SAI_DL_I2S BIT(0)
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#define FSL_SAI_DL_PDM BIT(1)
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struct fsl_sai_soc_data {
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bool use_imx_pcm;
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bool use_edma;
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@ -253,6 +260,14 @@ struct fsl_sai_param {
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u32 dataline;
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};
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struct fsl_sai_dl_cfg {
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unsigned int type;
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unsigned int pins[2];
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unsigned int mask[2];
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unsigned int start_off[2];
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unsigned int next_off[2];
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};
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struct fsl_sai {
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struct platform_device *pdev;
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struct regmap *regmap;
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@ -265,6 +280,8 @@ struct fsl_sai {
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bool is_dsp_mode;
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bool is_pdm_mode;
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bool synchronous[2];
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struct fsl_sai_dl_cfg *dl_cfg;
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unsigned int dl_cfg_cnt;
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unsigned int mclk_id[2];
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unsigned int mclk_streams;
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