staging: ccree: fix white space style errors
Fix checkpatch reported white space style violations in cc_hw_queue_defs.h Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Gilad Ben-Yossef
Greg Kroah-Hartman
parent
8ca57f5cec
commit
e3f25f7990
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@ -23,10 +23,9 @@
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#include "dx_crys_kernel.h"
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/******************************************************************************
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* DEFINITIONS
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* DEFINITIONS
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******************************************************************************/
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/* Dma AXI Secure bit */
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#define AXI_SECURE 0
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#define AXI_NOT_SECURE 1
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@ -54,17 +53,17 @@ enum cc_desc_direction {
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enum cc_dma_mode {
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DMA_MODE_NULL = -1,
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NO_DMA = 0,
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NO_DMA = 0,
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DMA_SRAM = 1,
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DMA_DLLI = 2,
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DMA_MLLI = 3,
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DMA_MODE_END = S32_MAX,
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DMA_MODE_END = S32_MAX,
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};
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enum cc_flow_mode {
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FLOW_MODE_NULL = -1,
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/* data flows */
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BYPASS = 0,
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BYPASS = 0,
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DIN_AES_DOUT = 1,
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AES_to_HASH = 2,
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AES_and_HASH = 3,
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@ -84,11 +83,11 @@ enum cc_flow_mode {
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DIN_AES_AESMAC = 17,
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HASH_to_DOUT = 18,
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/* setup flows */
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S_DIN_to_AES = 32,
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S_DIN_to_AES = 32,
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S_DIN_to_AES2 = 33,
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S_DIN_to_DES = 34,
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S_DIN_to_RC4 = 35,
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S_DIN_to_MULTI2 = 36,
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S_DIN_to_MULTI2 = 36,
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S_DIN_to_HASH = 37,
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S_AES_to_DOUT = 38,
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S_AES2_to_DOUT = 39,
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@ -127,10 +126,9 @@ enum cc_aes_mac_selector {
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AES_MAC_END = S32_MAX,
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};
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#define HW_KEY_MASK_CIPHER_DO 0x3
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#define HW_KEY_MASK_CIPHER_DO 0x3
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#define HW_KEY_SHIFT_CIPHER_CFG2 2
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/* HwCryptoKey[1:0] is mapped to cipher_do[1:0] */
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/* HwCryptoKey[2:3] is mapped to cipher_config2[1:0] */
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enum cc_hw_crypto_key {
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@ -166,7 +164,7 @@ enum cc_hw_des_key_size {
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/* Descriptor packing macros */
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/*****************************/
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#define GET_HW_Q_DESC_WORD_IDX(descWordIdx) (CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD ## descWordIdx) )
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#define GET_HW_Q_DESC_WORD_IDX(descWordIdx) (CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD ## descWordIdx))
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#define HW_DESC_INIT(pDesc) memset(pDesc, 0, sizeof(struct cc_hw_desc))
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@ -175,7 +173,7 @@ enum cc_hw_des_key_size {
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*
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* \param pDesc pointer HW descriptor struct
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*/
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#define HW_DESC_SET_QUEUE_LAST_IND(pDesc) \
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#define HW_DESC_SET_QUEUE_LAST_IND(pDesc) \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, QUEUE_LAST_IND, (pDesc)->word[3], 1); \
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} while (0)
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@ -185,14 +183,13 @@ enum cc_hw_des_key_size {
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*
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* \param pDesc pointer HW descriptor struct
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*/
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#define HW_DESC_SET_ACK_LAST(pDesc) \
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#define HW_DESC_SET_ACK_LAST(pDesc) \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, QUEUE_LAST_IND, (pDesc)->word[3], 1); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, ACK_NEEDED, (pDesc)->word[4], 1); \
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} while (0)
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#define MSB64(_addr) (sizeof(_addr) == 4 ? 0 : ((_addr) >> 32)&U16_MAX)
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#define MSB64(_addr) (sizeof(_addr) == 4 ? 0 : ((_addr) >> 32) & U16_MAX)
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/*!
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* This macro sets the DIN field of a HW descriptors
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@ -204,15 +201,14 @@ enum cc_hw_des_key_size {
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* \param axiNs AXI secure bit
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*/
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#define HW_DESC_SET_DIN_TYPE(pDesc, dmaMode, dinAdr, dinSize, axiNs) \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (dinAdr)&U32_MAX ); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DIN_ADDR_HIGH, (pDesc)->word[5], MSB64(dinAdr) ); \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (dinAdr) & U32_MAX); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DIN_ADDR_HIGH, (pDesc)->word[5], MSB64(dinAdr)); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_DMA_MODE, (pDesc)->word[1], (dmaMode)); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize)); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, NS_BIT, (pDesc)->word[1], (axiNs)); \
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} while (0)
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/*!
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* This macro sets the DIN field of a HW descriptors to NO DMA mode. Used for NOP descriptor, register patches and
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* other special modes
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@ -222,7 +218,7 @@ enum cc_hw_des_key_size {
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* \param dinSize Data size in bytes
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*/
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#define HW_DESC_SET_DIN_NO_DMA(pDesc, dinAdr, dinSize) \
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do { \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (u32)(dinAdr)); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize)); \
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} while (0)
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@ -237,7 +233,7 @@ enum cc_hw_des_key_size {
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* \param dinSize Data size in bytes
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*/
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#define HW_DESC_SET_DIN_SRAM(pDesc, dinAdr, dinSize) \
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do { \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (u32)(dinAdr)); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_DMA_MODE, (pDesc)->word[1], DMA_SRAM); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize)); \
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@ -250,7 +246,7 @@ enum cc_hw_des_key_size {
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* \param dinSize Data size in bytes
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*/
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#define HW_DESC_SET_DIN_CONST(pDesc, val, dinSize) \
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do { \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (u32)(val)); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_CONST_VALUE, (pDesc)->word[1], 1); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_DMA_MODE, (pDesc)->word[1], DMA_SRAM); \
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@ -263,7 +259,7 @@ enum cc_hw_des_key_size {
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* \param pDesc pointer HW descriptor struct
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*/
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#define HW_DESC_SET_DIN_NOT_LAST_INDICATION(pDesc) \
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do { \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, NOT_LAST, (pDesc)->word[1], 1); \
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} while (0)
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@ -277,9 +273,9 @@ enum cc_hw_des_key_size {
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* \param axiNs AXI secure bit
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*/
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#define HW_DESC_SET_DOUT_TYPE(pDesc, dmaMode, doutAdr, doutSize, axiNs) \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&U32_MAX ); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr) ); \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr) & U32_MAX); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr)); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], (dmaMode)); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize)); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, NS_BIT, (pDesc)->word[3], (axiNs)); \
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@ -295,10 +291,10 @@ enum cc_hw_des_key_size {
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* \param lastInd The last indication bit
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* \param axiNs AXI secure bit
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*/
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#define HW_DESC_SET_DOUT_DLLI(pDesc, doutAdr, doutSize, axiNs ,lastInd) \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&U32_MAX ); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr) ); \
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#define HW_DESC_SET_DOUT_DLLI(pDesc, doutAdr, doutSize, axiNs, lastInd) \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr) & U32_MAX); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr)); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], DMA_DLLI); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize)); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_LAST_IND, (pDesc)->word[3], lastInd); \
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@ -315,10 +311,10 @@ enum cc_hw_des_key_size {
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* \param lastInd The last indication bit
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* \param axiNs AXI secure bit
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*/
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#define HW_DESC_SET_DOUT_MLLI(pDesc, doutAdr, doutSize, axiNs ,lastInd) \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&U32_MAX ); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr) ); \
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#define HW_DESC_SET_DOUT_MLLI(pDesc, doutAdr, doutSize, axiNs, lastInd) \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr) & U32_MAX); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr)); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], DMA_MLLI); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize)); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_LAST_IND, (pDesc)->word[3], lastInd); \
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@ -335,7 +331,7 @@ enum cc_hw_des_key_size {
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* \param registerWriteEnable Enables a write operation to a register
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*/
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#define HW_DESC_SET_DOUT_NO_DMA(pDesc, doutAdr, doutSize, registerWriteEnable) \
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do { \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (u32)(doutAdr)); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize)); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_LAST_IND, (pDesc)->word[3], (registerWriteEnable)); \
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@ -348,7 +344,7 @@ enum cc_hw_des_key_size {
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* \param xorVal xor data value
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*/
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#define HW_DESC_SET_XOR_VAL(pDesc, xorVal) \
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do { \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (u32)(xorVal)); \
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} while (0)
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@ -358,7 +354,7 @@ enum cc_hw_des_key_size {
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* \param pDesc pointer HW descriptor struct
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*/
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#define HW_DESC_SET_XOR_ACTIVE(pDesc) \
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do { \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, HASH_XOR_BIT, (pDesc)->word[3], 1); \
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} while (0)
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@ -368,7 +364,7 @@ enum cc_hw_des_key_size {
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* \param pDesc pointer HW descriptor struct
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*/
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#define HW_DESC_SET_AES_NOT_HASH_MODE(pDesc) \
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do { \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, AES_SEL_N_HASH, (pDesc)->word[4], 1); \
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} while (0)
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@ -382,13 +378,12 @@ enum cc_hw_des_key_size {
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* \param doutSize Data size in bytes
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*/
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#define HW_DESC_SET_DOUT_SRAM(pDesc, doutAdr, doutSize) \
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do { \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (u32)(doutAdr)); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], DMA_SRAM); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize)); \
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} while (0)
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/*!
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* This macro sets the data unit size for XEX mode in data_out_addr[15:0]
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*
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@ -464,8 +459,8 @@ enum cc_hw_des_key_size {
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*/
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#define HW_DESC_SET_HW_CRYPTO_KEY(pDesc, hwKey) \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_DO, (pDesc)->word[4], (hwKey)&HW_KEY_MASK_CIPHER_DO); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_CONF2, (pDesc)->word[4], (hwKey>>HW_KEY_SHIFT_CIPHER_CFG2)); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_DO, (pDesc)->word[4], (hwKey) & HW_KEY_MASK_CIPHER_DO); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_CONF2, (pDesc)->word[4], (hwKey >> HW_KEY_SHIFT_CIPHER_CFG2)); \
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} while (0)
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/*!
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@ -530,7 +525,7 @@ enum cc_hw_des_key_size {
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*/
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#define HW_DESC_SET_CIPHER_DO(pDesc, cipherDo) \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_DO, (pDesc)->word[4], (cipherDo)&HW_KEY_MASK_CIPHER_DO); \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_DO, (pDesc)->word[4], (cipherDo) & HW_KEY_MASK_CIPHER_DO); \
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} while (0)
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/*!
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@ -540,10 +535,9 @@ enum cc_hw_des_key_size {
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* \param pDesc pointer HW descriptor struct
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*/
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#define HW_DESC_SET_DIN_MONITOR_CNTR(pDesc) \
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do { \
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do { \
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CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_MEASURE_CNTR, VALUE, (pDesc)->word[1], _HW_DESC_MONITOR_KICK); \
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} while (0)
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#endif /*__CC_HW_QUEUE_DEFS_H__*/
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