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x86/cpufeatures: Force disable X86_FEATURE_ENQCMD and remove update_pasid() 

commit 9bfecd0583 upstream.

While digesting the XSAVE-related horrors which got introduced with
the supervisor/user split, the recent addition of ENQCMD-related
functionality got on the radar and turned out to be similarly broken.

update_pasid(), which is only required when X86_FEATURE_ENQCMD is
available, is invoked from two places:

 1) From switch_to() for the incoming task

 2) Via a SMP function call from the IOMMU/SMV code

#1 is half-ways correct as it hacks around the brokenness of get_xsave_addr()
   by enforcing the state to be 'present', but all the conditionals in that
   code are completely pointless for that.

   Also the invocation is just useless overhead because at that point
   it's guaranteed that TIF_NEED_FPU_LOAD is set on the incoming task
   and all of this can be handled at return to user space.

#2 is broken beyond repair. The comment in the code claims that it is safe
   to invoke this in an IPI, but that's just wishful thinking.

   FPU state of a running task is protected by fregs_lock() which is
   nothing else than a local_bh_disable(). As BH-disabled regions run
   usually with interrupts enabled the IPI can hit a code section which
   modifies FPU state and there is absolutely no guarantee that any of the
   assumptions which are made for the IPI case is true.

   Also the IPI is sent to all CPUs in mm_cpumask(mm), but the IPI is
   invoked with a NULL pointer argument, so it can hit a completely
   unrelated task and unconditionally force an update for nothing.
   Worse, it can hit a kernel thread which operates on a user space
   address space and set a random PASID for it.

The offending commit does not cleanly revert, but it's sufficient to
force disable X86_FEATURE_ENQCMD and to remove the broken update_pasid()
code to make this dysfunctional all over the place. Anything more
complex would require more surgery and none of the related functions
outside of the x86 core code are blatantly wrong, so removing those
would be overkill.

As nothing enables the PASID bit in the IA32_XSS MSR yet, which is
required to make this actually work, this cannot result in a regression
except for related out of tree train-wrecks, but they are broken already
today.

Fixes: 20f0afd1fb ("x86/mmu: Allocate/free a PASID")
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Andy Lutomirski <luto@kernel.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/87mtsd6gr9.ffs@nanos.tec.linutronix.de
Signed-off-by: Chen Zhuo <sagazchen@tencent.com>
Signed-off-by: Xinghui Li <korantli@tencent.com>
This commit is contained in:
Thomas Gleixner 2021-05-29 11:17:30 +02:00 committed by Jianping Liu
parent 222998a338
commit e3a809b495
5 changed files with 70 additions and 74 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
arch/x86/include/asm/disabled-features.h
View File

@ -62,11 +62,8 @@
# define DISABLE_PTI (1 << (X86_FEATURE_PTI & 31))
#endif
#ifdef CONFIG_IOMMU_SUPPORT
# define DISABLE_ENQCMD 0
#else
# define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31))
#endif
/* Force disable because it's broken beyond repair */
#define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31))
#ifdef CONFIG_X86_SGX
# define DISABLE_SGX 0

6
arch/x86/include/asm/fpu/api.h
View File

@ -79,10 +79,6 @@ extern int cpu_has_xfeatures(u64 xfeatures_mask, const char **feature_name);
*/
#define PASID_DISABLED 0
#ifdef CONFIG_IOMMU_SUPPORT
/* Update current's PASID MSR/state by mm's PASID. */
void update_pasid(void);
#else
static inline void update_pasid(void) { }
#endif
#endif /* _ASM_X86_FPU_API_H */

7
arch/x86/include/asm/fpu/internal.h
View File

@ -569,13 +569,6 @@ static inline void switch_fpu_finish(struct fpu *new_fpu)
pkru_val = pk->pkru;
}
__write_pkru(pkru_val);
/*
* Expensive PASID MSR write will be avoided in update_pasid() because
* TIF_NEED_FPU_LOAD was set. And the PASID state won't be updated
* unless it's different from mm->pasid to reduce overhead.
*/
update_pasid();
}
/*

57
arch/x86/kernel/fpu/xstate.c
View File

@ -1434,60 +1434,3 @@ int proc_pid_arch_status(struct seq_file *m, struct pid_namespace *ns,
return 0;
}
#endif /* CONFIG_PROC_PID_ARCH_STATUS */
#ifdef CONFIG_IOMMU_SUPPORT
void update_pasid(void)
{
u64 pasid_state;
u32 pasid;
if (!cpu_feature_enabled(X86_FEATURE_ENQCMD))
return;
if (!current->mm)
return;
pasid = READ_ONCE(current->mm->pasid);
/* Set the valid bit in the PASID MSR/state only for valid pasid. */
pasid_state = pasid == PASID_DISABLED ?
pasid : pasid | MSR_IA32_PASID_VALID;
/*
* No need to hold fregs_lock() since the task's fpstate won't
* be changed by others (e.g. ptrace) while the task is being
* switched to or is in IPI.
*/
if (!test_thread_flag(TIF_NEED_FPU_LOAD)) {
/* The MSR is active and can be directly updated. */
wrmsrl(MSR_IA32_PASID, pasid_state);
} else {
struct fpu *fpu = &current->thread.fpu;
struct ia32_pasid_state *ppasid_state;
struct xregs_state *xsave;
/*
* The CPU's xstate registers are not currently active. Just
* update the PASID state in the memory buffer here. The
* PASID MSR will be loaded when returning to user mode.
*/
xsave = &fpu->state.xsave;
xsave->header.xfeatures |= XFEATURE_MASK_PASID;
ppasid_state = get_xsave_addr(xsave, XFEATURE_PASID);
/*
* Since XFEATURE_MASK_PASID is set in xfeatures, ppasid_state
* won't be NULL and no need to check its value.
*
* Only update the task's PASID state when it's different
* from the mm's pasid.
*/
if (ppasid_state->pasid != pasid_state) {
/*
* Invalid fpregs so that state restoring will pick up
* the PASID state.
*/
__fpu_invalidate_fpregs_state(fpu);
ppasid_state->pasid = pasid_state;
}
}
}
#endif /* CONFIG_IOMMU_SUPPORT */

67
mm/memory.c
View File

@ -4325,6 +4325,73 @@ int follow_pte(struct mm_struct *mm, unsigned long address,
}
EXPORT_SYMBOL_GPL(follow_pte);
int follow_pte_pud_lockless(struct mm_struct *mm, unsigned long address,
pte_t *ptep, pmd_t *pmdp, pud_t *pudp)
{
pgd_t *pgd, pgdval;
p4d_t *p4d, p4dval;
pud_t *pud, pudval;
pmd_t *pmd, pmdval;
pte_t *pte, pteval;
pgd = pgd_offset(mm, address);
pgdval = *pgd;
if (pgd_none(pgdval) || unlikely(pgd_bad(pgdval)))
goto out;
p4d = p4d_offset(&pgdval, address);
p4dval = *p4d;
if (p4d_none(p4dval) || unlikely(p4d_bad(p4dval)))
goto out;
pud = pud_offset(&p4dval, address);
pudval = *pud;
if (!pud_present(pudval))
goto out;
BUG_ON(pud_trans_huge(pudval));
if (pud_huge(pudval)) {
if (!pudp)
goto out;
*pudp = pudval;
return 0;
}
if (pud_none(pudval) || unlikely(pud_bad(pudval)))
goto out;
pmd = pmd_offset(&pudval, address);
pmdval = *pmd;
if (!pmd_present(pmdval))
goto out;
BUG_ON(pmd_trans_huge(pmdval));
if (pmd_huge(pmdval)) {
if (!pmdp)
goto out;
*pmdp = pmdval;
return 0;
}
if (pmd_none(pmdval) || unlikely(pmd_bad(pmdval)))
goto out;
pte = pte_offset_map(&pmdval, address);
if (!pte)
goto out;
pteval = *pte;
pte_unmap(pte);
if (!pte_present(pteval))
goto out;
*ptep = pteval;
return 0;
out:
return -EINVAL;
}
EXPORT_SYMBOL(follow_pte_pud_lockless);
/**
* follow_pfn - look up PFN at a user virtual address
* @vma: memory mapping