iwlwifi: document 4965 Tx scheduler
Document 4965 Tx scheduler Signed-off-by: Ben Cahill <ben.m.cahill@intel.com> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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Ben Cahill
David S. Miller
parent
5d5456fe50
commit
e385144766
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@ -1554,33 +1554,285 @@ enum {
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IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl))
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/********************* START TX SCHEDULER *************************************/
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/**
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* 4965 Tx Scheduler
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*
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* The Tx Scheduler selects the next frame to be transmitted, chosing TFDs
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* (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
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* host DRAM. It steers each frame's Tx command (which contains the frame
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* data) into one of up to 7 prioritized Tx DMA FIFO channels within the
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* device. A queue maps to only one (selectable by driver) Tx DMA channel,
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* but one DMA channel may take input from several queues.
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*
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* Tx DMA channels have dedicated purposes. For 4965, they are used as follows:
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*
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* 0 -- EDCA BK (background) frames, lowest priority
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* 1 -- EDCA BE (best effort) frames, normal priority
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* 2 -- EDCA VI (video) frames, higher priority
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* 3 -- EDCA VO (voice) and management frames, highest priority
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* 4 -- Commands (e.g. RXON, etc.)
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* 5 -- HCCA short frames
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* 6 -- HCCA long frames
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* 7 -- not used by driver (device-internal only)
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*
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* Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
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* In addition, driver can map queues 7-15 to Tx DMA/FIFO channels 0-3 to
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* support 11n aggregation via EDCA DMA channels.
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*
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* The driver sets up each queue to work in one of two modes:
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*
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* 1) Scheduler-Ack, in which the scheduler automatically supports a
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* block-ack (BA) window of up to 64 TFDs. In this mode, each queue
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* contains TFDs for a unique combination of Recipient Address (RA)
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* and Traffic Identifier (TID), that is, traffic of a given
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* Quality-Of-Service (QOS) priority, destined for a single station.
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*
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* In scheduler-ack mode, the scheduler keeps track of the Tx status of
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* each frame within the BA window, including whether it's been transmitted,
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* and whether it's been acknowledged by the receiving station. The device
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* automatically processes block-acks received from the receiving STA,
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* and reschedules un-acked frames to be retransmitted (successful
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* Tx completion may end up being out-of-order).
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*
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* The driver must maintain the queue's Byte Count table in host DRAM
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* (struct iwl4965_sched_queue_byte_cnt_tbl) for this mode.
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* This mode does not support fragmentation.
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*
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* 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
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* The device may automatically retry Tx, but will retry only one frame
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* at a time, until receiving ACK from receiving station, or reaching
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* retry limit and giving up.
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*
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* The command queue (#4) must use this mode!
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* This mode does not require use of the Byte Count table in host DRAM.
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*
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* Driver controls scheduler operation via 3 means:
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* 1) Scheduler registers
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* 2) Shared scheduler data base in internal 4956 SRAM
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* 3) Shared data in host DRAM
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*
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* Initialization:
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*
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* When loading, driver should allocate memory for:
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* 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
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* 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
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* (1024 bytes for each queue).
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*
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* After receiving "Alive" response from uCode, driver must initialize
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* the scheduler (especially for queue #4, the command queue, otherwise
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* the driver can't issue commands!):
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*/
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/**
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* Max Tx window size is the max number of contiguous TFDs that the scheduler
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* can keep track of at one time when creating block-ack chains of frames.
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* Note that "64" matches the number of ack bits in a block-ack packet.
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* Driver should use SCD_WIN_SIZE and SCD_FRAME_LIMIT values to initialize
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* SCD_CONTEXT_QUEUE_OFFSET(x) values.
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*/
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#define SCD_WIN_SIZE 64
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#define SCD_FRAME_LIMIT 64
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/* SRAM structures */
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#define SCD_CONTEXT_DATA_OFFSET 0x380
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#define SCD_TX_STTS_BITMAP_OFFSET 0x400
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#define SCD_TRANSLATE_TBL_OFFSET 0x500
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#define SCD_CONTEXT_QUEUE_OFFSET(x) (SCD_CONTEXT_DATA_OFFSET + ((x) * 8))
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#define SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
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((SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc)
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/* SCD registers are internal, must be accessed via HBUS_TARG_PRPH regs */
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#define SCD_START_OFFSET 0xa02c00
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/*
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* 4965 tells driver SRAM address for internal scheduler structs via this reg.
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* Value is valid only after "Alive" response from uCode.
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*/
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#define SCD_SRAM_BASE_ADDR (SCD_START_OFFSET + 0x0)
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/*
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* Driver may need to update queue-empty bits after changing queue's
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* write and read pointers (indexes) during (re-)initialization (i.e. when
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* scheduler is not tracking what's happening).
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* Bit fields:
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* 31-16: Write mask -- 1: update empty bit, 0: don't change empty bit
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* 15-00: Empty state, one for each queue -- 1: empty, 0: non-empty
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* NOTE: This register is not used by Linux driver.
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*/
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#define SCD_EMPTY_BITS (SCD_START_OFFSET + 0x4)
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/*
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* Physical base address of array of byte count (BC) circular buffers (CBs).
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* Each Tx queue has a BC CB in host DRAM to support Scheduler-ACK mode.
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* This register points to BC CB for queue 0, must be on 1024-byte boundary.
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* Others are spaced by 1024 bytes.
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* Each BC CB is 2 bytes * (256 + 64) = 740 bytes, followed by 384 bytes pad.
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* (Index into a queue's BC CB) = (index into queue's TFD CB) = (SSN & 0xff).
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* Bit fields:
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* 25-00: Byte Count CB physical address [35:10], must be 1024-byte aligned.
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*/
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#define SCD_DRAM_BASE_ADDR (SCD_START_OFFSET + 0x10)
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/*
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* Enables any/all Tx DMA/FIFO channels.
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* Scheduler generates requests for only the active channels.
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* Set this to 0xff to enable all 8 channels (normal usage).
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* Bit fields:
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* 7- 0: Enable (1), disable (0), one bit for each channel 0-7
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*/
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#define SCD_TXFACT (SCD_START_OFFSET + 0x1c)
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/* Mask to enable contiguous Tx DMA/FIFO channels between "lo" and "hi". */
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#define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \
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((1<<(hi))|((1<<(hi))-(1<<(lo))))
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/*
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* Queue (x) Write Pointers (indexes, really!), one for each Tx queue.
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* Initialized and updated by driver as new TFDs are added to queue.
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* NOTE: If using Block Ack, index must correspond to frame's
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* Start Sequence Number; index = (SSN & 0xff)
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* NOTE: Alternative to HBUS_TARG_WRPTR, which is what Linux driver uses?
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*/
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#define SCD_QUEUE_WRPTR(x) (SCD_START_OFFSET + 0x24 + (x) * 4)
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/*
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* Queue (x) Read Pointers (indexes, really!), one for each Tx queue.
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* For FIFO mode, index indicates next frame to transmit.
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* For Scheduler-ACK mode, index indicates first frame in Tx window.
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* Initialized by driver, updated by scheduler.
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*/
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#define SCD_QUEUE_RDPTR(x) (SCD_START_OFFSET + 0x64 + (x) * 4)
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/*
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* Select which queues work in chain mode (1) vs. not (0).
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* Use chain mode to build chains of aggregated frames.
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* Bit fields:
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* 31-16: Reserved
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* 15-00: Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time
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* NOTE: If driver sets up queue for chain mode, it should be also set up
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* Scheduler-ACK mode as well, via SCD_QUEUE_STATUS_BITS(x).
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*/
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#define SCD_QUEUECHAIN_SEL (SCD_START_OFFSET + 0xd0)
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/*
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* Select which queues interrupt driver when scheduler increments
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* a queue's read pointer (index).
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* Bit fields:
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* 31-16: Reserved
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* 15-00: Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled
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* NOTE: This functionality is apparently a no-op; driver relies on interrupts
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* from Rx queue to read Tx command responses and update Tx queues.
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*/
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#define SCD_INTERRUPT_MASK (SCD_START_OFFSET + 0xe4)
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/*
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* Queue search status registers. One for each queue.
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* Sets up queue mode and assigns queue to Tx DMA channel.
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* Bit fields:
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* 19-10: Write mask/enable bits for bits 0-9
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* 9: Driver should init to "0"
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* 8: Scheduler-ACK mode (1), non-Scheduler-ACK (i.e. FIFO) mode (0).
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* Driver should init to "1" for aggregation mode, or "0" otherwise.
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* 7-6: Driver should init to "0"
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* 5: Window Size Left; indicates whether scheduler can request
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* another TFD, based on window size, etc. Driver should init
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* this bit to "1" for aggregation mode, or "0" for non-agg.
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* 4-1: Tx FIFO to use (range 0-7).
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* 0: Queue is active (1), not active (0).
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* Other bits should be written as "0"
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*
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* NOTE: If enabling Scheduler-ACK mode, chain mode should also be enabled
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* via SCD_QUEUECHAIN_SEL.
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*/
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#define SCD_QUEUE_STATUS_BITS(x) (SCD_START_OFFSET + 0x104 + (x) * 4)
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/* Bit field positions */
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#define SCD_QUEUE_STTS_REG_POS_ACTIVE (0)
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#define SCD_QUEUE_STTS_REG_POS_TXF (1)
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#define SCD_QUEUE_STTS_REG_POS_WSL (5)
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#define SCD_QUEUE_STTS_REG_POS_SCD_ACK (8)
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/* Write masks */
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#define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10)
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#define SCD_QUEUE_STTS_REG_MSK (0x0007FC00)
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/**
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* 4965 internal SRAM structures for scheduler, shared with driver ...
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*
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* Driver should clear and initialize the following areas after receiving
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* "Alive" response from 4965 uCode, i.e. after initial
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* uCode load, or after a uCode load done for error recovery:
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*
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* SCD_CONTEXT_DATA_OFFSET (size 128 bytes)
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* SCD_TX_STTS_BITMAP_OFFSET (size 256 bytes)
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* SCD_TRANSLATE_TBL_OFFSET (size 32 bytes)
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*
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* Driver accesses SRAM via HBUS_TARG_MEM_* registers.
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* Driver reads base address of this scheduler area from SCD_SRAM_BASE_ADDR.
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* All OFFSET values must be added to this base address.
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*/
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/*
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* Queue context. One 8-byte entry for each of 16 queues.
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*
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* Driver should clear this entire area (size 0x80) to 0 after receiving
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* "Alive" notification from uCode. Additionally, driver should init
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* each queue's entry as follows:
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*
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* LS Dword bit fields:
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* 0-06: Max Tx window size for Scheduler-ACK. Driver should init to 64.
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*
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* MS Dword bit fields:
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* 16-22: Frame limit. Driver should init to 10 (0xa).
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*
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* Driver should init all other bits to 0.
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*
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* Init must be done after driver receives "Alive" response from 4965 uCode,
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* and when setting up queue for aggregation.
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*/
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#define SCD_CONTEXT_DATA_OFFSET 0x380
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#define SCD_CONTEXT_QUEUE_OFFSET(x) (SCD_CONTEXT_DATA_OFFSET + ((x) * 8))
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#define SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0)
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#define SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F)
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#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
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#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
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/*
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* Tx Status Bitmap
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*
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* Driver should clear this entire area (size 0x100) to 0 after receiving
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* "Alive" notification from uCode. Area is used only by device itself;
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* no other support (besides clearing) is required from driver.
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*/
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#define SCD_TX_STTS_BITMAP_OFFSET 0x400
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/*
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* RAxTID to queue translation mapping.
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*
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* When queue is in Scheduler-ACK mode, frames placed in a that queue must be
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* for only one combination of receiver address (RA) and traffic ID (TID), i.e.
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* one QOS priority level destined for one station (for this wireless link,
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* not final destination). The SCD_TRANSLATE_TABLE area provides 16 16-bit
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* mappings, one for each of the 16 queues. If queue is not in Scheduler-ACK
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* mode, the device ignores the mapping value.
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*
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* Bit fields, for each 16-bit map:
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* 15-9: Reserved, set to 0
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* 8-4: Index into device's station table for recipient station
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* 3-0: Traffic ID (tid), range 0-15
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*
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* Driver should clear this entire area (size 32 bytes) to 0 after receiving
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* "Alive" notification from uCode. To update a 16-bit map value, driver
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* must read a dword-aligned value from device SRAM, replace the 16-bit map
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* value of interest, and write the dword value back into device SRAM.
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*/
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#define SCD_TRANSLATE_TBL_OFFSET 0x500
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/* Find translation table dword to read/write for given queue */
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#define SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
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((SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc)
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#define SCD_TXFIFO_POS_TID (0)
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#define SCD_TXFIFO_POS_RA (4)
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#define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
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/*********************** END TX SCHEDULER *************************************/
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static inline u8 iwl4965_hw_get_rate(__le32 rate_n_flags)
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{
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return le32_to_cpu(rate_n_flags) & 0xFF;
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@ -63,7 +63,10 @@
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#ifndef __iwl_prph_h__
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#define __iwl_prph_h__
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/*
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* Registers in this file are internal, not PCI bus memory mapped.
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* Driver accesses these via HBUS_TARG_PRPH_* registers.
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*/
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#define PRPH_BASE (0x00000)
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#define PRPH_END (0xFFFFF)
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@ -225,8 +228,8 @@
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#define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800)
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#define BSM_SRAM_SIZE (1024) /* bytes */
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/* ALM SCD */
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/* SCD (Scheduler) */
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/* 3945 Tx scheduler registers */
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#define ALM_SCD_BASE (PRPH_BASE + 0x2E00)
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#define ALM_SCD_MODE_REG (ALM_SCD_BASE + 0x000)
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#define ALM_SCD_ARASTAT_REG (ALM_SCD_BASE + 0x004)
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@ -236,7 +239,10 @@
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#define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C)
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#define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030)
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/* 4965 SCD memory mapped registers */
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/*
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* 4965 Tx Scheduler registers.
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* Details are documented in iwl-4965-hw.h
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*/
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#define KDR_SCD_BASE (PRPH_BASE + 0xa02c00)
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#define KDR_SCD_SRAM_BASE_ADDR (KDR_SCD_BASE + 0x0)
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@ -201,6 +201,8 @@ static void iwl4965_print_hex_dump(int level, void *p, u32 len)
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* The 4965 operates with up to 17 queues: One receive queue, one transmit
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* queue (#4) for sending commands to the device firmware, and 15 other
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* Tx queues that may be mapped to prioritized Tx DMA/FIFO channels.
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*
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* See more detailed info in iwl-4965-hw.h.
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***************************************************/
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static int iwl4965_queue_space(const struct iwl4965_queue *q)
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