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drm/i915/dsi: move dsi pll modeset asserts to vlv_dsi_pll.c 

Keep the functionality and the assert code together.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/0a5fa9b8d4d4615d4e6503b6bb33541c0bccffbb.1632992608.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula 2021-09-30 12:23:01 +03:00
parent 80e77e30a2
commit e365e4aaa5
5 changed files with 27 additions and 19 deletions
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1
drivers/gpu/drm/i915/display/intel_color.c
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@ -26,6 +26,7 @@
#include "intel_de.h" #include "intel_de.h"
#include "intel_display_types.h" #include "intel_display_types.h"
#include "intel_dpll.h" #include "intel_dpll.h"
#include "intel_dsi.h"
#define CTM_COEFF_SIGN (1ULL << 63) #define CTM_COEFF_SIGN (1ULL << 63)

16
drivers/gpu/drm/i915/display/intel_display.c
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@ -398,22 +398,6 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
} }
} }
/* XXX: the dsi pll is shared between MIPI DSI ports */
void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
{
u32 val;
bool cur_state;
vlv_cck_get(dev_priv);
val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
vlv_cck_put(dev_priv);
cur_state = val & DSI_PLL_VCO_EN;
I915_STATE_WARN(cur_state != state,
"DSI PLL state assertion failure (expected %s, current %s)\n",
onoff(state), onoff(cur_state));
}
void assert_transcoder(struct drm_i915_private *dev_priv, void assert_transcoder(struct drm_i915_private *dev_priv,
enum transcoder cpu_transcoder, bool state) enum transcoder cpu_transcoder, bool state)
{ {

3
drivers/gpu/drm/i915/display/intel_display.h
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@ -645,9 +645,6 @@ void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
int intel_modeset_all_pipes(struct intel_atomic_state *state); int intel_modeset_all_pipes(struct intel_atomic_state *state);
/* modesetting asserts */ /* modesetting asserts */
void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
void assert_transcoder(struct drm_i915_private *dev_priv, void assert_transcoder(struct drm_i915_private *dev_priv,
enum transcoder cpu_transcoder, bool state); enum transcoder cpu_transcoder, bool state);
#define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true) #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)

3
drivers/gpu/drm/i915/display/intel_dsi.h
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@ -207,6 +207,9 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
struct intel_crtc_state *config); struct intel_crtc_state *config);
void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port); void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
void assert_dsi_pll_enabled(struct drm_i915_private *i915);
void assert_dsi_pll_disabled(struct drm_i915_private *i915);
/* intel_dsi_vbt.c */ /* intel_dsi_vbt.c */
bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id); bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on); void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on);

23
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
View File

@ -568,3 +568,26 @@ void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
} }
intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);
} }
static void assert_dsi_pll(struct drm_i915_private *i915, bool state)
{
bool cur_state;
vlv_cck_get(i915);
cur_state = vlv_cck_read(i915, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN;
vlv_cck_put(i915);
I915_STATE_WARN(cur_state != state,
"DSI PLL state assertion failure (expected %s, current %s)\n",
onoff(state), onoff(cur_state));
}
void assert_dsi_pll_enabled(struct drm_i915_private *i915)
{
assert_dsi_pll(i915, true);
}
void assert_dsi_pll_disabled(struct drm_i915_private *i915)
{
assert_dsi_pll(i915, false);
}