MIPS: KVM: Report more accurate CP0_Config fields to guest
Initialise the guest's CP0_Config register with a few more bits of information from the host. The BE bit should be set on big endian machines, the VI bit should be set on machines with a virtually tagged instruction cache, and the reported architecture revision should match that of the host (since we won't support emulating pre-r6 instruction encodings on r6 or vice versa). Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -426,7 +426,7 @@ static int kvm_trap_emul_vcpu_init(struct kvm_vcpu *vcpu)
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static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu)
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{
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struct mips_coproc *cop0 = vcpu->arch.cop0;
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u32 config1;
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u32 config, config1;
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int vcpu_id = vcpu->vcpu_id;
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/*
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@ -434,10 +434,20 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu)
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* guest will come up as expected, for now we simulate a MIPS 24kc
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*/
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kvm_write_c0_guest_prid(cop0, 0x00019300);
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/* Have config1, Cacheable, noncoherent, write-back, write allocate */
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kvm_write_c0_guest_config(cop0, MIPS_CONF_M | (0x3 << CP0C0_K0) |
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(0x1 << CP0C0_AR) |
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(MMU_TYPE_R4000 << CP0C0_MT));
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/*
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* Have config1, Cacheable, noncoherent, write-back, write allocate.
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* Endianness, arch revision & virtually tagged icache should match
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* host.
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*/
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config = read_c0_config() & MIPS_CONF_AR;
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config |= MIPS_CONF_M | (0x3 << CP0C0_K0) |
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(MMU_TYPE_R4000 << CP0C0_MT);
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#ifdef CONFIG_CPU_BIG_ENDIAN
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config |= CONF_BE;
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#endif
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if (cpu_has_vtag_icache)
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config |= MIPS_CONF_VI;
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kvm_write_c0_guest_config(cop0, config);
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/* Read the cache characteristics from the host Config1 Register */
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config1 = (read_c0_config1() & ~0x7f);
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