ARM: dts: Fix up the IXP4xx ethernet nodes

All of IXP4xx SoCs has an EthA at 0xc800c000 so move this
from the IXP[56]x to the IXP4xx DTSI.

Then add the second ethernet port on the Cambria GW2358-4
on EthA.

Reported-by: Zoltan HERPAI <wigyori@uid0.hu>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts

@@ -153,7 +153,20 @@
 				phy1: ethernet-phy@1 {
 					reg = <1>;
 				};
+
+				phy2: ethernet-phy@2 {
+					reg = <2>;
+				};
 			};
 		};
+
+		ethernet@c800c000 {
+			status = "ok";
+			queue-rx = <&qmgr 2>;
+			queue-txready = <&qmgr 19>;
+			phy-mode = "rgmii";
+			phy-handle = <&phy2>;
+			intel,npe-handle = <&npe 0>;
+		};
 	};
 };

arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi

@@ -31,17 +31,6 @@
 			status = "disabled";
 		};
 
-		/* This is known as EthA */
-		ethernet@c800c000 {
-			compatible = "intel,ixp4xx-ethernet";
-			reg = <0xc800c000 0x1000>;
-			status = "disabled";
-			intel,npe = <0>;
-			/* Dummy values that depend on firmware */
-			queue-rx = <&qmgr 0>;
-			queue-txready = <&qmgr 0>;
-		};
-
 		/* This is known as EthB1 */
 		ethernet@c800d000 {
 			compatible = "intel,ixp4xx-ethernet";

arch/arm/boot/dts/intel-ixp4xx.dtsi

@@ -136,5 +136,16 @@
 			queue-txready = <&qmgr 0>;
 			intel,npe-handle = <&npe 2>;
 		};
+
+		/* This is known as EthA */
+		ethernet@c800c000 {
+			compatible = "intel,ixp4xx-ethernet";
+			reg = <0xc800c000 0x1000>;
+			status = "disabled";
+			intel,npe = <0>;
+			/* Dummy values that depend on firmware */
+			queue-rx = <&qmgr 0>;
+			queue-txready = <&qmgr 0>;
+		};
 	};
 };